Document Outline
- FEATURES
- DESCRIPTION
- ORDERING INFORMATION
- PIN CONFIGURATION
- PIN DESCRIPTION
- BLOCK DIAGRAM
- FUNCTION TABLE
- CLOCK ENABLE CONFIGURATION
- POWER MANAGEMENT REQUIREMENTS
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- POWER MANAGEMENT
- DC CHARACTERISTICS
- AC CHARACTERISTICS
- AC WAVEFORMS
- PACKAGE
- Data sheet status
- Definitions
- Disclaimers
Philips
Semiconductors
PCK2010RA
CK98R (100/133MHz) RCC spread
spectrum system clock generator
Product specification
Supersedes data of 2000 Dec 01
ICL03 -- PC Motherboard ICs; Logic Products Group
2001 Apr 02
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
PCK2010RA
CK98R (100/133MHz) RCC spread spectrum
system clock generator
2
2001 Apr 02
8532232 25964
FEATURES
·
Mixed 2.5 V and 3.3 V operation
·
Four CPU clocks at 2.5 V
·
Eight PCI clocks at 3.3 V, one free-running
(synchronous with CPU clocks)
·
Four 3.3 V fixed clocks @ 66 MHz
·
Two 2.5 V CPUDIV2 clocks @
1
/
2
CPU clock frequency
·
Three 2.5 V IOAPIC clocks @ 16.67 MHz
·
One 3.3 V 48 MHz USB clock
·
Two 3.3 V reference clocks @ 14.318 MHz
·
Reference 14.31818 MHz Xtal oscillator input
·
133 MHz or 100 MHz operation, 133.01 MHz in 133 mode
·
Power management control input pins
·
CPU clock jitter
250 ps cycle-cycle
·
CPU clock skew
175 ps pin-pin
·
0.0 ns 1.5 ns CPU3V66 delay
·
1.5 ns 3.5 ns 3V66PCI delay
·
1.5 ns 4.0 ns CPUIOAPIC delay
·
1.5 ns 4.0 ns CPUPCI delay
·
Available in 56-pin SSOP package
·
±
0.6% center spread spectrum capability via select pins
·
0.6% down spread spectrum capability via select pins
DESCRIPTION
The PCK2010RA is a clock generator (frequency synthesizer) chip
for a Pentium II and other similar processors.
The PCK2010RA has four CPU clock outputs at 2.5 V, two
CPUDIV2 clock outputs running at
1
/
2
CPU clock frequency
(66 MHz or 50 MHz depending on the state of SEL133/100) and four
3V66 clocks running at 66MHz. There are eight PCI clock outputs
running at 33 MHz. One of the PCI clock outputs is free-running.
Additionally, the part has three 2.5 V IOAPIC clock outputs at
16.67 MHz and two 3.3 V reference clock outputs at 14.318 MHz. All
clock outputs meet Intel's drive strength, rise/fall time, jitter,
accuracy, and skew requirements.
The part possesses dedicated power-down, CPUSTOP, and
PCISTOP input pins for power management control. These inputs
are synchronized on-chip and ensure glitch-free output transitions.
When the CPUSTOP input is asserted, the CPU clock outputs and
3V66 clock outputs are driven LOW. When the PCISTOP input is
asserted, the PCI clock outputs are driven LOW.
Finally, when the PWRDWN input pin is asserted, the internal
reference oscillator and PLLs are shut down, and all outputs are
driven LOW.
PIN CONFIGURATION
SW00892
1
2
3
4
5
6
7
8
9
10
11
12
45
46
47
48
49
50
51
52
53
54
55
56
V
SS
REF1
V
DD
3V
XTAL_IN
XTAL_OUT
V
SS
PCICLK_F
PCICLK1
V
DD
3V
PCICLK2
CPUCLK0
V
SS
CPUCLK1
V
DD
3V
CPUCLK2
PCICLK3
13
14
15
16
17
18
39
40
41
42
43
44
V
SS
PCICLK4
PCICLK5
V
DD
3V
PCICLK6
CPUCLK3
PCICLK7
19
38
V
SS
20
21
22
23
24
25
32
33
34
35
36
37
V
DD
3V
3V66_0
3V66_1
SEL1
SEL0
V
SS
26
31
27
30
48MHz_USB
28
29
SEl133/100
REF0
V
SS
3V66_2
3V66_3
V
DD
3V
V
DD
25V
APIC2
APIC1
APIC0
V
DD
25V
CPUDIV2_1
CPUDIV2_0
V
SS
V
DD
25V
V
SS
V
DD
25V
V
SS
V
SS
PCISTOP
CPUSTOP
PWRDWN
SPREAD
V
DD
3V
V
SS
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
56-Pin plastic SSOP
0 to +70
°
C
PCK2010RADL
SOT371-1
Intel and Pentium are registered trademarks of Intel Corporation.
Philips Semiconductors
Product specification
PCK2010RA
CK98R (100/133MHz) RCC spread spectrum
system clock generator
2001 Apr 02
3
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
2,3
REF [01]
3.3 V 14.318 MHz clock output
5
XTAL_IN
14.318 MHz crystal input
6
XTAL_OUT
14.318 MHz crystal output
8
PCICLK_F
3.3 V free running PCI clock
9, 11, 12, 14, 15, 17, 18
PCICLK [17]
3.3 V PCI clock outputs
21, 22, 25, 26
3V66 [03]
3.3 V fixed 66 MHz clock outputs
28
SEL133/100
Select input pin for enabling 133 MHz or 100 MHz CPU outputs.
H = 133 MHz, L = 100 MHz
30
48 MHz USB
3.3 V fixed 48 MHZ clock output
32, 33
SEL [01]
Logic select pins. TTL levels.
34
SPREAD
3.3 V LVTTL input. Enables spread spectrum mode when held LOW.
35
PWRDWN
3.3 V LVTTL input. Device enters powerdown mode when held LOW.
36
CPUSTOP
3.3 V LVTTL input. Stops all CPU clocks and 3V66 clocks when held LOW.
CPUDIV_2 output remains on all the time.
37
PCISTOP
3.3 V LVTTL input. Stops all PCI clocks except PCICLK_F when held LOW.
41, 42, 45, 46
CPUCLK [03]
2.5 V CPU output. 133 MHz or 100MHz depending on state of input pin SEL133/100.
49, 50
CPUDIV_2 [01]
2.5 V output running at 1/2 CPU clock frequency. 66 MHz or 50 MHz depending on
state of input pin SEL133/100.
53, 54, 55
IOAPIC [02]
2.5 V clock outputs running divide synchronous with the CPU clock frequency.
Fixed 16.67 MHz limit.
4, 10, 16, 23, 27, 31, 39
2
V
DD3V
3.3 V power supply.
1, 7, 13, 19, 20, 24, 29,
38, 40, 44, 48, 52
V
SS
Ground
43, 47, 51, 56
V
DD25V
2.5 V power supply
NOTE:
1. V
DD3V
, V
DD25V
and V
SS
in the above table reflects a likely internal POWER and GROUND partition to reduce the effects of internal noise on
the performance of the device. In reality, the platform will be configured with the V
DD25V
pins tied to a 2.5 V supply, all remaining V
DD
pins
tied to a common 3.3 V supply and all V
SS
pins being common.
2. Pin 39 should have a pi or equivalent filter to reduce the effect of noise on the analog portions of the device.
Philips Semiconductors
Product specification
PCK2010RA
CK98R (100/133MHz) RCC spread spectrum
system clock generator
2001 Apr 02
4
BLOCK DIAGRAM
PWRDWN
LOGIC
SYSPLL
USBPLL
14.318
MHZ
OSC
PWRDWN
LOGIC
DECODE
LOGIC
X
X
X
X
X
X
X
X
REF [01](14.318 MHz)
PWRDWN
SEL1
SPREAD
SEL133/100
XTAL_IN
XTAL_OUT
48 MHz USB
CPUCLK [03]
3V66 [03] (66MHz)
CPUDIV2 [01]
X
SEL0
SW00505
PWRDWN
LOGIC
X PCICLK_F (33MHz)
PWRDWN
LOGIC
X
PWRDWN
LOGIC
X APIC [02] (16.67 MHz)
PCICLK [17] (33 MHz)
X
STOP
LOGIC
LOGIC
X
PCISTOP
CPUSTOP
STOP
LOGIC
STOP
LOGIC
Philips Semiconductors
Product specification
PCK2010RA
CK98R (100/133MHz) RCC spread spectrum
system clock generator
2001 Apr 02
5
FUNCTION TABLE
SEL
133/100
SEL1
SEL0
CPU
CPUDIV2
3V66
PCI
48 MHz
REF
IOAPIC
NOTES
0
0
0
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
1
0
0
1
100 MHz
50 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
16.67 MHz
2
0
1
0
100 MHz
50 MHz
66 MHz
33 MHz
HI-Z
14.318 MHz
16.67 MHz
3
0
1
1
100 MHz
50 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
16.67 MHz
4, 7, 8
1
0
0
TCLK/2
TCLK/4
TCLK/4
TCLK/8
TCLK/2
TCLK
TCLK/16
5, 6
1
0
1
133 MHz
66 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
16.67 MHz
2
1
1
0
133 MHz
66 MHz
66 MHz
33 MHz
HI-Z
14.318 MHz
16.67 MHz
3
1
1
1
133 MHz
66 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
16.67 MHz
4, 7, 8
NOTES:
1. Required for board level "bed-of-nails" testing.
2. Philips center spread mode.
3. 48 MHz PLL disabled to reduce component jitter. 48 MHz outputs to be held Hi-Z instead of driven to LOW state.
4. "Normal" mode of operation.
5. TCLK is a test clock over driven on the XTALIN input during test mode. TCLK mode is based on 133 MHz CPU select logic.
6. Required for DC output impedance verification.
7. Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
8. Range of reference frequency allowed is MIN = 14.316 MHz, NOMINAL = 14.31818 MHz, MAX = 14.32 MHz.
CLOCK OUTPUT
TARGET FREQUENCY (MHz)
ACTUAL FREQUENCY (MHz)
PPM
USBCLK
7
48.0
48.008
167
CLOCK ENABLE CONFIGURATION
CPUSTOP
PWRDWN
PCISTOP
CPUCLK
CPUDIV2
APIC
3V66
PCI
PCI_F
REF / 48 MHz
OSC
VCOs
X
0
X
LOW
LOW
LOW
LOW
LOW
LOW
LOW
OFF
OFF
0
1
0
LOW
ON
ON
LOW
LOW
ON
ON
ON
ON
0
1
1
LOW
ON
ON
LOW
ON
ON
ON
ON
ON
1
1
0
ON
ON
ON
ON
LOW
ON
ON
ON
ON
1
1
1
ON
ON
ON
ON
ON
ON
ON
ON
ON
NOTES:
1. LOW means outputs held static LOW as per latency requirement below
2. ON means active.
3. PWRDWN pulled LOW, impacts all outputs including REF and 48 MHz outputs.
4. All 3V66 clocks as well as CPU clocks should stop cleanly when CPUSTOP is pulled LOW.
5. CPUDIV2, IOAPIC, REF, 48 MHz signals are not controlled by the CPUSTOP functionality and are enabled all in all conditions except when
PWRDWN is LOW.
POWER MANAGEMENT REQUIREMENTS
SIGNAL
SIGNAL STATE
LATENCY
SIGNAL
SIGNAL STATE
NO. OF RISING EDGES OF FREE RUNNING PCICLK
CPUSTOP
0 (DISABLED)
1
1 (ENABLED)
1
PCISTOP
0 (DISABLED)
1
1 (ENABLED)
1
PWRDWN
1 (NORMAL OPERATION)
3 ms
0 (POWER DOWN)
2 MAX
NOTES:
1. Clock ON/OFF latency is defined as the number of rising edges of free running PCICLKs between the clock disable goes HIGH/LOW to the
first valid clock that comes out of the device.
2. Power up latency is when PWRDWN goes inactive (HIGH) to when the first valid clocks are driven from the device.
Philips Semiconductors
Product specification
PCK2010RA
CK98R (100/133MHz) RCC spread spectrum
system clock generator
2001 Apr 02
6
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to V
SS
(V
SS
= 0 V).
SYMBOL
PARAMETER
CONDITION
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITION
MIN
MAX
UNIT
V
DD3
DC 3.3 V core supply voltage
0.5
+4.6
V
V
DDQ3
DC 3.3 V I/O supply voltage
0.5
+4.6
V
V
DDQ2
DC 2.5 V I/O supply voltage
0.5
+3.6
V
I
IK
DC input diode current
V
I
< 0
50
mA
V
I
DC input voltage
Note 2
0.5
5.5
V
I
OK
DC output diode current
V
O
> V
CC
or V
O
< 0
±
50
mA
V
O
DC output voltage
Note 2
0.5
V
CC
+ 0.5
V
I
O
DC output source or sink current
V
O
= 0 to V
CC
±
50
mA
T
stg
Storage temperature range
65
+150
°
C
P
tot
Power dissipation per package
plastic medium-shrink (SSOP)
For temperature range: 40 to +125
°
C
above +55
°
C derate linearly with 11.3 mW/K
850
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
V
DD3V
DC 3.3 V core supply voltage
3.135
3.465
V
V
DD25V
DC 2.5 V I/O supply voltage
2.375
2.625
V
Capacitive load on:
CPUCLK
1 device load, possible 2 loads
10
20
pF
PCICLK
Must meet PCI 2.1 requirements
10
30
pF
C
L
CPUDIV2
1 device load, possible 2 loads
10
20
pF
C
L
3V66
1 device load, possible 2 loads
10
30
pF
48 MHz clock USB
1 device load
10
20
pF
REF
1 device load
10
20
pF
IOAPIC
1 device load
10
20
pF
V
I
DC input voltage range
0
V
DD3V
V
V
O
DC output voltage range
0
V
DD25V
V
DD3V
V
f
REF
Reference frequency, oscillator nominal value
14.31818
14.31818
MHz
T
amb
Operating ambient temperature range in free air
0
+70
°
C
POWER MANAGEMENT
CK133
CONDITION
MAXIMUM 2.5 V SUPPLY CONSUMPTION
MAXIMUM DISCRETE CAP LOADS,
V
DD25V
= 2.625 V
ALL STATIC INPUTS = V
DD3V
OR V
SS
MAXIMUM 3.3 V SUPPLY CONSUMPTION
MAXIMUM DISCRETE CAP LOADS,
V
DD25V
= 3.465 V
ALL STATIC INPUTS = V
DD3V
OR V
SS
Power-down mode
(PWRDWN = 0)
100
µ
A
200
µ
A
Full active 100 MHz
SEL133/100# = 0
SEL1, 0 = 1 1
CPUSTOP, PCISTOP = 1
80 mA
160 mA
Full active 133 MHz
SEL133/100# = 1
SEL1, 0 = 1 1
CPUSTOP, PCISTOP = 1
90 mA
160 mA
Philips Semiconductors
Product specification
PCK2010RA
CK98R (100/133MHz) RCC spread spectrum
system clock generator
2001 Apr 02
7
DC CHARACTERISTICS
TEST CONDITIONS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= 0 to +70
°
C
UNIT
SYMBOL
PARAMETER
V
DD
(V)
OTHER
MIN
TYP
MAX
V
IH
HIGH level input voltage
3.135 to 3.465
V
DD25V
=
2.5 V
±
5%
2.0
V
DD
+ 0.3
V
V
IL
LOW level input voltage
3.135 to 3.465
V
DD3V
=
3.3 V
±
5%
V
SS
0.3
0.8
V
V
OH2
2.5 V output HIGH voltage
CPUCLK, IOAPIC, CPUDIV2
2.375 to 2.625
I
OH
= 1 mA
2.0
V
V
OL2
2.5 V output LOW voltage
CPUCLK, IOAPIC, CPUDIV2
2.375 to 2.625
I
OL
= 1 mA
0.4
V
V
OH3
3.3 V output HIGH voltage
REF, 48 MHz USB
3.135 to 3.465
I
OH
= 1 mA
2.0
V
V
OL3
3.3 V output LOW voltage
REF, 48 MHz USB
3.135 to 3.465
I
OL
= 1 mA
0.4
V
V
OH3
3.3 V output HIGH voltage
PCI, 3V66
3.135 to 3.465
I
OH
= 1 mA
2.4
V
V
OL3
3.3 V output LOW voltage
PCI, 3V66
3.135 to 3.465
I
OL
= 1 mA
0.55
V
I
O
CPUCLK
2.375
V
OUT
= 1.0 V
27
mA
I
OH
output HIGH current
2.625
V
OUT
= 2.375 V
27
mA
I
O
48 MHz USB, REF
3.135
V
OUT
= 1.0 V
29
mA
I
OH
,
output HIGH current
3.465
V
OUT
= 3.135 V
23
mA
I
O
PCI, 3V66
3.135
V
OUT
= 1.0 V
33
mA
I
OH
,
output HIGH current
3.465
V
OUT
= 3.135 V
33
mA
I
O
CPUCLK
2.375
V
OUT
= 1.2 V
27
mA
I
OL
output LOW current
2.625
V
OUT
= 0.3 V
30
mA
I
O
48 MHz USB, REF
3.135
V
OUT
= 1.95 V
29
mA
I
OL
,
output LOW current
3.465
V
OUT
= 0.4 V
27
mA
I
O
PCI, 3V66
3.135
V
OUT
= 1.95 V
30
mA
I
OL
,
output LOW current
3.465
V
OUT
= 0.4 V
38
mA
±
I
I
Input leakage current
3.465
5
µ
A
±
I
OZ
3-State output OFF-State
current
3.465
V
OUT
=
V
dd
or GND
I
O
= 0
10
µ
A
Cin
Input pin capacitance
5
pF
Cxtal
Xtal pin capacitance, as seen
by external crystal
18
pF
Cout
Output pin capacitance
6
pF
Philips Semiconductors
Product specification
PCK2010RA
CK98R (100/133MHz) RCC spread spectrum
system clock generator
2001 Apr 02
8
AC CHARACTERISTICS
V
DD3V
= 3.3 V
±
5%; VDDAPIC = V
DD25V
= 2.5 V
±
5%; f
crystal
= 14.31818 MHz
CPU CLOCK OUTPUTS, CPU(03) (LUMP CAPACITANCE TEST LOAD = 20 pF)
SYMBOL
PARAMETER
LIMITS
T
amb
= 0 to +70
°
C
LIMITS
T
amb
= 0 to +70
°
C
UNIT
NOTES
SYMBOL
PARAMETER
133 MHz MODE
100 MHz MODE
UNIT
NOTES
MIN
MAX
MIN
MAX
T
HKP
CPUCLK period
7.5
7.65
10.0
10.3
ns
2, 9
T
HKHPabsmin
Absolute minimum period
7.35
n/a
9.85
n/a
ns
2, 9
T
HKH
CPUCLK HIGH time
1.87
n/a
3.0
n/a
ns
5, 10
T
HKL
CPUCLK LOW time
1.67
n/a
2.8
n/a
ns
6, 10
T
HRISE
CPUCLK rise time
0.4
1.6
0.4
1.6
ns
8
T
HFALL
CPUCLK fall time
0.4
1.6
0.4
1.6
ns
8
T
JITTER
CPUCLK cycle-cycle jitter
250
250
ps
DUTY CYCLE
Output Duty Cycle
45
55
45
55
%
1
T
HSKW
CPUCLK pin-pin skew
175
175
ps
2
CPUDIV2 CLOCK OUTPUTS, CPUDIV2 (01) (LUMP CAPACITANCE TEST LOAD = 20 pF)
SYMBOL
PARAMETER
LIMITS
T
amb
= 0 to +70
°
C
LIMITS
T
amb
= 0 to +70
°
C
UNIT
NOTES
SYMBOL
PARAMETER
133 MHz MODE
100 MHz MODE
UNIT
NOTES
MIN
MAX
MIN
MAX
T
HKP
CPUDIV2 CLK period
15.0
15.3
20.0
20.6
ns
2, 9
T
HKH
CPUDIV2 CLK HIGH time
5.25
n/a
7.5
n/a
ns
5, 10
T
HKL
CPUDIV2 CLK LOW time
5.05
n/a
7.3
n/a
ns
6, 10
T
HRISE
CPUDIV2 CLK rise time
0.4
1.6
0.4
1.6
ns
8
T
HFALL
CPUDIV2 CLK fall time
0.4
1.6
0.4
1.6
ns
8
T
JITTER
CPUDIV2 CLK cycle-cycle jitter
250
250
ps
DUTY CYCLE
CPUDIV2 CLK Duty Cycle
45
55
45
55
%
1
T
HSKW
CPUDIV2 CLK pin-pin skew
175
175
ps
2
PCI CLOCK OUTPUTS, PCI(07) (LUMP CAPACITANCE TEST LOAD = 30 pF)
SYMBOL
PARAMETER
LIMITS
T
amb
= 0 to +70
°
C
LIMITS
T
amb
= 0 to +70
°
C
UNIT
NOTES
SYMBOL
PARAMETER
133 MHz MODE
100 MHz MODE
UNIT
NOTES
MIN
MAX
MIN
MAX
T
HKP
PCICLK period
30.0
n/a
30.0
n/a
ns
2, 9
T
HKH
PCICLK HIGH time
12.0
n/a
12.0
n/a
ns
5, 10
T
HKL
PCICLK LOW time
12.0
n/a
12.0
n/a
ns
6, 10
T
HRISE
PCICLK rise time
0.5
2.0
0.5
2.0
ns
8
T
HFALL
PCICLK fall time
0.5
2.0
0.5
2.0
ns
8
T
JITTER
PCICLK cycle-cycle jitter
500
500
ps
DUTY CYCLE
PCICLK Duty Cycle
45
55
45
55
%
1
T
HSKW
PCICLK pin-pin skew
500
500
ps
2
Philips Semiconductors
Product specification
PCK2010RA
CK98R (100/133MHz) RCC spread spectrum
system clock generator
2001 Apr 02
9
APIC(01) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20 pF)
SYMBOL
PARAMETER
LIMITS
T
amb
= 0 to +70
°
C
LIMITS
T
amb
= 0 to +70
°
C
UNIT
NOTES
SYMBOL
PARAMETER
133 MHz MODE
100 MHz MODE
UNIT
NOTES
MIN
MAX
MIN
MAX
T
HKP
IOAPIC CLK period
60.0
61.2
60.0
61.2
ns
2, 9
T
HKH
IOAPIC CLK HIGH time
25.5
n/a
25.5
n/a
ns
5, 10
T
HKL
IOAPIC CLK LOW time
25.3
n/a
25.3
n/a
ns
6, 10
T
HRISE
IOAPIC CLK rise time
0.4
1.6
0.4
1.6
ns
8
T
HFALL
IOAPIC CLK fall time
0.4
1.6
0.4
1.6
ns
8
T
JITTER
IOAPIC CLK cycle-cycle jitter
500
500
ps
DUTY CYCLE
IOAPIC CLK Duty Cycle
45
55
45
55
%
1
T
HSKW
IOAPIC CLK pin-pin skew
250
250
ps
2
3V66 CLOCK OUTPUT, 3V66 (03) (LUMP CAPACITANCE TEST LOAD = 30 pF)
SYMBOL
PARAMETER
LIMITS
T
amb
= 0 to +70
°
C
LIMITS
T
amb
= 0 to +70
°
C
UNIT
NOTES
SYMBOL
PARAMETER
133 MHz MODE
100 MHz MODE
UNIT
NOTES
MIN
MAX
MIN
MAX
T
HKP
3V66 CLK period
15.0
15.3
15.0
15.3
ns
2, 9, 4
T
HKH
3V66 CLK HIGH time
4.95
n/a
4.95
n/a
ns
5, 10
T
HKL
3V66 CLK LOW time
4.55
n/a
4.55
n/a
ns
6, 10
T
HRISE
3V66 CLK rise time
0.5
2.0
0.5
2.0
ns
8
T
HFALL
3V66 CLK fall time
0.5
2.0
0.5
2.0
ns
8
T
JITTER
3V66 CLK cycle-cycle jitter
500
500
ps
DUTY CYCLE
3V66 CLK Duty Cycle
45
55
45
55
%
1
T
HSKW
3V66 CLK pin-pin skew
250
250
ps
2
48MHZ(01) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20 pF)
SYMBOL
PARAMETER
LIMITS
T
amb
= 0 to +70
°
C
LIMITS
T
amb
= 0 to +70
°
C
UNIT
NOTES
SYMBOL
PARAMETER
133 MHz MODE
100 MHz MODE
UNIT
NOTES
MIN
MAX
MIN
MAX
T
HKP
48 MHz clock period
20.829
20.83
20.829
20.83
ns
2
T
HKH
48 MHz clock HIGH time
7.57
n/a
7.57
n/a
ns
T
HKL
48 MHz clock LOW time
7.17
n/a
7.17
n/a
ns
T
HRISE
(t
R
)
Output rise edge rate
1
4
1
4
ns
T
HFALL
(t
F
)
Output fall edge rate
1
4
1
4
ns
DUTY CYCLE (t
D
)
Duty Cycle
45
55
45
55
%
T
JITTER
CLK cycle-cycle jitter
500
500
ps
T
HSTB
(f
ST
)
Frequency stabilization from Power-up (cold start)
3
ms
NOTES:
1. See Figure 5 for measure points.
2. Average period over 1
µ
s.
Philips Semiconductors
Product specification
PCK2010RA
CK98R (100/133MHz) RCC spread spectrum
system clock generator
2001 Apr 02
10
AC CHARACTERISTICS (Continued)
TEST CONDITIONS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= 0 to +70
°
C
UNIT
NOTES
SYMBOL
PARAMETER
Measurement loads
(lumped)
Measure points
MIN
TYP
MAX
UNIT
NOTES
T
HPOFFSET
CPUCLK to 3V66 CLK,
CPU leads
CPU@20 pF,
3V66@30 pF
CPU@1.25 V,
3V66@1.5 V
0.0
0.45
1.5
ns
1
T
HPOFFSET
3V66 CLK to PCICLK,
3V66 leads
3V66@30 pF,
PCI@30 pF
3V66@1.5 V,
PCI@1.5 V
1.5
2.0
3.5
ns
1
T
HPOFFSET
CPUCLK to IOAPIC,
CPU leads
CPU@20 pF,
IOAPIC@20 pF
3CPU@1.25 V,
IOAPIC@1.25 V
1.5
2.4
4.0
ns
1
T
HPOFFSET
CPUCLK to PCICLK ,
CPU leads
CPU@20 pF
PCI@30 pF
CPU@1.25 V
PCI@1.5 V
1.5
2.7
4.0
ns
NOTES:
1. Output drivers must have monotonic rise/fall times through the specified V
OL
/V
OH
levels.
2. Period, jitter, offset and skew measured on rising edge @1.25 V for 2.5 V clocks and @ 1.5 V for 3.3 V clocks.
3. The PCICLK is the CPUCLK divided by four at CPUCLK = 133 MHz. The 3V66 CLK is internal VCO frequency divided by three at
CPUCLK = 100 MHz.
4. 3V66 CLK is internal VCO frequency divided by two at CPUCLK = 133 MHz. The 3V66 CLK is internal VCO frequency divided by three at
CPUCLK = 100 MHz.
5. T
HKH
is measured at 2.0 V for 2.5 V outputs, 2.4 V for 3.3 V outputs as shown in Figure 4.
6. T
HKL
is measured at 0.4 V for all outputs as shown in Figure 4.
7. The time is specified from when V
DDQ
achieves its nominal operating level (typical condition V
DDQ
= 3.3 V) until the frequency output is
stable and operating within specification.
8. T
HRISE
and T
HFALL
are measured as a transition through the threshold region V
OL
= 0.4 V and V
OH
= 2.4 V for 3 V outputs (1 mA) JEDEC
specification. T
HRISE
and T
HFALL
are measured as a transition through the threshold region V
OL
= 0.4 V and V
OH
= 2.0 V for 2.5 V outputs
(1 mA) JEDEC specification.
9. The average period over any 1
µ
s period of time must be greater than the minimum specified period.
10. Calculated at minimum edge-rate (1V/ns) to guarantee 45/55% duty-cycle. Pulse width is required to be wider at faster edge-rate to ensure
duty-cycle specification is met.
11. Output (see Figure 5 for measure points).
Philips Semiconductors
Product specification
PCK2010RA
CK98R (100/133MHz) RCC spread spectrum
system clock generator
2001 Apr 02
11
SPREAD SPECTRUM FUNCTION TABLE
SPREAD#
SEL133/100#
SEL1
SEL0
F nction
48 MHz PLL
pin 34
pin 28
pin 33
pin 32
Function
48 MHz PLL
0 (active)
0 (100 MHz)
0
0
3-State to High Impedance
Inactive
0 (active)
0 (100 MHz)
0
1
100 MHz, Center Spread
±
0.6%
Active
0 (active)
0 (100 MHz)
1
0
100 MHz, Down Spread 0.6%
Inactive
0 (active)
0 (100 MHz)
1
1
100 MHz, Down Spread 0.6%
Active
0 (active)
1 (133 MHz)
0
0
Test Mode
Active
0 (active)
1 (133 MHz)
0
1
133 MHz, Center Spread
±
0.6%
Active
0 (active)
1 (133 MHz)
1
0
133 MHz, Down Spread 0.6%
Inactive
0 (active)
1 (133 MHz)
1
1
133 MHz, Down Spread 0.6%
Active
1 (inactive)
0 (100 MHz)
0
0
3-State to High Impedance
Inactive
1 (inactive)
0 (100 MHz)
0
1
100 MHz, No Spread Spectrum
Active
1 (inactive)
0 (100 MHz)
1
0
100 MHz, No Spread Spectrum
Inactive
1 (inactive)
0 (100 MHz)
1
1
100 MHz, No Spread Sprectrum
Active
1 (inactive)
1 (133 MHz)
0
0
Test Mode
Active
1 (inactive)
1 (133 MHz)
0
1
133 MHz, No Spread Sprectrum
Active
1 (inactive)
1 (133 MHz)
1
0
133 MHz, No Spread Sprectrum
Inactive
1 (inactive)
1 (133 MHz)
1
1
133 MHz, No Spread Sprectrum
Active
Philips Semiconductors
Product specification
PCK2010RA
CK98R (100/133MHz) RCC spread spectrum
system clock generator
2001 Apr 02
12
AC WAVEFORMS
V
M
= 1.25 V @ V
DDQ2
and 1.5 V @ V
DDQ3
V
X
= V
OL
+ 0.3 V
V
Y
= V
OH
0.3 V
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
CPUCLK
@133MHz
1.5V
1.25V
V
DDQ2
V
SS
V
DDQ3
V
SS
T
HPOFFSET
SW00354
3v66
@66MHz
CPU leads 3V66
Figure 1. CPUCLK to 3V66 offset
1.5V
1.5V
PCICLK
@ 33MHz
V
DDQ3
V
SS
V
DDQ3
V
SS
T
HPOFFSET
SW00356
3V66 leads PCICLK
3V66
@ 66MHz
Figure 2. 3V66 to PCI offset
CPUCLK
@ 133MHz
1.25V
1.25V
IOAPIC
@ 16.6MHz
V
DDQ2
V
SS
V
DDQ2
V
SS
T
HPOFFSET
SW00357
CPUCLK leads IOAPIC
Figure 3. CPU to IOAPIC offset
T
HKP
DUTY CYCLE
T
HKH
T
RISE
T
FALL
T
HKL
T
PKP
T
PKH
T
RISE
T
FALL
T
PKL
2.5V CLOCKING
INTERFACE
3.3V CLOCKING
INTERFACE
(TTL)
2.0
1.25
0.4
2.4
1.5
0.4
SW00242
Figure 4. 2.5V/3.3V clock waveforms
V
DDQ2
2.5 V MEASUREMENT POINTS
V
OH
= 2.0 V
V
IH
= 1.7 V
1.25 V
V
IL
= 0.7 V
V
OL
= 0.4 V
V
SS
SYSTEM
MEASUREMENT
POINTS
V
DDQ3
3.3 V MEASUREMENT POINTS
V
OH
= 2.4 V
V
IH
= 2.0 V
1.5 V
V
IL
= 0.7 V
V
OL
= 0.4 V
V
SS
COMPONENT
MEASUREMENT
POINTS
SYSTEM
MEASUREMENT
POINTS
COMPONENT
MEASUREMENT
POINTS
SW00243
Figure 5. Component versus system measure points
t
PLZ
t
PZL
V
I
SEL133/100,
SEL1, SEL0
GND
V
DD
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
OL
V
OH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
V
SS
outputs
enabled
outputs
enabled
outputs
disabled
t
PHZ
V
M
V
M
V
M
t
PZH
V
X
V
Y
SW00454
Figure 6. 3-State enable and disable times
Philips Semiconductors
Product specification
PCK2010RA
CK98R (100/133MHz) RCC spread spectrum
system clock generator
2001 Apr 02
13
PULSE
GENERATOR
RT
VI
D.U.T.
VO
C
L
VDD
TEST
S
1
t
PLH
/t
PHL
Open
t
PLZ
/t
PZL
2
<
V
DD
t
PHZ
/t
PZH
V
SS
Open
V
SS
S
1
2
<
V
DD
V
DD
= V
DDQ2
or V
DDQ3
, DEPENDS ON THE OUTPUT
500
500
SW00238
Figure 7. Load circuitry for switching times
SW00244
Á
Á
Á
Á
PWRDWN
CPUCLK
(INTERNAL)
PCICLK
(INTERNAL)
PCICLK
(EXTERNAL)
CPUCLK
(EXTERNAL)
PWRDWN
OSC & VCO
USB (48MHz)
Figure 8. Power Management
Philips Semiconductors
Product specification
PCK2010RA
CK98R (100/133MHz) RCC spread spectrum
system clock generator
2001 Apr 02
14
SSOP56:
plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
Philips Semiconductors
Product specification
PCK2010RA
CK98R (100/133MHz) RCC spread spectrum
system clock generator
2001 Apr 02
15
NOTES
Philips Semiconductors
Product specification
PCK2010RA
CK98R (100/133MHz) RCC spread spectrum
system clock generator
2001 Apr 02
16
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381
©
Copyright Philips Electronics North America Corporation 2001
All rights reserved. Printed in U.S.A.
Date of release: 0401
Document order number:
9397 750 08212
Philips
Semiconductors
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
[1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1]
Please consult the most recently issued datasheet before initiating or completing a design.
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