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Part Number PCA9548

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Philips
Semiconductors
PCA9548
8-channel I
2
C switch with reset
2004 Sep 30
INTEGRATED CIRCUITS
Product data sheet
Supersedes data of 2002 Feb 19
Philips Semiconductors
Product data sheet
PCA9548
8-channel I
2
C switch with reset
2
2004 Sep 30
FEATURES
·
1-of-8 bi-directional translating switches
·
I
2
C interface logic; compatible with SMBus standards
·
Active LOW Reset Input
·
3 address pins allowing up to 8 devices on the I
2
C-bus
·
Channel selection via I
2
C-bus, in any combination
·
Power-up with all switch channels deselected
·
Low Rds
ON
switches
·
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and
5 V buses
·
No glitch on power-up
·
Supports hot insertion
·
Low stand-by current
·
Operating power supply voltage range of 2.3 V to 5.5 V
·
5 V tolerant Inputs
·
0 kHz to 400 kHz clock frequency
·
ESD protection exceeds 2000 V HBM per JESD22-A114,
150 V MM per JESD22-A115 and 1000 V per JESD22-C101
·
Latchup testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
·
Packages offered: SO24, TSSOP24
DESCRIPTION
The PCA9548 is a octal bi-directional translating switch controlled
by the I
2
C-bus. The SCL/SDA upstream pair fans out to eight
downstream pairs, or channels. Any individual SCx/SDx channel or
combination of channels can be selected, determined by the
contents of the programmable Control Register.
An active-LOW reset input allows the PCA9548 to recover from a
situation where one of the downstream I
2
C-buses is stuck in a LOW
state. Pulling the RESET pin LOW resets the I2C state machine and
causes all the channels to be deselected as does the internal power
on reset function.
The pass gates of the switches are constructed such that the V
DD
pin can be used to limit the maximum high voltage which will be
passed by the PCA9548. This allows the use of different bus
voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V parts can
communicate with 5 V parts without any additional protection.
External pull-up resistors pull the bus up to the desired voltage level
for each channel. All I/O pins are 5 V tolerant.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
24-Pin Plastic SO
­40
°
C to +85
°
C
PCA9548D
SOT137-1
24-Pin Plastic TSSOP
­40
°
C to +85
°
C
PCA9548PW
SOT355-1
Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging.
Philips Semiconductors
Product data sheet
PCA9548
8-channel I
2
C switch with reset
2004 Sep 30
3
PIN CONFIGURATION -- SO, TSSOP
A0
A1
RESET
SD0
SD2
V
DD
SDA
SCL
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
SC0
SD1
SC1
A2
SC7
SD7
SC6
SD6
SW00361
V
SS
9
16
10
15
11
14
12
13
SC2
SD3
SC3
SC5
SD5
SC4
SD4
Figure 1. Pin configuration -- SO, TSSOP
PIN DESCRIPTION
SO, TSSOP
PIN NUMBER
SYMBOL
FUNCTION
1
A0
Address input 0
2
A1
Address input 1
3
RESET
Active LOW reset input
4
SD0
Serial data output 0
5
SC0
Serial clock output 1
6
SD1
Serial data output 1
7
SC1
Serial clock output 2
8
SD2
Serial data output 2
9
SC2
Serial clock output 3
10
SD3
Serial data output 3
11
SC3
Serial clock output 4
12
V
SS
Supply ground
13
SD4
Serial data output 4
14
SC4
Serial clock output 5
15
SD5
Serial data output 5
16
SC5
Serial clock output 6
17
SD6
Serial data output 6
18
SC6
Serial clock output 7
19
SD7
Serial data output 7
20
SC7
Serial clock output 8
21
A2
Address input 2
22
SCL
Serial clock line
23
SDA
Serial data line
24
V
DD
Supply voltage
Philips Semiconductors
Product data sheet
PCA9548
8-channel I
2
C switch with reset
2004 Sep 30
4
BLOCK DIAGRAM
SC1
SC2
SC3
SC4
SD0
SD1
SD2
SD3
V
SS
SCL
V
DD
SDA
INPUT
FILTER
RESET
CIRCUIT
I
2
C-BUS
CONTROL
SC0
SC5
SC6
SC7
SD4
SD5
SD6
SD7
SW00371
A0
A1
A2
RESET
PCA9548
SWITCH CONTROL LOGIC
Figure 2. Block diagram
Philips Semiconductors
Product data sheet
PCA9548
8-channel I
2
C switch with reset
2004 Sep 30
5
DEVICE ADDRESSING
Following a START condition the bus master must output the
address of the slave it is accessing. The address of the PCA9548 is
shown in Figure 3. To conserve power, no internal pullup resistors
are incorporated on the hardware selectable address pins and they
must be pulled HIGH or LOW.
A1 A0
0
A2
SW00915
1
1
1
R/W
FIXED
HARDWARE SELECTABLE
Figure 3. Slave address
The last bit of the slave address defines the operation to be
performed. When set to logic 1, a read is selected while a logic 0
selects a write operation.
CONTROL REGISTER
Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9548, which will be stored
in the control register. If multiple bytes are received by the
PCA9548, it will save the last byte received. This register can be
written and read via the I
2
C-bus.
B3
B2
B1
B0
SW00932
B7
B6
B5
B4
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
CHANNEL SELECTION BITS
(READ/WRITE)
6
5
4
2
1
0
7
3
Figure 4. Control register
CONTROL REGISTER DEFINITION
One or several SCx/SDx downstream pair, or channel, is selected
by the contents of the control register. This register is written after
the PCA9548 has been addressed. The 2 LSBs of the control byte
are used to determine which channel is to be selected. When a
channel is selected, the channel will become active after a stop
condition has been placed on the I
2
C-bus. This ensures that all
SCx/SDx lines will be in a HIGH state when the channel is made
active, so that no false conditions are generated at the time of
connection.
Table 1. Control Register; Write -- Channel Selection/
Read -- Channel Status
B7
B6
B5
B4
B3
B2
B1
B0
COMMAND
X
X
X
X
X
X
X
0
Channel 0
disabled
X
X
X
X
X
X
X
1
Channel 0
enabled
X
X
X
X
X
X
0
X
Channel 1
disabled
X
X
X
X
X
X
1
X
Channel 1
enabled
X
X
X
X
X
0
X
X
Channel 2
disabled
X
X
X
X
X
1
X
X
Channel 2
enabled
X
X
X
X
0
X
X
X
Channel 3
disabled
X
X
X
X
1
X
X
X
Channel 3
enabled
X
X
X
0
X
X
X
X
Channel 4
disabled
X
X
X
1
X
X
X
X
Channel 4
enabled
X
X
0
X
X
X
X
X
Channel 5
disabled
X
X
1
X
X
X
X
X
Channel 5
enabled
X
0
X
X
X
X
X
X
Channel 6
disabled
X
1
X
X
X
X
X
X
Channel 6
enabled
0
X
X
X
X
X
X
X
Channel 7
disabled
1
X
X
X
X
X
X
X
Channel 7
enabled
0
0
0
0
0
0
0
0
No channel
selected;
power-up/reset
default state
NOTE: Several channels can be enabled at the same time.
Ex: B7 = 0, B6 = 1, B5 = 0, B4 = 0, B3 = 1, B2 = 1, B1 = 0, B0 = 0,
means that channels 7, 5, 4, 1, and 0 are disabled and channels 6,
3, and 2 are enabled.
Care should be taken not to exceed the maximum bus capacitance.
RESET INPUT
The RESET input is an active-LOW signal which may be used to
recover from a bus fault condition. By asserting this signal LOW for
a minimum of t
WL
, the PCA9548 will reset its registers and I
2
C state
machine and will deselect all channels. The RESET input must be
connected to V
DD
through a pull-up resistor.
POWER-ON RESET
When power is applied to V
DD
, an internal Power On Reset holds
the PCA9548 in a reset state until V
DD
has reached V
POR
. At this
point, the reset condition is released and the PCA9548 registers and
I
2
C state machine are initialized to their default states, all zeroes
causing all the channels to be deselected.
Philips Semiconductors
Product data sheet
PCA9548
8-channel I
2
C switch with reset
2004 Sep 30
6
VOLTAGE TRANSLATION
The pass gate transistors of the PCA9548 are constructed such that
the V
DD
voltage can be used to limit the maximum voltage that will
be passed from one I
2
C-bus to another.
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
V
pass
vs. V
DD
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
pass
V
DD
MINIMUM
TYPICAL
MAXIMUM
SW00820
2.0
Figure 5. V
pass
voltage vs. V
DD
Figure 5 shows the voltage characteristics of the pass gate
transistors (note that the PCA9548 is only tested at the points
specified in the DC Characteristics section of this datasheet). In
order for the PCA9548 to act as a voltage translator, the V
pass
voltage should be equal to, or lower than the lowest bus voltage. For
example, if the main bus was running at 5 V, and the downstream
buses were 3.3 V and 2.7 V, then V
pass
should be equal to or below
2.7 V to effectively clamp the downstream bus voltages. Looking at
Figure 5, we see that V
pass
(max.) will be at 2.7 V when the
PCA9548 supply voltage is 3.5 V or lower so the PCA9548 supply
voltage could be set to 3.3 V. Pull-up resistors can then be used to
bring the bus voltages to their appropriate levels (see Figure 12).
More Information can be found in Application Note AN262
PCA954X
family of I
2
C/SMBus multiplexers and switches.
Philips Semiconductors
Product data sheet
PCA9548
8-channel I
2
C switch with reset
2004 Sep 30
7
CHARACTERISTICS OF THE I
2
C-BUS
The I
2
C-bus is for 2-way, 2-line communication between different ICs
or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock pulse. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (see Figure 6).
SDA
SCL
SW00363
data line
stable;
data valid
change
of data
allowed
Figure 6. Bit transfer
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 7).
System configuration
A device generating a message is a `transmitter', a device receiving
is the `receiver'. The device that controls the message is the
`master' and the devices which are controlled by the master are the
`slaves' (see Figure 8).
SDA
SCL
SW00365
S
P
SDA
SCL
START condition
STOP condition
Figure 7. Definition of start and stop conditions
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
SW00366
I
2
C
MULTIPLEXER
SLAVE
Figure 8. System configuration
Philips Semiconductors
Product data sheet
PCA9548
8-channel I
2
C switch with reset
2004 Sep 30
8
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of
the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT
BY TRANSMITTER
SCL FROM
MASTER
SW00368
DATA OUTPUT
BY RECEIVER
1
2
8
9
S
START condition
clock pulse for
acknowledgement
acknowledge
not acknowledge
Figure 9. Acknowledgement on the I
2
C-bus
S
SDA
0
A
A
1
1
1
0
A2
A1 A0
SLAVE ADDRESS
start condition
R/W
acknowledge
from slave
acknowledge
from slave
B0
CONTROL REGISTER
B4
P
SW01032
B1
B5
B2
B6
B3
B7
Figure 10. WRITE control register
SDA
S
1
A
NA
1
1
1
0
A2 A1 A0
start condition
R/W
acknowledge
from slave
CONTROL REGISTER
P
stop condition
last byte
SW01033
SLAVE ADDRESS
no acknowledge
from master
B0
B4
B1
B5
B2
B6
B3
B7
Figure 11. READ control register
Philips Semiconductors
Product data sheet
PCA9548
8-channel I
2
C switch with reset
2004 Sep 30
9
TYPICAL APPLICATION
PCA9548
V = 2.7 ­ 5.5 V
SD0
SC0
V = 2.7 ­ 5.5 V
SD1
SC1
A1
A0
V
SS
SDA
SCL
RESET
V
DD
= 3.3 V
V
DD
= 2.7 ­ 5.5 V
I2C/SMBus MASTER
SW00924
SDA
SCL
CHANNEL 0
CHANNEL 1
V = 2.7 ­ 5.5 V
SD2
SC2
CHANNEL 2
V = 2.7 ­ 5.5 V
SD3
SC3
CHANNEL 3
A2
V = 2.7 ­ 5.5 V
SD4
SC4
V = 2.7 ­ 5.5 V
SD5
SC5
CHANNEL 4
CHANNEL 5
V = 2.7 ­ 5.5 V
SD6
SC6
CHANNEL 6
V = 2.7 ­ 5.5 V
SD7
SC7
CHANNEL 7
Figure 12. Typical application
Philips Semiconductors
Product data sheet
PCA9548
8-channel I
2
C switch with reset
2004 Sep 30
10
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).Voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
DD
DC supply voltage
­0.5 to +7.0
V
V
I
DC input voltage
­0.5 to +7.0
V
I
I
DC input current
±
20
mA
I
O
DC output current
±
25
mA
I
DD
Supply current
±
100
mA
I
SS
Supply current
±
100
mA
P
tot
total power dissipation
400
mW
T
stg
Storage temperature range
­60 to +150
°
C
T
amb
Operating ambient temperature
­40 to +85
°
C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
°
C.
DC CHARACTERISTICS
V
DD
= 2.3 V to 3.6 V; V
SS
= 0 V; T
amb
= ­40
°
C to +85
°
C; unless otherwise specified. (See page 11 for V
DD
= 3.6 V to 5.5 V)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply
V
DD
Supply voltage
2.3
--
3.6
V
I
DD
Supply current
Operating mode; V
DD
= 3.6 V;
no load; V
I
= V
DD
or V
SS
;
f
SCL
= 100 kHz
--
45
100
µ
A
I
stb
Standby current
Standby mode; V
DD
= 3.6 V;
no load; V
I
= V
DD
or V
SS
--
25
100
µ
A
V
POR
Power-on reset voltage
no load; V
I
= V
DD
or V
SS
--
1.6
2.1
V
Input SCL; input/output SDA
V
IL
LOW-level input voltage
­0.5
--
0.3V
DD
V
V
IH
HIGH-level input voltage
0.7V
DD
--
6
V
I
OL
LOW-level output current
V
OL
= 0.4 V
3
--
--
mA
I
OL
LOW-level out ut current
V
OL
= 0.6 V
6
--
--
mA
I
L
Leakage current
V
I
= V
DD
or V
SS
­1
--
+1
µ
A
C
i
Input capacitance
V
I
= V
SS
--
20
21
pF
Select inputs A0 to A2 / RESET
V
IL
LOW-level input voltage
­0.5
--
+0.3V
DD
V
V
IH
HIGH-level input voltage
0.7V
DD
--
V
DD
+ 0.5
V
I
LI
Input leakage current
pin at V
DD
or V
SS
­1
--
+1
µ
A
C
i
Input capacitance
V
I
= V
SS
--
2
5
pF
Pass Gate
R
ON
Switch resistance
V
CC
= 3.67 V; V
O
= 0.4 V; I
O
= 15 mA
5
20
30
R
ON
Switch resistance
V
CC
= 2.3 V to 2.7 V; V
O
= 0.4V; I
O
= 10 mA
7
26
55
V
swin
= V
DD
= 3.3 V; I
swout
= ­100
µ
A
--
2.2
--
V
P
Switch output voltage
V
swin
= V
DD
= 3.0 V to 3.6 V; I
swout
= ­100
µ
A
1.6
--
2.8
V
V
Pass
Switch out ut voltage
V
swin
= V
DD
= 2.5 V; I
swout
= ­100
µ
A
--
1.5
--
V
V
swin
= V
DD
= 2.3 V to 2.7 V; I
swout
= ­100
µ
A
1.1
--
2.0
I
L
Leakage current
V
I
= V
DD
or V
SS
­1
--
+1
µ
A
C
io
Input/output capacitance
V
I
= V
SS
--
3
5
pF
Philips Semiconductors
Product data sheet
PCA9548
8-channel I
2
C switch with reset
2004 Sep 30
11
DC CHARACTERISTICS
V
DD
= 3.6 V to 5.5 V; V
SS
= 0 V; T
amb
= ­40
°
C to +85
°
C; unless otherwise specified. (See page 10 for V
DD
= 2.3 V to 3.6 V)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply
V
DD
Supply voltage
3.6
--
5.5
V
I
DD
Supply current
Operating mode; V
DD
= 5.5 V;
no load; V
I
= V
DD
or V
SS
;
f
SCL
= 100 kHz
--
575
600
µ
A
I
stb
Standby current
Standby mode; V
DD
= 5.5 V;
no load; V
I
= V
DD
or V
SS
--
250
300
µ
A
V
POR
Power-on reset voltage
no load; V
I
= V
DD
or V
SS
--
1.7
2.1
V
Input SCL; input/output SDA
V
IL
LOW-level input voltage
­0.5
--
0.3V
DD
V
V
IH
HIGH-level input voltage
0.7V
DD
--
6
V
I
O
LOW level output current
V
OL
= 0.4 V
3
--
--
mA
I
OL
LOW-level output current
V
OL
= 0.6 V
6
--
--
mA
I
IL
LOW-level input current
V
I
= V
SS
­10
--
+10
µ
A
I
IH
HIGH­level input current
V
I
= V
DD
--
--
100
µ
A
C
i
Input capacitance
V
I
= V
SS
--
20
21
pF
Select inputs A0 to A2 / RESET
V
IL
LOW-level input voltage
­0.5
--
+0.3V
DD
V
V
IH
HIGH-level input voltage
0.7V
DD
--
V
DD
+ 0.5
V
I
LI
Input leakage current
pin at V
DD
or V
SS
­1
--
+50
µ
A
C
i
Input capacitance
V
I
= V
SS
--
2
5
pF
Pass Gate
R
ON
Switch resistance
V
CC
= 4.5 V to 5.5 V; V
O
= 0.4 V; I
O
= 15 mA
4
11
24
V
Switch output voltage
V
swin
= V
DD
= 5.0 V; I
swout
= ­100
µ
A
--
3.5
--
V
V
Pass
Switch output voltage
V
swin
= V
DD
= 4.5 V to 5.5 V; I
swout
= ­100
µ
A
2.6
--
4.5
V
I
L
Leakage current
V
I
= V
DD
or V
SS
­10
--
+10
µ
A
C
io
Input/output capacitance
V
I
= V
SS
--
3
5
pF
Philips Semiconductors
Product data sheet
PCA9548
8-channel I
2
C switch with reset
2004 Sep 30
12
AC CHARACTERISTICS
SYMBOL
PARAMETER
STANDARD-MODE
I
2
C-BUS
FAST-MODE
I
2
C-BUS
UNIT
MIN
MAX
MIN
MAX
t
pd
Propagation delay from SDA to SD
n
or SCL to SC
n
--
0.3
1
--
0.3
1
ns
f
SCL
SCL clock frequency
0
100
0
400
kHz
t
BUF
Bus free time between a STOP and START condition
4.7
--
1.3
--
µ
s
t
HD;STA
Hold time (repeated) START condition
After this period, the first clock pulse is generated
4.0
--
0.6
--
µ
s
t
LOW
LOW period of the SCL clock
4.7
--
1.3
--
µ
s
t
HIGH
HIGH period of the SCL clock
4.0
--
0.6
--
µ
s
t
SU;STA
Set-up time for a repeated START condition
4.7
--
0.6
--
µ
s
t
SU;STO
Set-up time for STOP condition
4.0
--
0.6
--
µ
s
t
HD;DAT
Data hold time
0
2
3.45
0
2
0.9
µ
s
t
SU;DAT
Data set-up time
250
--
100
--
ns
t
R
Rise time of both SDA and SCL signals
--
1000
20 + 0.1C
b
3
300
ns
t
F
Fall time of both SDA and SCL signals
--
300
20 + 0.1C
b
3
300
µ
s
C
b
Capacitive load for each bus line
--
400
--
400
µ
s
t
SP
Pulse width of spikes which must be suppressed
by the input filter
--
50
--
50
ns
t
VD:DATL
Data valid (HL)
--
1
--
1
µ
s
t
VD:DATH
Data valid (LH)
--
0.6
--
0.6
µ
s
t
VD:ACK
Data valid Acknowledge
--
1
--
1
µ
s
RESET
t
WL(rst)
Pulse width low reset
4
--
4
--
ns
t
rst
Reset time (SDA clear)
500
--
500
--
ns
t
REC:STA
Recovery to Start
0
--
0
--
ns
NOTES:
1. Pass gate propagation delay is calculated from the 20
typical R
ON
and the 15 pF load capacitance.
2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH(min)
of the SCL signal) in order to bridge
the undefined region of the falling edge of SCL.
3. C
b
= total capacitance of one bus line in pF.
t
SP
t
BUF
t
HD;STA
P
P
S
t
LOW
t
R
t
HD;DAT
t
F
t
HIGH
t
SU;DAT
t
SU;STA
Sr
t
HD;STA
t
SU;STO
SDA
SCL
SU00645
Figure 13. Definition of timing on the I
2
C-bus
Philips Semiconductors
Product data sheet
PCA9548
8-channel I
2
C switch with reset
2004 Sep 30
13
SO24:
plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
Philips Semiconductors
Product data sheet
PCA9548
8-channel I
2
C switch with reset
2004 Sep 30
14
TSSOP24:
plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
Philips Semiconductors
Product data sheet
PCA9548
8-channel I
2
C switch with reset
2004 Sep 30
15
REVISION HISTORY
Rev
Date
Description
_2
20040930
Product data sheet (9397 750 14117). Supersedes data of 2002 Feb 19 (9397 750 09461).
Modifications:
·
Table 1. "Control Register; Write -- Channel Selection / Read -- Channel Status" on page 4:
add `No channel selected ; power-up/reset default state' row to bottom of table.
_1
20020219
Product data (9397 750 09461). ECN 853-2318 27757 of 19 February 2002.
Philips Semiconductors
Product data sheet
PCA9548
8-channel I
2
C switch with reset
2004 Sep 30
16
Purchase of Philips I
2
C components conveys a license under the Philips' I
2
C patent
to use the components in the I
2
C system provided the system conforms to the
I
2
C specifications defined by Philips. This specification can be ordered using the
code 9398 393 40011.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described
or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
©
Koninklijke Philips Electronics N.V. 2004
All rights reserved. Published in the U.S.A.
Date of release: 09-04
Document number:
9397 750 14117
Philips
Semiconductors
Data sheet status
[1]
Objective data sheet
Preliminary data sheet
Product data sheet
Product
status
[2] [3]
Development
Qualification
Production
Definitions
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
Data sheet status
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Level
I
II
III