Document Outline
- FEATURES
- DESCRIPTION
- ORDERING INFORMATION
- PIN CONFIGURATION „ SO, TSSOP
- PIN CONFIGURATION „ HVQFN
- PIN DESCRIPTION
- BLOCK DIAGRAM
- DEVICE ADDRESSING
- CONTROL REGISTER
- CONTROL REGISTER DEFINITION
- INTERRUPT HANDLING
- POWER-ON RESET
- VOLTAGE TRANSLATION
- CHARACTERISTICS OF THE I 2 C-BUS
- TYPICAL APPLICATION
- ABSOLUTE MAXIMUM RATINGS 1, 2
- DC CHARACTERISTICS
- AC CHARACTERISTICS
- PACKAGE OUTLINE
- SOT163-1
- SOT360-1
- SOT662-1
- REVISION HISTORY
- Data sheet status
- Definitions
- Disclaimers
Philips
Semiconductors
PCA9544A
4-channel I
2
C multiplexer with interrupt logic
2004 Sep 29
INTEGRATED CIRCUITS
Product data sheet
Supersedes data of 2004 Jul 28
Philips Semiconductors
Product data sheet
PCA9544A
4-channel I
2
C multiplexer with interrupt logic
2
2004 Sep 29
FEATURES
·
1-of-4 bi-directional translating multiplexer
·
I
2
C interface logic; compatible with SMBus
·
4 Active-LOW Interrupt Inputs
·
Active-LOW Interrupt Output
·
3 address pins allowing up to 8 devices on the I
2
C-bus
·
Channel selection via I
2
C-bus
·
Power-up with all multiplexer channels deselected
·
Low Rds
ON
switches
·
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and
5 V buses
·
No glitch on power-up
·
Supports hot insertion
·
Low stand-by current
·
Operating power supply voltage range of 2.3 V to 5.5 V
·
5 V tolerant Inputs
·
0 to 400 kHz clock frequency
·
ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V per JESD22-C101
·
Latchup testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
·
Three packages offered: SO20, TSSOP20, and HVQFN20
DESCRIPTION
The PCA9544A is a 1-of-4 bi-directional translating multiplexer,
controlled via the I
2
C-bus. The SCL/SDA upstream pair fans out to
four SCx/SDx downstream pairs, or channels. Only one SCx/SDx
channel is selected at a time, determined by the contents of the
programmable control register. Four interrupt inputs, INT0 to INT3,
one for each of the SCx/SDx downstream pairs, are provided. One
interrupt output, INT, which acts as an AND of the four interrupt
inputs, is provided.
A power-on reset function puts the registers in their default state and
initializes the I
2
C state machine with no channels selected.
The pass gates of the multiplexer are constructed such that the V
DD
pin can be used to limit the maximum high voltage which will be
passed by the PCA9544A. This allows the use of different bus
voltages on each SCx/SDx pair, so that 1.8 V, 2.5 V or 3.3 V parts
can communicate with 5 V parts without any additional protection.
External pull-up resistors pull the bus up to the desired voltage level
for each channel. All I/O pins are 5 V tolerant.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
TOPSIDE MARK
DRAWING NUMBER
20-Pin Plastic SO
40
°
C to +85
°
C
PCA9544AD
PCA9544AD
SOT163-1
20-Pin Plastic TSSOP
40
°
C to +85
°
C
PCA9544APW
PA9544A
SOT360-1
20-Pin Plastic HVQFN
40
°
C to +85
°
C
PCA9544ABS
9544A
SOT662-1
Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging.
I
2
C is a trademark of Philips Semiconductors Corporation.
Philips Semiconductors
Product data sheet
PCA9544A
4-channel I
2
C multiplexer with interrupt logic
2004 Sep 29
3
PIN CONFIGURATION -- SO, TSSOP
A0
A1
A2
INT0
SD1
V
DD
SDA
SCL
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
SD0
SC0
INT1
INT
SC3
SD3
INT3
SC2
9
12
10
11
SC1
VSS
SD2
INT2
SW00373
Figure 1. Pin configuration -- SO, TSSOP
PIN CONFIGURATION -- HVQFN
15
14
13
12
11
6
7
8
9
10
1
2
3
4
5
20
19
18
17
16
su01666
TOP VIEW
A2
INT0
SD0
SC0
INT1
SD1 SC1 V
SS
INT2 SD2
SC2
SC3
INT
INT3
SD3
SCL
SDA
V
DD
A0
A1
Figure 2. Pin configuration -- HVQFN
PIN DESCRIPTION
SO, TSSOP
PIN NUMBER
HVQFN
PIN NUMBER
SYMBOL
FUNCTION
1
19
A0
Address input 0
2
20
A1
Address input 1
3
1
A2
Address input 2
4
2
INT0
Active-LOW interrupt input 0
5
3
SD0
Serial data 0
6
4
SC0
Serial clock 0
7
5
INT1
Active-LOW interrupt input 1
8
6
SD1
Serial data 1
9
7
SC1
Serial clock 1
10
8
V
SS
Supply ground
11
9
INT2
Active-LOW interrupt input 2
12
10
SD2
Serial data 2
13
11
SC2
Serial clock 2
14
12
INT3
Active-LOW interrupt input 3
15
13
SD3
Serial data 3
16
14
SC3
Serial clock 3
17
15
INT
Active-LOW interrupt output
18
16
SCL
Serial clock line
19
17
SDA
Serial data line
20
18
V
DD
Supply voltage
Philips Semiconductors
Product data sheet
PCA9544A
4-channel I
2
C multiplexer with interrupt logic
2004 Sep 29
4
BLOCK DIAGRAM
SW02267
SC0
SC1
SC2
SC3
SD0
SD1
SD2
SD3
V
SS
SCL
V
DD
SDA
INPUT
FILTER
POWER-ON
RESET
I
2
C-BUS
CONTROL
A0
A2
INT[03]
INT LOGIC
INT
A1
PCA9544A
SWITCH CONTROL LOGIC
Figure 3. Block diagram
Philips Semiconductors
Product data sheet
PCA9544A
4-channel I
2
C multiplexer with interrupt logic
2004 Sep 29
5
DEVICE ADDRESSING
Following a START condition the bus master must output the
address of the slave it is accessing. The address of the PCA9544A
is shown in Figure 4. To conserve power, no internal pull-up
resistors are incorporated on the hardware selectable address pins
and they must be pulled HIGH or LOW.
A1 A0
0
A2
SW00862
1
1
1
R/W
FIXED
HARDWARE SELECTABLE
Figure 4. Slave address
The last bit of the slave address defines the operation to be
performed. When set to logic 1, a read is selected while a logic 0
selects a write operation.
CONTROL REGISTER
Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9544A which will be
stored in the Control Register. If multiple bytes are received by the
PCA9544A, it will save the last byte received. This register can be
written and read via the I
2
C-bus.
INT2 INT1
INT0
B2 B1 B0
CHANNEL SELECTION BITS
INTERRUPT BITS
INT3
SW00386
X
(READ ONLY)
(READ/WRITE)
6
5
4
2
1
0
7
3
ENABLE BIT
Figure 5. Control register
CONTROL REGISTER DEFINITION
A SCx/SDx downstream pair, or channel, is selected by the contents
of the control register. This register is written after the PCA9544A
has been addressed. The 3 LSBs of the control byte are used to
determine which channel is to be selected. When a channel is
selected, it will become active after a stop condition has been placed
on the I
2
C-bus. This ensures that all SCx/SDx lines will be in a
HIGH state when the channel is made active, so that no false
conditions are generated at the time of connection.
Table 1. Control Register; Write -- Channel Selection/
Read -- Channel Status
INT3
INT2
INT1
INT0
D3
B2
B1
B0
COMMAND
X
X
X
X
X
0
X
X
No channel
selected
X
X
X
X
X
1
0
0
Channel 0
enabled
X
X
X
X
X
1
0
1
Channel 1
enabled
X
X
X
X
X
1
1
0
Channel 2
enabled
X
X
X
X
X
1
1
1
Channel 3
enabled
0
0
0
0
0
0
0
0
No channel
selected;
power-up
default state
INTERRUPT HANDLING
The PCA9544A provides 4 interrupt inputs, one for each channel
and one open drain interrupt output. When an interrupt is generated by
any device, it will be detected by the PCA9544A and the interrupt
output will be driven LOW. The channel need not be active for
detection of the interrupt. A bit is also set in the control byte.
Bits 4 7 of the control byte correspond to channels 0 3 of the
PCA9544A, respectively. Therefore, if an interrupt is generated by
any device connected to channel 2, the state of the interrupt inputs is
loaded into the control register when a read is accomplished.
Likewise, an interrupt on any device connected to channel 0 would
cause bit 4 of the control register to be set on the read. The master
can then address the PCA9544A and read the contents of the
control byte to determine which channel contains the device
generating the interrupt. The master can then reconfigure the
PCA9544A to select this channel, and locate the device generating
the interrupt and clear it. The interrupt clears when the device
originating the interrupt clears.
It should be noted that more than one device can be providing an
interrupt on a channel, so it is up to the master to ensure that all
devices on a channel are interrogated for an interrupt.
The interrupt inputs may be used as general purpose inputs if the
interrupt function is not required.
If unused, interrupt input(s) must be connected to V
DD
through a
pull-up resistor.
Table 2. Control Register Read -- Interrupt
INT3
INT2
INT1
INT0
D3
B2
B1
B0
COMMAND
X
X
X
0
X
X
X
X
No interrupt
on channel 0
X
X
X
1
X
X
X
X
Interrupt on
channel 0
X
X
0
X
X
X
X
X
No interrupt
on channel 1
X
X
1
X
X
X
X
X
Interrupt on
channel 1
X
0
X
X
X
X
X
X
No interrupt
on channel 2
X
1
X
X
X
X
X
X
Interrupt on
channel 2
0
X
X
X
X
X
X
X
No interrupt
on channel 3
1
X
X
X
X
X
X
X
Interrupt on
channel 3
NOTE: Several interrupts can be active at the same time.
Ex: INT3 = 0, INT2 = 1, INT1 = 1, INT0 = 0, means that there is no
interrupt on channels 0 and 3, and there is interrupt on channels 1
and 2.
POWER-ON RESET
When power is applied to V
DD
, an internal Power On Reset holds
the PCA9544A in a reset condition until V
DD
has reached V
POR
. At
this point, the reset condition is released and the PCA9544A
registers and I
2
C state machine are initialized to their default states,
all zeroes causing all the channels to be deselected. Thereafter,
V
DD
must be lowered below 0.2 V to reset the device.
Philips Semiconductors
Product data sheet
PCA9544A
4-channel I
2
C multiplexer with interrupt logic
2004 Sep 29
6
VOLTAGE TRANSLATION
The pass gate transistors of the PCA9544A are constructed such
that the V
DD
voltage can be used to limit the maximum voltage that
will be passed from one I
2
C-bus to another.
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
V
pass
vs. V
DD
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
pass
V
DD
MINIMUM
TYPICAL
MAXIMUM
SW00820
2.0
Figure 6. V
pass
voltage
Figure 6 shows the voltage characteristics of the pass gate
transistors (note that the graph was generated using the data
specified in the DC Characteristics section of this datasheet). In
order for the PCA9544A to act as a voltage translator, the V
pass
voltage should be equal to, or lower than the lowest bus voltage. For
example, if the main bus was running at 5 V, and the downstream
buses were 3.3 V and 2.7 V, then V
pass
should be equal to or below
2.7 V to effectively clamp the downstream bus voltages. Looking at
Figure 6, we see that V
pass
(max.) will be at 2.7 V when the
PCA9544A supply voltage is 3.5 V or lower so the PCA9544A
supply voltage could be set to 3.3 V. Pull-up resistors can then be
used to bring the bus voltages to their appropriate levels (see
Figure 13).
More Information can be found in Application Note AN262
PCA954X
family of I
2
C/SMBus multiplexers and switches.
Philips Semiconductors
Product data sheet
PCA9544A
4-channel I
2
C multiplexer with interrupt logic
2004 Sep 29
7
CHARACTERISTICS OF THE I
2
C-BUS
The I
2
C-bus is for 2-way, 2-line communication between different ICs
or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock pulse. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (see Figure 7).
SDA
SCL
SW00363
data line
stable;
data valid
change
of data
allowed
Figure 7. Bit transfer
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 8).
System configuration
A device generating a message is a `transmitter', a device receiving
is the `receiver'. The device that controls the message is the
`master' and the devices which are controlled by the master are the
`slaves' (see Figure 9).
SDA
SCL
SW00365
S
P
SDA
SCL
START condition
STOP condition
Figure 8. Definition of start and stop conditions
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
SW00366
I
2
C
MULTIPLEXER
SLAVE
Figure 9. System configuration
Philips Semiconductors
Product data sheet
PCA9544A
4-channel I
2
C multiplexer with interrupt logic
2004 Sep 29
8
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of
the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT
BY TRANSMITTER
SCL FROM
MASTER
SW00368
DATA OUTPUT
BY RECEIVER
1
2
8
9
S
START condition
clock pulse for
acknowledgement
acknowledge
not acknowledge
Figure 10. Acknowledgement on the I
2
C-bus
SDA
S
0
A
A
1
1
1
0
A2
A1 A0
SLAVE ADDRESS
start condition
R/W
acknowledge
from slave
acknowledge
from slave
B0
CONTROL REGISTER
P
SW00802
B1
B2
X
X
X
X
X
Figure 11. WRITE control register
SDA
S
1
A
NA
1
1
1
0
A2 A1 A0
start condition
R/W
acknowledge
from slave
CONTROL REGISTER
P
stop condition
last byte
SW00378
SLAVE ADDRESS
no acknowledge
from master
B0
INT0
B1
INT1
B2
INT2
X
INT3
Figure 12. READ control register
Philips Semiconductors
Product data sheet
PCA9544A
4-channel I
2
C multiplexer with interrupt logic
2004 Sep 29
9
TYPICAL APPLICATION
PCA9544A
V = 2.7 5.5 V
SD0
SC0
V = 2.7 5.5 V
SD1
SC1
A1
A0
V
SS
SDA
SCL
V
DD
= 3.3 V
V
DD
= 2.7 5.5 V
I
2
C/SMBus MASTER
SW02268
SDA
SCL
A2
INT
INT1
INT0
CHANNEL 0
CHANNEL 1
V = 2.7 5.5 V
SD1
SC1
INT2
CHANNEL 2
V = 2.7 5.5 V
SD1
SC1
INT3
CHANNEL 3
NOTE:
1.
If the device generating the Interrupt has an open-drain output
structure or can be tri-stated, a pull-up resistor is required.
If the device generating the Interrupt has a totem-pole output
structure and cannot be tri-stated, a pull-up resistor is not
required.
The Interrupt inputs should not be left floating.
SEE NOTE (1)
SEE NOTE (1)
SEE NOTE (1)
SEE NOTE (1)
Figure 13. Typical application
Philips Semiconductors
Product data sheet
PCA9544A
4-channel I
2
C multiplexer with interrupt logic
2004 Sep 29
10
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).Voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
DD
DC supply voltage
0.5 to +7.0
V
V
I
DC input voltage
0.5 to +7.0
V
I
I
DC input current
±
20
mA
I
O
DC output current
±
25
mA
I
DD
Supply current
±
100
mA
I
SS
Supply current
±
100
mA
P
tot
total power dissipation
400
mW
T
stg
Storage temperature range
60 to +150
°
C
T
amb
Operating ambient temperature
40 to +85
°
C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
°
C.
Philips Semiconductors
Product data sheet
PCA9544A
4-channel I
2
C multiplexer with interrupt logic
2004 Sep 29
11
DC CHARACTERISTICS
V
DD
= 2.3 V to 3.6 V; V
SS
= 0 V; T
amb
= 40
°
C to +85
°
C; unless otherwise specified. (See page 12 for V
DD
= 3.6 V to 5.5 V)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply
V
DD
Supply voltage
2.3
--
3.6
V
I
DD
Supply current
Operating mode; V
DD
= 3.6 V; no load;
V
I
= V
DD
or V
SS
; f
SCL
= 100 kHz
--
10
30
µ
A
I
stb
Standby current
Standby mode; V
DD
= 3.6 V; no load;
V
I
= V
DD
or V
SS;
f
SCL
= 0 kHz
--
0.1
1
µ
A
V
POR
Power-on reset voltage
(Note 1)
no load; V
I
= V
DD
or V
SS
--
1.5
2.1
V
Input SCL; input/output SDA
V
IL
LOW-level input voltage
0.5
--
0.3V
DD
V
V
IH
HIGH-level input voltage
0.7V
DD
--
6
V
I
O
LOW level output current
V
OL
= 0.4 V
3
7
--
mA
I
OL
LOW-level output current
V
OL
= 0.6 V
6
10
--
mA
I
L
Leakage current
V
I
= V
DD
or V
SS
1
--
+1
µ
A
C
i
Input capacitance
V
I
= V
SS
--
10
13
pF
Select inputs A0 to A2 / INT0 to INT3
V
IL
LOWlevel input voltage
0.5
--
+0.3V
DD
V
V
IH
HIGH-level input voltage
0.7V
DD
--
V
DD
+ 0.5
V
I
LI
Input leakage current
V
I
= V
DD
or V
SS
1
--
+1
µ
A
C
i
Input capacitance
V
I
= V
SS
--
1.6
3
pF
Pass Gate
R
O
Switch resistance
V
CC
= 3.0 V to 3.6 V, V
O
= 0.4 V, I
O
= 15 mA
5
11
30
R
ON
Switch resistance
V
CC
= 2.3 V to 2.7 V, V
O
= 0.4V, I
O
= 10 mA
7
16
55
V
swin
= V
DD
= 3.3 V; I
swout
= 100
µ
A
--
1.9
--
V
Switch output voltage
V
swin
= V
DD
= 3.0 V to 3.6 V; I
swout
= 100
µ
A
1.6
--
2.8
V
V
Pass
Switch output voltage
V
swin
= V
DD
= 2.5 V; I
swout
= 100
µ
A
--
1.5
--
V
V
swin
= V
DD
= 2.3 V to 2.7 V; I
swout
= 100
µ
A
1.1
--
2.0
I
L
Leakage current
V
I
= V
DD
or V
SS
1
--
+1
µ
A
C
io
Input/output capacitance
V
I
= V
SS
--
3
5
pF
INT Output
I
OL
LOW-level output current
V
OL
= 0.4 V
3
7
--
mA
I
OH
HIGH-level output current
--
--
+10
µ
A
NOTES:
1. V
DD
must be lowered to 0.2 V in order to reset part.
2. For operation between published voltage ranges, refer to worst case parameter in both ranges.
Philips Semiconductors
Product data sheet
PCA9544A
4-channel I
2
C multiplexer with interrupt logic
2004 Sep 29
12
DC CHARACTERISTICS
V
DD
= 4.5 V to 5.5 V; V
SS
= 0 V; T
amb
= 40
°
C to +85
°
C; unless otherwise specified. (See page 11 for V
DD
= 2.3 V to 3.6 V)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply
V
DD
Supply voltage
4.5
--
5.5
V
I
DD
Supply current
Operating mode; V
DD
= 5.5 V;
no load; V
I
= V
DD
or V
SS
;
f
SCL
= 100 kHz
--
25
100
µ
A
I
stb
Standby current
Standby mode; V
DD
= 5.5 V;
no load; V
I
= V
DD
or V
SS;
f
SCL
= 0 kHz
--
0.3
1
µ
A
V
POR
Power-on reset voltage
no load; V
I
= V
DD
or V
SS
--
1.7
2.1
V
Input SCL; input/output SDA
V
IL
LOW-level input voltage
0.5
--
0.3V
DD
V
V
IH
HIGH-level input voltage
0.7V
DD
--
6
V
I
O
LOW level output current
V
OL
= 0.4 V
3
--
--
mA
I
OL
LOW-level output current
V
OL
= 0.6 V
6
--
--
mA
I
L
Leakage current
V
I
= V
DD
or V
SS
1
--
+1
µ
A
C
i
Input capacitance
V
I
= V
SS
--
12
13
pF
Select inputs A0 to A2 / INT0 to INT3
V
IL
LOW-level input voltage
0.5
--
+0.3V
DD
V
V
IH
HIGH-level input voltage
0.7V
DD
--
V
DD
+ 0.5
V
I
LI
Input leakage current
pin at V
DD
or V
SS
1
--
+1
µ
A
C
i
Input capacitance
V
I
= V
SS
--
2
5
pF
Pass Gate
R
ON
Switch resistance
V
CC
= 4.5 V to 5.5 V, V
O
= 0.4 V, I
O
= 15 mA
4
9
24
V
Switch output voltage
V
swin
= V
DD
= 5.0 V; I
swout
= 100
µ
A
--
3.6
--
V
V
Pass
Switch output voltage
V
swin
= V
DD
= 4.5 V to 5.5 V; I
swout
= 100
µ
A
2.6
4.5
V
I
L
Leakage current
V
I
= V
DD
or V
SS
1
--
+1
µ
A
C
io
Input/output capacitance
V
I
= V
SS
--
3
5
pF
INT Output
I
OL
LOW-level output current
V
OL
= 0.4 V
3
--
--
mA
I
OH
HIGH-level output current
--
--
+10
µ
A
NOTES:
1. V
DD
must be lowered to 0.2 V in order to reset part.
2. For operation between published voltage ranges, refer to worst case parameter in both ranges.
Philips Semiconductors
Product data sheet
PCA9544A
4-channel I
2
C multiplexer with interrupt logic
2004 Sep 29
13
AC CHARACTERISTICS
SYMBOL
PARAMETER
STANDARD-MODE
I
2
C-bus
FAST-MODE
I
2
C-bus
UNIT
MIN
MAX
MIN
MAX
t
pd
Propagation delay from SDA to SD
n
or SCL to SC
n
--
0.3
1
--
0.3
1
ns
f
SCL
SCL clock frequency
0
100
0
400
kHz
t
BUF
Bus free time between a STOP and START condition
4.7
--
1.3
--
µ
s
t
HD;STA
Hold time (repeated) START condition
After this period, the first clock pulse is generated
4.0
--
0.6
--
µ
s
t
LOW
LOW period of the SCL clock
4.7
--
1.3
--
µ
s
t
HIGH
HIGH period of the SCL clock
4.0
--
0.6
--
µ
s
t
SU;STA
Set-up time for a repeated START condition
4.7
--
0.6
--
µ
s
t
SU;STO
Set-up time for STOP condition
4.0
--
0.6
--
µ
s
t
HD;DAT
Data hold time
0
2
3.45
0
2
0.9
µ
s
t
SU;DAT
Data set-up time
250
--
100
--
ns
t
R
Rise time of both SDA and SCL signals
--
1000
20 + 0.1C
b
3
300
ns
t
F
Fall time of both SDA and SCL signals
--
300
20 + 0.1C
b
3
300
µ
s
C
b
Capacitive load for each bus line
--
400
--
400
µ
s
t
SP
Pulse width of spikes which must be suppressed
by the input filter
--
50
--
50
ns
t
VD:DATL
Data valid (HL)
4
--
1
--
1
µ
s
t
VD:DATH
Data valid (LH)
4
--
0.6
--
0.6
µ
s
t
VD:ACK
Data valid Acknowledge
--
1
--
1
µ
s
INT
t
iv
INTn to INT active valid time
4
--
4
--
4
µ
s
t
ir
INTn to INT inactive delay time
4
--
2
--
2
µ
s
L
pwr
LOW level pulse width rejection of INTn inputs
4
10
--
1
--
ns
H
pwr
HIGH level pulse width rejection of INTn inputs
4
500
--
500
--
ns
NOTES:
1. Pass gate propagation delay is calculated from the 20
typical R
ON
and and the 15 pF load capacitance.
2. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IH(min)
of the SCL signal) in order to bridge
the undefined region of the falling edge of SCL.
3. C
b
= total capacitance of one bus line in pF.
4. Measurements taken with 1 k
pull-up resistor and 50 pF load.
t
SP
t
BUF
t
HD;STA
P
P
S
t
LOW
t
R
t
HD;DAT
t
F
t
HIGH
t
SU;DAT
t
SU;STA
Sr
t
HD;STA
t
SU;STO
SDA
SCL
SU00645
Figure 14. Definition of timing on the I
2
C-bus
Philips Semiconductors
Product data sheet
PCA9544A
4-channel I
2
C multiplexer with interrupt logic
2004 Sep 29
14
SO20:
plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
Philips Semiconductors
Product data sheet
PCA9544A
4-channel I
2
C multiplexer with interrupt logic
2004 Sep 29
15
TSSOP20:
plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
Philips Semiconductors
Product data sheet
PCA9544A
4-channel I
2
C multiplexer with interrupt logic
2004 Sep 29
16
HVQFN20:
plastic thermal enhanced very thin quad flat package; no leads; 20 terminals;
body 5 x 5 x 0.85 mm
SOT662-1
Philips Semiconductors
Product data sheet
PCA9544A
4-channel I
2
C multiplexer with interrupt logic
2004 Sep 29
17
REVISION HISTORY
Rev
Date
Description
_2
2004929
Product data sheet (9397 750 13931). Supersedes data of 2004 Jul 28 (9397 750 13301).
Modifications:
·
Table 1. "Control Register; Write -- Channel Selection / Read -- Channel Status" on page 5:
add `no channel selected; power-up default state' row to bottom of table
·
DC characteristics table (V
DD
= 2.3 V to 3.6 V) on page 11:
Supply
change I
DD
Typ. from 20
µ
A to 10
µ
A
change I
DD
Max. from 50
µ
A to 30
µ
A
Input SCL; input/output SDA
change I
OL
Typ. (V
OL
= 0.4 V) from "" to 7 mA
change I
OL
Typ. (V
OL
= 0.6 V) from "" to 10 mA
change C
i
Typ. from 12 pF to 10 pF
Select inputs A0 to A2 / INT0 to INT3
change Test conditions for I
LI
from "pin at V
DD
or V
SS
" to "V
I
= V
DD
or V
SS
"
INT output
change I
OL
Typ. from "" to 7 mA
change I
OH
Max. from +100
µ
A to +10
µ
A
Add Note 2.
·
DC characteristics table (V
DD
= 4.5 V to 5.5 V) on page 12:
change description from "V
DD
= 3.6 V to 5.5 V" to "V
DD
= 4.5 V to 5.5 V"
Supply
change V
DD
Min. from 3.6 V to 4.5 V
change I
DD
Typ. from 65
µ
A to 25
µ
A
Input SCL; input/output SDA
remove parameters I
IL
and I
IH
add parameter I
L
Select inputs A0 to A2 / INT0 to INT3; change I
LI
Max. from +50
µ
A to +1
µ
A
Pass Gate
change I
L
Min. from 10
µ
A to 1
µ
A
change I
L
Max. from +100
µ
A to +1
µ
A
INT output; change I
OH
Max from +100
µ
A to +10
µ
A
Add Note 2.
·
AC characteristics table on page 13:
add reference to (new) Note 4 at parameters t
VD:DATL
and t
VD:DATH
INT
Add reference to (new) Note 4 in all 4 parameter descriptions
L
pwr
and H
pwr
: change "or" to "of"
Add Note 4.
_1
20040728
Objective data sheet (9397 750 13301).
Philips Semiconductors
Product data sheet
PCA9544A
4-channel I
2
C multiplexer with interrupt logic
2004 Sep 29
18
Purchase of Philips I
2
C components conveys a license under the Philips' I
2
C patent
to use the components in the I
2
C system provided the system conforms to the
I
2
C specifications defined by Philips. This specification can be ordered using the
code 9398 393 40011.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described
or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
©
Koninklijke Philips Electronics N.V. 2004
All rights reserved. Printed in U.S.A.
Date of release: 09-04
Document number:
9397 750 13931
Philips
Semiconductors
Data sheet status
[1]
Objective data sheet
Preliminary data sheet
Product data sheet
Product
status
[2] [3]
Development
Qualification
Production
Definitions
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
Data sheet status
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Level
I
II
III
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