Philips Semiconductors

Product data

PCA9501

8-bit I

C and SMBus I/O port with interrupt,

2-kbit EEPROM and 6 address pins

2003 Sep 12

FEATURES

8 general purpose input/output expander/collector

Replacement for PCF8574 with integrated 2-kbit EEPROM

Internal 256

8 EEPROM

Self timed write cycle (5 ms typ)

16 byte page write operation

C and SMBus interface logic

Internal power-on reset

Noise filter on SCL/SDA inputs

Active low interrupt output

6 address pins allowing up to 64 devices on the I

C/SMBus

No glitch on power-up

Supports hot insertion

Power-up with all channels configured as inputs

Low standby current

Operating power supply voltage range of 2.5 V to 3.6 V

5 V tolerant inputs/outputs

0 to 400 kHz clock frequency

ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101

Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA

Packages offered: SO20, TSSOP20, HVQFN20

DESCRIPTION

The PCA9501 is an 8-bit I/O expander with an on-board 2-kbit
EEPROM.

The I/O expandable eight quasi bidirectional data pins can be
independently assigned as inputs or outputs to monitor board level
status or activate indicator devices such as LEDs. The system
master writes to the I/O configuration bits in the same way as for the
PCF8574. The data for each Input or Output is kept in the
corresponding Input or Output register. The system master can read
all registers.

The EEPROM can be used to store error codes or board
manufacturing data for read-back by application software for
diagnostic purposes and are included in the I/O expander package.

The PCA9501 Active-LOW open-drain interrupt output is activated
when any input state differes from its corresponding input port
register state. It is used to indicate to the system master that an
input state has changed and the device needs to be interrogated.

The PCA9501 has six address pins with internal pull-up resistors
allowing up to 64 devices to share the common two wire I

software protocol serial data bus. The fixed GPIO address starts
with "1" and the fixed EEPROM I

C address starts with "0", so the

PCA9501 appears as two separate devices to the bus master.

The PCA9501 supports hot insertion to facilitate usage in removable
cards on backplane systems.

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

TOPSIDE MARK

DRAWING NUMBER

20-pin plastic SO

-40 to +85

PCA9501D

SOT163-1

20-Pin Plastic TSSOP

-40 to +85

PCA9501PW

PCA9501

SOT360-1

20-Pin Plastic HVQFN

-40 to +85

PCA9501BS

9501

SOT662-1

Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I

C patent.

C is a trademark of Philips Semiconductors Corporation.

Philips Semiconductors

Product data

PCA9501

8-bit I

C and SMBus I/O port with interrupt,

2-kbit EEPROM and 6 address pins

2003 Sep 12

PIN CONFIGURATION - SO, TSSOP

SW00903

I/O0

I/O3

SDA

SCL

I/O1

I/O2

INT

I/O7

I/O6

I/O5

I/O4

PCA9501

Figure 1. Pin configuration - SO, TSSOP

PIN CONFIGURATION - HVQFN

SW02017

TOP VIEW

I/O0

I/O1

I/O2

I/O3

INT

I/O4

I/O7

I/O5

I/O6

SCL

SDA

Figure 2. Pin configuration - HVQFN

PIN DESCRIPTION

PIN NUMBER

SYMBOL

NAME AND FUNCTION

SO, TSSOP

HVQFN

1, 2, 3, 9, 11, 12

19, 20, 1, 7, 9, 10

A0-5

Address lines (internal pull-up)

4, 5, 6, 7

2, 3, 4, 5

I/O0-3

Quasi-bidirectional I/O pins

INT

Active low interrupt output (open drain)

Supply ground

13, 14, 15, 16

11, 12, 13, 14

I/O4-7

Quasi-bidirectional I/O pins

Active low write control pin

SCL

C serial clock

SDA

C serial data

Supply voltage

Philips Semiconductors

Product data

PCA9501

8-bit I

C and SMBus I/O port with interrupt,

2-kbit EEPROM and 6 address pins

2003 Sep 12

FUNCTIONAL DESCRIPTION

SW00788

WRITE PULSE

DATA FROM
SHIFT REGISTER

POWER-ON
RESET

READ PULSE

DATA TO
SHIFT REGISTER

I/O0 TO I/O7

100

TO INTERRUPT LOGIC

Figure 4. Simplified schematic diagram of each I/O

DEVICE ADDRESSING

Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9501 is shown in
Figure 5. Internal pullup resistors are incorporated on the hardware selectable address pins.

(a) I/O EXPANDER

(b) MEMORY

SW02006

SLAVE ADDRESS

HARDWARE

PROGRAMMABLE

FIXED

R/W

HARDWARE

PROGRAMMABLE

Figure 5. PCA9501 slave addresses

The last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected while a logic 0 selects a write
operation.

CONTROL REGISTER

The PCA9501 contains a single 8-bit register called the Control Register, which can be written and read via the I

C bus. This register is sent

after a successful acknowledgment of the slave address.

It contains the I/O operation information.

Philips Semiconductors

Product data

PCA9501

8-bit I

C and SMBus I/O port with interrupt,

2-kbit EEPROM and 6 address pins

2003 Sep 12

I/O OPERATIONS (see also Figure 4)

Each of the PCA9501's eight I/Os can be independently used as an input or output. Output data is transmitted to the port by the I/O WRITE
mode (see Figure 6). Input I/O data is transferred from the port to the microcontroller by the READ mode (See Figure 7).

DATA 1

DATA 2

SDA

SCL

t pv

DATA 2 VALID

DATA 1 VALID

SW00649

ACKNOWLEDGE
FROM SLAVE

R/W

START CONDITION

ACKNOWLEDGE
FROM SLAVE

SLAVE ADDRESS (I/O EXPANDER)

DATA TO PORT

WRITE TO
PORT

DATA OUT
FROM PORT

Figure 6. I/O WRITE mode (output)

DATA 1

DATA 4

SDA

t ph

t ps

DATA 4

DATA 2

DATA 3

SW00650

SLAVE ADDRESS (I/O EXPANDER)

DATA FROM PORT

READ FROM
PORT

DATA INTO
PORT

START CONDITION

ACKNOWLEDGE
FROM SLAVE

R/W

ACKNOWLEDGE
FROM MASTER

STOP
CONDITION

DATA 1

INT

t iv

t ir

Figure 7. I/O READ mode (input)

Philips Semiconductors

Product data

PCA9501

8-bit I

C and SMBus I/O port with interrupt,

2-kbit EEPROM and 6 address pins

2003 Sep 12

Quasi-bidirectional I/Os (see Figure 8)

A quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data direction. At power-on the I/Os are HIGH.
In this mode, only a current source to V

is active. An additional strong pull-up to V

allows fast rising edges into heavily loaded outputs.

These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The I/Os should be HIGH before
being used as inputs.

SDA

SCL

SW00904

ACKNOWLEDGE
FROM SLAVE

R/W

START CONDITION

ACKNOWLEDGE
FROM SLAVE

SLAVE ADDRESS (I/O EXPANDER)

DATA TO PORT

I/O3

I/O3
OUTPUT
VOLTAGE

I/O3
PULL-UP
OUTPUT
CURRENT

OHt

Figure 8. Transient pull-up current I

OHt

while I/O3 changes from LOW-to-HIGH and back to LOW

Philips Semiconductors

Product data

PCA9501

8-bit I

C and SMBus I/O port with interrupt,

2-kbit EEPROM and 6 address pins

2003 Sep 12

Interrupt (see Figs 9 and 12)

The PCA9501 provides an open drain output (INT) which can be fed
to a corresponding input of the microcontroller. This gives these
chips a type of master function which can initiate an action
elsewhere in the system.

An interrupt is generated by any rising or falling edge of the port
inputs in the input mode. After time t

the signal INT is valid.

Resetting and reactivating the interrupt circuit is achieved when data
on the port is changed to the original setting or data is read from or
written to the port which has generated the interrupt.

Resetting occurs as follows:

In the READ mode at the acknowledge bit after the rising edge of
the SCL signal

In the WRITE mode at the acknowledge bit after the
HIGH-to-LOW transition of the SCL signal

Returning of the port data to its original setting.

Interrupts which occur during the acknowledge clock pulse may
be lost (or very short) due to the resetting of the interrupt during
this pulse.

Each change of the I/Os after resetting will be detected and, after
the next rising clock edge, will be transmitted as INT. Reading from
or writing to another device does not affect the interrupt circuit.

SW00790

PCA9501

(1)

INT

PCA9501

(2)

INT

PCA9501

(16)

INT

MICROCONTROLLER

INT

Figure 9. Application of multiple PCA9501s with interrupt

SDA

SCL

t ir

SW00791

ACKNOWLEDGE
FROM SLAVE

R/W

START CONDITION

STOP CONDITION

SLAVE ADDRESS (I/O EXPANDER)

DATA FROM PORT

DATA INTO I/O5

INT

I/O5

t iv

Figure 10. Interrupt generated by a change of input to I/O5

Philips Semiconductors

Product data

PCA9501

8-bit I

C and SMBus I/O port with interrupt,

2-kbit EEPROM and 6 address pins

2003 Sep 12

MEMORY OPERATIONS

Write operations

Write operations require an additional address field to indicate the
memory address location to be written. The address field is eight
bits long providing access to any one of the 256 words of memory.
There are two types of write operations, byte write and page write.

Write operation is possible when WC control pin put at a low logic
level (0). When this control signal is set at 1, write operation is not
possible and data in the memory is protected.

Byte Write and Page Write explained below assume that Write
Control pin (WC) is set to 0.

Byte Write (see Figure 11)
To perform a byte write the start condition is followed by the memory
slave address and the R/W bit set to 0. The PCA9501 will respond
with an acknowledge and then consider the next eight bits sent as

the word address and the eight bits after the word address as the
data. The PCA9501 will issue an acknowledge after the receipt of
both the word address and the data. To terminate the data transfer
the master issues the stop condition, initiating the internal write cycle
to the non-volatile memory. Only write and read operations to the
quasi-bidirectional I/Os are allowed during the internal write cycle.

Page Write (see Figure 12)
A page write is initiated in the same way as the byte write, if after
sending the first word of data, the stop condition is not received the
PCA9501 considers subsequent words as data. After each data
word the PCA9501 responds with an acknowledge and the four
least significant bits of the memory address field are incremented.
Should the master not send a stop condition after 16 data words the
address counter will return to its initial value and overwrite the data
previously written. After the receipt of the stop condition the inputs
will behave as with the byte write during the internal write cycle.

SW00651

A5 A4 A3 A2 A1 A0

SDA

ACKNOWLEDGE
FROM SLAVE

R/W

START CONDITION

ACKNOWLEDGE
FROM SLAVE

SLAVE ADDRESS (MEMORY)

WORD ADDRESS

DATA

ACKNOWLEDGE

FROM SLAVE

STOP CONDITION.
WRITE TO THE
MEMORY IS
PERFORMED

Figure 11. Byte write

SW00652

ACKNOWLEDGE

FROM SLAVE

A5 A4 A3 A2 A1 A0

SDA

ACKNOWLEDGE
FROM SLAVE

R/W

START CONDITION

ACKNOWLEDGE
FROM SLAVE

SLAVE ADDRESS (MEMORY)

WORD ADDRESS

DATA TO MEMORY

DATA n

DATA n + 3

STOP CONDITION.

WRITE TO THE MEMORY

IS PERFORMED

DATA TO MEMORY

Figure 12. Page Write

Philips Semiconductors

Product data

PCA9501

8-bit I

C and SMBus I/O port with interrupt,

2-kbit EEPROM and 6 address pins

2003 Sep 12

Read operations

PCA9501 read operations are initiated in an identical manner to
write operations with the exception that the memory slave address'
R/W bit is set to a one. There are three types of read operations;
current address, random and sequential.

Current Address Read (see Figure 13)
The PCA9501 contains an internal address counter that increments
after each read or write access, as a result if the last word accessed
was at address n then the address counter contains the address
n+1.

When the PCA9501 receives its memory slave address with the
R/W bit set to one it issues an acknowledge and uses the next eight
clocks to transmit the data contained at the address stored in the
address counter. The master ceases the transmission by issuing the
stop condition after the eighth bit. There is no ninth clock cycle for
the acknowledge.

Random Read (see Figure 14)
The PCA9501's random read mode allows the address to be read
from to be specified by the master. This is done by performing a
dummy write to set the address counter to the location to be read.

The master must perform a byte write to the address location to be
read, but instead of transmitting the data after receiving the
acknowledge from the PCA9501 the master reissues the start
condition and memory slave address with the R/W bit set to one.
The PCA9501 will then transmit an acknowledge and use the next
eight clock cycles to transmit the data contained in the addressed
location. The master ceases the transmission by issuing the stop
condition after the eighth bit, omitting the ninth clock cycle
acknowledge.

Sequential Read (see Figure 15)
The PCA9501 sequential read is an extension of either the current
address read or random read. If the master doesn't issue a stop
condition after it has received the eighth data bit, but instead issues
an acknowledge, the PCA9501 will increment the address counter
and use the next eight cycles to transmit the data from that location.
The master can continue this process to read the contents of the
entire memory. Upon reaching address 255 the counter will return to
address 0 and continue transmitting data until a stop condition is
received. The master ceases the transmission by issuing the stop
condition after the eighth bit, omitting the ninth clock cycle
acknowledge.

SW00653

SDA

ACKNOWLEDGE
FROM SLAVE

R/W

START CONDITION

SLAVE ADDRESS (MEMORY)

DATA FROM MEMORY

STOP
CONDITION

Figure 13. Current Address Read

SW00654

SDA

A5 A4 A3 A2 A1 A0

START
CONDITION

R/W

ACKNOWLEDGE
FROM SLAVE

ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE
FROM SLAVE

DATA FROM MEMORY

STOP
CONDITION

START
CONDITION

1 A5 A4 A3 A2 A1 A0

R/W

SLAVE ADDRESS (MEMORY)

WORD ADDRESS

SLAVE ADDRESS (MEMORY)

Figure 14. Random Read

SW00655

SDA

SLAVE ADDRESS (MEMORY)

DATA FROM MEMORY

A5 A4 A3 A2 A1 A0

START CONDITION

R/W

ACKNOWLEDGE
FROM SLAVE

ACKNOWLEDGE
FROM MASTER

DATA n

ACKNOWLEDGE
FROM MASTER

DATA n+X

STOP
CONDITION

DATA n+1

DATA FROM MEMORY

Figure 15. Sequential Read

Philips Semiconductors

Product data

PCA9501

8-bit I

C and SMBus I/O port with interrupt,

2-kbit EEPROM and 6 address pins

2003 Sep 12

CHARACTERISTICS OF THE I

C-BUS

The I

C-bus is for 2-way, 2-line communication between different ICs

or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.

Bit transfer

One data bit is transferred during each clock phase. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (See Figure 16).

Start and stop conditions

Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 17).

System configuration

A device generating a message is a "transmitter", a device receiving
is the "receiver". The device that controls the message is the
"master" and the devices which are controlled by the master are the
"slaves" (see Figure 18).

SDA

SCL

SW00542

DATA LINE

STABLE;

DATA VALID

CHANGE

OF DATA

ALLOWED

Figure 16. Bit transfer

SDA

SCL

SDA

SCL

SW00543

START CONDITION

STOP CONDITION

Figure 17. Definition of start and stop conditions

SDA

SCL

SW00544

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER/

RECEIVER

Figure 18. System configuration

Philips Semiconductors

Product data

PCA9501

8-bit I

C and SMBus I/O port with interrupt,

2-kbit EEPROM and 6 address pins

2003 Sep 12

Acknowledge (see Figure 19)

The number of data bytes transferred between the start and the stop
conditions from transmitter to receiver is not limited. Each byte of
eight bits is followed by one acknowledge bit. The acknowledge bit
is a HIGH level put on the bus by the transmitter whereas the
master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge
after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked

out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that
the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse, set-up and hold times must be
taken into account.

A master receiver must signal an end of data to the transmitter by
not generating an acknowledge on the last byte that has been
clocked out of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a stop condition.

SW00545

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER

ACKNOWLEDGE

NOT ACKNOWLEDGE

CLOCK PULSE FOR
ACKNOWLEDGEMENT

START
CONDITION

Figure 19. Acknowledgment on the I

C-bus

Philips Semiconductors

Product data

PCA9501

8-bit I

C and SMBus I/O port with interrupt,

2-kbit EEPROM and 6 address pins

2003 Sep 12

TYPICAL APPLICATION

Applications

Board version tracking and configuration

Board health monitoring and status reporting

Multi-card systems in Telecom, Networking, and Base Station
Infrastructure Equipment

Field recall and troubleshooting functions for installed boards

General-purpose integrated I/O with memory

Replacement for PCF8574 with integrated 2-kbit EEPROM

Bus master sees GPIO and EEPROM as two separate devices

Six hardware address pins allow up to 64 PCA9501s to be located
in the same I

C/SMBus

CONTROL

EEPROM

GPIO

ASIC

BACKPLANE

CPU

MONITORING

AND

CONTROL

INPUTS

ALARM

LEDs

PCA9501

CARD ID, SUBROUTINES, CONFIGURATION DATA, OR REVISION HISTORY

SW02007

UP TO 64 CARDS

CONFIGURATION CONTROL

Figure 20. Typical application

A central processor/controller typically located on the system main
board can use the 400 kHz I

C/SMBus to poll the PCA9501 devices

located on the system cards for status or version control type of
information. The PCA9501 may be programmed at manufacturing to
store information regarding board build, firmware version,

manufacturer identification, configuration option data

...

Alternately,

these devices can be used as convenient interface for board
configuration, thereby utilizing the I

C/SMBus as an intra-system

communication bus.

Philips Semiconductors

Product data

PCA9501

8-bit I

C and SMBus I/O port with interrupt,

2-kbit EEPROM and 6 address pins

2003 Sep 12

TYPICAL APPLICATION

SW01078

I/0

SCL

SDA

INT

RESET

MASTER

CONTROLLER

GND

SCL

SDA

PCA9501

SUBSYSTEM 3

(e.g. alarm

system)

SUBSYSTEM 2

(e.g. counter)

SUBSYSTEM 1

(e.g. temp sensor)

INT

ALARM

Controlled Switch
(e.g. CBT device)

ENABLE

1.6 k

1.1 k

2 k

NOTE: GPIO device address configured as 0110000 for this example

EEPROM device address configured as 1110000 for this example
I/0

, I/0

, configured as outputs

I/0

, I/0

, configured as inputs

I/0

, I/0

, are not used and have to be configured as outputs

2 k

(optional)

Figure 21. Typical application

Philips Semiconductors

Product data

PCA9501

8-bit I

C and SMBus I/O port with interrupt,

2-kbit EEPROM and 6 address pins

2003 Sep 12

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.

SYMBOL

PARAMETER

MIN

MAX

UNIT

Supply Voltage

-0.5

4.0

Input Voltage

- 0.5

5.5

DC Input Current

-20

DC Output Current

-25

Supply Current

-100

100

Supply Current

-100

100

tot

Total Power Dissipation

400

Total Power Dissipation per Output

100

STG

Storage Temperature

-65

+150

AMB

Operating Temperature

-40

+85

DC ELECTRICAL CHARACTERISTICS

amb

= -40

C to +85

C unless otherwise specified; V

= 3.3 V

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

Supply

Supply Voltage

2.5

3.3

3.6

DDQ

Standby Current; A

thru A

, WC = HIGH

DD1

Supply Current Read

DD2

Supply Current Write

POR

Power on Reset Voltage

2.4

Input SCL; input, output SDA

Input LOW voltage

-0.5

0.3 V

Input HIGH voltage

0.7 V

5.5

Output LOW current @ V

= 0.4 V

Input leakage current @ V

= V

or V

-1

Input capacitance @ V

= V

I/O Expander Port

Input LOW voltage

-0.5

0.3 V

Input HIGH voltage

0.7 V

5.5

IHL(max)

Input current through protection diodes

-400

400

Output LOW current @ V

= 1 V

Output HIGH current @ V

= V

100

300

OHt

Transient pull-up current

Input Capacitance

Output Capacitance

Address Inputs A

thru A

, WC input

Input LOW voltage

-0.5

0.3 V

Input HIGH voltage

0.7 V

5.5

Input leakage current @ V

= V

-1

Input leakage (pull-up) current @ V

= V

100

Interrupt output INT

Low level output current; V

= 0.4 V

1.6

Leakage current @ V

= V

or V

-1

Philips Semiconductors

Product data

PCA9501

8-bit I

C and SMBus I/O port with interrupt,

2-kbit EEPROM and 6 address pins

2003 Sep 12

NON-VOLATILE STORAGE SPECIFICATIONS

PARAMETER

SPECIFICATION

Memory cell data retention

10 years minimum

Number of memory cell write cycles

100,000 cycles minimum

C-BUS TIMING CHARACTERISTICS

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

C-bus timing (see Figure 22; Note 1)

SCL

SCL clock frequency

400

kHz

tolerable spike width on bus

BUF

bus free time

1.3

SU;STA

START condition set-up time

0.6

HD;STA

START condition hold time

0.6

SCL and SDA rise time

0.3

SCL and SDA fall time

0.3

SU;DAT

data set-up time

250

HD;DAT

data hold time

VD;DAT

SCL LOW to data out valid

1.0

SU;STO

STOP condition set-up time

0.6

NOTE:
1. All the timing values are valid within the operating supply voltage and ambient temperature range and refer to V

and V

with an input

voltage swing of V

to V

PORT TIMING CHARACTERISTICS

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

Output data valid; C

100 pF

Input data setup time; C

100 pF

Input data hold time; C

100 pF

Interrupt input data valid time; C

100 pF

Interrupt reset time; C

100 pF

Philips Semiconductors

Product data

PCA9501

8-bit I

C and SMBus I/O port with interrupt,

2-kbit EEPROM and 6 address pins

2003 Sep 12

handbook, full pagewidth

SCL

SDA

MBD820

BIT 0

LSB

(R/W)

HD;STA

SU;DAT

HD;DAT

VD;DAT

SU;STO

BUF

SU;STA

1 / f

SCL

START

CONDITION

(S)

BIT 7

MSB

(A7)

BIT 6

(A6)

ACKNOWLEDGE

(A)

STOP

CONDITION

(P)

SW00561

PROTOCOL

Figure 22.

POWER-UP TIMING

SYMBOL

PARAMETER

MAX.

UNIT

PUR

Power-up to Read Operation

PUW

Power-up to Write Operation

NOTE:
1. t

PUR

and t

PUW

are the delays required from the time V

is stable until the specified operation can be initiated. These parameters are

guaranteed by design.

WRITE CYCLE LIMITS

SYMBOL

PARAMETER

MIN.

TYP.

(5)

MAX.

UNIT

Write Cycle Time

NOTE:
1. t

is the maximum time that the device requires to perform the internal write operation.

Write Cycle Timing

SCL

SDA

8th Bit

Word n

ACK

Stop
Condition

Start
Condition

MEMORY

ADDRESS

SW00560

Figure 23.

Philips Semiconductors

Product data

PCA9501

8-bit I

C and SMBus I/O port with interrupt,

2-kbit EEPROM and 6 address pins

2003 Sep 12

SOLDERING

Introduction

There is no soldering method that is ideal for all IC packages. Wave
soldering is often preferred when through-hole and surface mounted
components are mixed on one printed-circuit board. However, wave
soldering is not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these situations
reflow soldering is often used.

This text gives a very brief insight to a complex technology. A more
in-depth account of soldering ICs can be found in our IC Package
Databook (order code 9398 652 90011).

DIP

Soldering by dipping or by wave
The maximum permissible temperature of the solder is 260

solder at this temperature must not be in contact with the joint for
more than 5 seconds. The total contact time of successive solder
waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the
temperature of the plastic body must not exceed the specified
maximum storage temperature (T

stg

max). If the printed-circuit board

has been pre-heated, forced cooling may be necessary immediately
after soldering to keep the temperature within the permissible limit.

Repairing soldered joints

Apply a low voltage soldering iron (less than 24 V) to the lead(s) of
the package, below the seating plane or not more than 2 mm above
it. If the temperature of the soldering iron bit is less than 300

C it

may remain in contact for up to 10 seconds. If the bit temperature is
between 300 and 400

C, contact may be up to 5 seconds.

SO and SSOP

Reflow soldering
Reflow soldering techniques are suitable for all SO and SSOP
packages.

Reflow soldering requires solder paste (a suspension of fine solder
particles, flux and binding agent) to be applied to the printed-circuit
board by screen printing, stencilling or pressure-syringe dispensing
before package placement.

Several techniques exist for reflowing; for example, thermal
conduction by heated belt. Dwell times vary between 50 and 300

seconds depending on heating method. Typical reflow temperatures
range from 215 to 250

Preheating is necessary to dry the paste and evaporate the binding
agent. Preheating duration: 45 minutes at 45

Wave soldering
Wave soldering is not recommended for SSOP packages. This is
because of the likelihood of solder bridging due to closely-spaced
leads and the possibility of incomplete solder penetration in
multi-lead devices.

If wave soldering cannot be avoided, the following conditions
must be observed:

A double-wave (a turbulent wave with high upward pressure
followed by a smooth laminar wave) soldering technique
should be used.

The longitudinal axis of the package footprint must be
parallel to the solder flow and must incorporate solder
thieves at the downstream end.

Even with these conditions, only consider wave soldering
SSOP packages that have a body width of 4.4 mm, that is
SSOP16 (SOT369-1) or SSOP20 (SOT266-1).

During placement and before soldering, the package must be fixed
with a droplet of adhesive. The adhesive can be applied by screen
printing, pin transfer or syringe dispensing. The package can be
soldered after the adhesive is cured.

Maximum permissible solder temperature is 260

C, and maximum

duration of package immersion in solder is 10 seconds, if cooled to
less than 150

C within 6 seconds. Typical dwell time is 4 seconds at

250

A mildly-activated flux will eliminate the need for removal of
corrosive residues in most applications.

Repairing soldered joints
Fix the component by first soldering two diagonally opposite end
leads. Use only a low voltage soldering iron (less than 24 V) applied
to the flat part of the lead. Contact time must be limited to
10 seconds at up to 300

C. When using a dedicated tool, all other

leads can be soldered in one operation within 2 to 5 seconds
between 270 and 320

Philips Semiconductors

Product data

PCA9501

8-bit I

C and SMBus I/O port with interrupt,

2-kbit EEPROM and 6 address pins

2003 Sep 12

Purchase of Philips I

C components conveys a license under the Philips' I

C patent

to use the components in the I

C system provided the system conforms to the

C specifications defined by Philips. This specification can be ordered using the

code 9398 393 40011.

Definitions

Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described
or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.

Contact information

For additional information please visit
http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.

Koninklijke Philips Electronics N.V. 2003

Date of release: 09-03

Document order number:

9397 750 12058

Philips
Semiconductors

Data sheet status

[1]

Objective data

Preliminary data

Product data

Product
status

[2] [3]

Development

Qualification

Production

Definitions

This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.

This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.

This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).

Data sheet status

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Level

III

Part Number PCA9501