Philips Semiconductors

Product data

P82B96

Dual bi-directional bus buffer

2004 Mar 26

FEATURES

Bi-directional data transfer of I

C-bus signals

Isolates capacitance allowing 400 pF on Sx/Sy side and
4000 pF on Tx/Ty side

Tx/Ty outputs have 60 mA sink capability for driving
low impedance or high capacitive buses

400 kHz operation over at least 20 meters of wire (see

AN10148)

Supply voltage range of 2 V to 15 V with I

C logic levels on Sx/Sy

side independent of supply voltage

Splits I

C signal into pairs of forward/reverse Tx/Rx, Ty/Ry signals

for interface with opto-electrical isolators and similar devices that
need uni-directional input and output signal paths.

Low power supply current

ESD protection exceeds 3500 V HBM per JESD22-A114,
250 V DIP package / 400 V SO package MM per JESD22-A115,
and 1000 V CDM per JESD22-C101

Latch-up free (bipolar process with no latching structures)

Packages offered: DIP, SO, and TSSOP

TYPICAL APPLICATIONS

Interface between I

C buses operating at different logic levels

(e.g., 5 V and 3 V or 15 V)

Interface between I

C and SMB (350

╣

A) bus standard.

Simple conversion of I

C SDA or SCL signals to multi-drop

differential bus hardware, e.g., via compatible PCA82C250.

Interfaces with Opto-couplers to provide Opto isolation between
I

C-bus nodes up to 400 kHz.

DESCRIPTION

The P82B96 is a bipolar IC that creates a non-latching,
bi-directional, logic interface between the normal I

C-bus and a

range of other bus configurations. It can interface I

C-bus logic

signals to similar buses having different voltage and current levels.

For example it can interface to the 350

╣

A SMB bus, to 3.3 V logic

devices, and to 15 V levels and/or low impedance lines to improve
noise immunity on longer bus lengths.

It achieves this interface without any restrictions on the normal I

protocols or clock speed. The IC adds minimal loading to the I

node, and loadings of the new bus or remote I

C nodes are not

transmitted or transformed to the local node. Restrictions on the
number of I

C devices in a system, or the physical separation

between them, are virtually eliminated. Transmitting SDA/SCL
signals via balanced transmission lines (twisted pairs) or with
galvanic isolation (opto-coupling) is simple because separate
directional Tx and Rx signals are provided. The Tx and Rx signals
may be directly connected, without causing latching, to provide an
alternative bi-directional signal line with I

C properties.

PIN CONFIGURATIONS
8-pin dual in-line, SO, TSSOP

GND

SU01011

PINNING

аааааа

SYMBOL

ааа

PIN

аааааааааа

DESCRIPTION

аааааа

ааа

аааааааааа

C-bus (SDA or SCL)

аааааа

ааа

аааааааааа

Receive signal

аааааа

ааа

аааааааааа

Transmit signal

аааааа

GND

ааа

аааааааааа

Negative Supply

аааааа

ааа

аааааааааа

Transmit signal

аааааа

ааа

аааааааааа

Receive signal

аааааа

ааа

аааааааааа

C-bus (SDA or SCL)

аааааа

ааа

аааааааааа

Positive supply

SPECIAL NOTE:

Two or more Sx or Sy I/Os must not be interconnected. The P82B96
design does not support this configuration. Bi-directional I

C signals

do not allow any direction control pin so, instead, slightly different
logic low voltage levels are used at Sx/Sy to avoid latching of this
buffer. A "regular I

C low" applied at the Rx/Ry of a P82B96 will be

propagated to Sx/Sy as a "buffered low" with a slightly higher
voltage level. If this special "buffered low" is applied to the Sx/Sy of
another P82B96 that second P82B96 will not recognize it as a
"regular I

C-bus low" and will not propagate it to its Tx/Ty output.

The Sx/Sy side of P82B96 may not be connected to similar buffers
that rely on special logic thresholds for their operation, for example
PCA9511, PCA9515, or PCA9518. The Sx/Sy side is only intended
for, and compatible with, the normal I

C logic voltage levels of I

master and slave chips--or even Tx/Rx signals of a second P82B96
if required. The Tx/Rx and Ty/Ry I/O pins use the standard I

C logic

voltage levels of all I

C parts. There are NO restrictions on the

interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s,
for example in a star or multi-point configuration with the Tx/Rx and
Ty/Ry I/O pins on the common bus and the Sx/Sy side connected to
the line card slave devices. For more details see

Application

Note AN255.

Philips Semiconductors

Product data

P82B96

Dual bi-directional bus buffer

2004 Mar 26

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

TOPSIDE MARK

DRAWING NUMBER

8-pin plastic dual In-line package

ґ40

╟

C to +85

╟

P82B96PN

SOT97-1

8-pin plastic small outline package

ґ40

╟

C to +85

╟

P82B96TD

P82B96T

SOT96-1

8-pin plastic thin shrink small outline package

ґ40

╟

C to +85

╟

P82B96DP

82B96

SOT505-1

NOTE:
1. Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.

BLOCK DIAGRAM

P82B96

Sx (SDA)

Sy (SCL)

Ry (RxD, SCL)

Ty (TxD, SCL)

Rx (RxD, SDA)

Tx (TxD, SDA)

GND

(2ґ15 V)

SU01012

FUNCTIONAL DESCRIPTION

The P82B96 has two identical buffers allowing buffering of both of
the I

C (SDA and SCL) signals. Each buffer is made up of two logic

signal paths, a forward path from the I

C interface pin which drives

the buffered bus, and a reverse signal path from the buffered bus
input to drive the I

C-bus interface.

Thus these paths are:
1. Sense the voltage state of the I

C pin Sx (or Sy) and transmit

this state to the pin Tx (Ty resp.), and

2. Sense the state of the pin Rx (Ry) and pull the I

C pin LOW

whenever Rx (Ry) is LOW.

The rest of this discussion will address only the "x" side of the buffer:

the "y" side is identical.

The I

C pin (Sx) is designed to interface with a normal I

C-bus.

The logic threshold voltage levels on the I

C-bus are independent of

the IC supply V

The maximum I

C-bus supply voltage is 15 V and

the guaranteed static sink current is 3 mA.

The logic level of Rx is determined from the power supply voltage
V

of the chip. Logic LOW is below 42 % of V

and logic HIGH is

above 58 % of V

: with a typical switching threshold of half V

CC.

Tx is an open collector output without ESD protection diodes to V

It may be connected via a pull-up resistor to a supply voltage in
excess of V

CC,

as long as the 15 V rating is not exceeded. It has a

larger current sinking capability than a normal I

C device, being able

to sink a static current of greater than 30 mA, and typical 100 mA
dynamic pull-down capability as well.

A logic LOW is only transmitted to Tx when the voltage at the I

pin (Sx) is below 0.6 V. A logic LOW at Rx will cause the I

C-bus

(Sx) to be pulled to a logic LOW level in accordance with I

requirements (max. 1.5 V in 5 V applications) but not low enough to
be looped back to the Tx output and cause the buffer to latch LOW.

The minimum LOW level this chip can achieve on the I

C-bus by a

LOW at Rx is typically 0.8 V.

If the supply voltage V

fails, then neither the I

C nor the Tx output

will be held LOW. Their open collector configuration allows them to
be pulled up to the rated maximum of 15 V even without V

present. The input configuration on Sx and Rx also present no
loading of external signals even when V

is not present.

The effective input capacitance of any signal pin, measured by its
effect on bus rise times, is less than 7 pF for all bus voltages and
supply voltages including V

= 0 V.

Philips Semiconductors

Product data

P82B96

Dual bi-directional bus buffer

2004 Mar 26

MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages with respect to pin GND (pin 4).

ааааа

SYMBOL

аааааааааааааааааааа

PARAMETER

аааа

MIN.

ааааа

MAX.

аааа

UNIT

ааааа

to GND

аааааааааааааааааааа

Supply voltage range V

аааа

ґ0.3

ааааа

+18

аааа

ааааа

bus

аааааааааааааааааааа

Voltage range on I

C Bus, SDA or SCL

аааа

ґ0.3

ааааа

+18

аааа

ааааа

аааааааааааааааааааа

Voltage range on buffered output

аааа

ґ0.3

ааааа

+18

аааа

ааааа

аааааааааааааааааааа

Voltage range on receive input

аааа

ґ0.3

ааааа

+18

аааа

ааааа

аааааааааааааааааааа

DC current (any pin)

аааа

ааааа

250

аааа

ааааа

tot

аааааааааааааааааааа

Power dissipation

аааа

ааааа

300

аааа

ааааа

stg

аааааааааааааааааааа

Storage temperature range

аааа

ґ55

ааааа

+125

аааа

╟

ааааа

amb

аааааааааааааааааааа

Operating ambient temperature range

аааа

ґ40

ааааа

+85

аааа

╟

CHARACTERISTICS

At T

amb

= 25

╟

C; Voltages are specified with respect to GND with V

= 5 V unless otherwise stated.

ааааа

SYMBOL

ааааааааааа

PARAMETER

аааааааааа

CONDITIONS

аааа

MIN.

ааа

TYP.

ааа

MAX.

аааа

UNIT

аааааааааааааааааааааааааааааааааа

Power Supply

ааааа

ааааааааааа

Supply voltage (operating)

аааааааааа

аааа

2.0

ааа

аааа

ааааа

ааааааааааа

Supply current, buses HIGH

аааааааааа

аааа

ааа

0.9

ааа

1.8

аааа

ааааа

ааааааааааа

Supply current at V

= 15 V, buses HIGH

аааааааааа

аааа

ааа

1.1

ааа

2.5

аааа

ааааа

ааааааааааа

Additional supply current per Tx or Ty LOW

аааааааааа

аааа

ааа

1.7

ааа

3.5

аааа

аааааааааааааааааааааааааааааааааа

Bus pull-up (load) voltages and currents

ааааа

ааа

ааааа

, V

ааааааааааа

ааааааааа

ааааааааааа

Maximum input/output voltage level

аааааааааа

аааааааа

аааааааааа

Open collector;
I

C-bus and V

, V

= HIGH

аааа

аа

аааа

ааа

аааа

аа

аааа

ааааа

, I

ааааааааааа

Static output loading on I

C-bus (Note 1)

аааааааааа

, V

= 1.0 V;

, V

= LOW

аааа

0.2

ааа

аааа

ааааа

ааа

ааааа

, I

ааааааааааа

ааааааааа

ааааааааааа

Dynamic output sink capability on I

C-bus

аааааааааа

аааааааа

аааааааааа

, V

> 2 V;

, V

= LOW

аааа

аа

аааа

ааа

аааа

аа

аааа

ааааа

, I

ааааааааааа

Leakage current on I

C-bus

аааааааааа

, V

= 5 V;

, V

= HIGH

аааа

ааа

аааа

╣

ааааа

ааа

ааааа

, I

ааааааааааа

ааааааааа

ааааааааааа

Leakage current on I

C-bus

аааааааааа

аааааааа

аааааааааа

, V

= 15 V;

, V

= HIGH

аааа

аа

аааа

ааа

аааа

аа

аааа

╣

ааааа

, V

ааааааааааа

Maximum output voltage level

аааааааааа

Open collector

аааа

ааа

аааа

ааааа

, I

ааааааааааа

Static output loading on buffered bus

аааааааааа

, V

= 0.4 V;

, V

= LOW on I

C-bus = 0.4 V

аааа

ааа

аааа

ааааа

ааа

ааааа

, I

ааааааааааа

ааааааааа

ааааааааааа

Dynamic output sink capability, buffered bus

аааааааааа

аааааааа

аааааааааа

, V

> 1 V

, V

= LOW on I

C-bus = 0.4 V

аааа

аа

аааа

ааа

100

ааа

аааа

аа

аааа

ааааа

, I

ааааааааааа

Leakage current on buffered bus

аааааааааа

, V

= V

= 15 V;

, V

= HIGH

аааа

ааа

аааа

╣

аааааааааааааааааааааааааааааааааа

Input Currents

ааааа

ааа

ааааа

, I

ааааааааааа

ааааааааа

ааааааааааа

Input current from I

C-bus

аааааааааа

аааааааа

аааааааааа

bus LOW
V

, V

= HIGH

аааа

аа

аааа

ааа

ґ1

ааа

аааа

аа

аааа

╣

ааааа

, I

ааааааааааа

Input current from buffered bus

аааааааааа

bus LOW
V

, V

= 0.4 V

аааа

ааа

ґ1

ааа

аааа

╣

ааааа

, I

ааааааааааа

Leakage current on buffered bus input

аааааааааа

, V

= V

аааа

ааа

аааа

╣

аааааааааааааааааааааааааааааааааа

Output Logic LOW Levels

ааааа

, V

ааааааааааа

Output logic level LOW, on normal I

C bus

(Note 2)

аааааааааа

, I

= 3 mA

аааа

0.8

ааа

0.88

ааа

1.0

аааа

ааааа

ааа

ааааа

, V

ааааааааааа

ааааааааа

ааааааааааа

Output logic level LOW, on normal I

C bus

(Note 2)

аааааааааа

аааааааа

аааааааааа

, I

= 0.2 mA

аааа

аа

аааа

670

ааа

730

ааа

790

аааа

аа

аааа

ааааа

/dT,

/dT

ааааааааааа

Temperature coefficient of output LOW
levels (Note 2)

аааааааааа

, I

= 0.2 mA

аааа

ааа

ґ1.8

ааа

аааа

mV/K

Philips Semiconductors

Product data

P82B96

Dual bi-directional bus buffer

2004 Mar 26

аааа

UNIT

ааа

MAX.

ааа

TYP.

аааа

MIN.

аааааааааа

CONDITIONS

ааааааааааа

PARAMETER

ааааа

SYMBOL

аааааааааааааааааааааааааааааааааа

Input logic switching threshold voltages

ааааа

, V

ааааааааааа

Input logic voltage LOW (Note 3)

аааааааааа

On normal I

C-bus

аааа

ааа

640

ааа

600

аааа

ааааа

, V

ааааааааааа

Input logic level HIGH threshold (Note 3)

аааааааааа

On normal I

C-bus

аааа

700

ааа

650

ааа

аааа

ааааа

ааа

ааааа

/dT,

/dT

ааааааааааа

ааааааааа

ааааааааааа

Temperature coefficient of input thresholds

аааааааааа

аааааааа

аааааааааа

аааа

аа

аааа

ааа

ґ2

ааа

аааа

аа

аааа

mV/K

ааааа

, V

ааааааааааа

Input logic HIGH level

аааааааааа

Fraction of applied V

аааа

0.58

ааа

аааа

ааааа

, V

ааааааааааа

Input threshold

аааааааааа

Fraction of applied V

аааа

ааа

0.5

ааа

аааа

ааааа

, V

ааааааааааа

Input logic LOW level

аааааааааа

Fraction of applied V

аааа

ааа

0.42

аааа

аааааааааааааааааааааааааааааааааа

Logic level threshold difference

ааааа

ааа

ааааа

, V

ааааааааааа

ааааааааа

ааааааааааа

Input/Output logic level difference (Note 1)

аааааааааа

аааааааа

аааааааааа

output LOW at 0.2 mA ґ

input HIGH max

аааа

аа

аааа

ааа

аааа

аа

аааа

NOTES:
1. The minimum value requirement for pull-up current, 200

╣

A, guarantees that the minimum value for V

output LOW will always exceed the

minimum V

input HIGH level to eliminate any possibility of latching. The specified difference is guaranteed by design within any IC. While

the tolerances on absolute levels allow a small probability the LOW from one S

output is recognized by an S

input of another P82B96 this

has no consequences for normal applications. In any design the S

pins of different ICs should never be linked because the resulting system

would be very susceptible to induced noise and would not support all I

C operating modes.

2. The output logic LOW depends on the sink current. For scaling, see

Application Note AN255.

3. The input logic threshold is independent of the supply voltage.

CHARACTERISTICS

At T

amb

= 25

╟

C; Voltages are specified with respect to GND with V

= 5 V unless otherwise stated.

ааааа

SYMBOL

аааааааааааа

PARAMETER

аааааааа

CONDITIONS

аааа

MIN.

аааа

TYP.

ааа

MAX.

аааа

UNIT

аааааааааааааааааааааааааааааааааа

Bus Release on V

Failure

ааааа

ааа

ааааа

, V

аааааааааааа

аааааааааа

аааааааааааа

voltage at which all buses are

guaranteed to be released

аааааааа

аааааа

аааааааа

аааа

аа

аааа

аа

аааа

ааа

аааа

аа

аааа

ааааа

dV/dT

аааааааааааа

Temperature coefficient of guaranteed release
voltage

аааааааа

аааа

ґ4

ааа

аааа

mV/K

аааааааааааааааааааааааааааааааааа

Buffer response time

ааааа

ааа

ааааа

fall delay

to V

аааааааааааа

аааааааааа

аааааааааааа

Buffer time delay on FALLING input between
V

= input switching threshold,

and V

output falling 50%.

аааааааа

аааааа

аааааааа

pull-up = 160

no capacitive load, V

= 5 V

аааа

аа

аааа

аа

аааа

ааа

аааа

аа

аааа

ааааа

ааа

ааааа

rise delay

to V

аааааааааааа

аааааааааа

аааааааааааа

Buffer time delay on RISING input between
V

= input switching threshold,

and V

output reaching 50% V

аааааааа

аааааа

аааааааа

pull-up = 160

no capacitive load, V

= 5 V

аааа

аа

аааа

аа

аааа

ааа

аааа

аа

аааа

ааааа

ааа

ааааа

fall delay

to V

аааааааааааа

аааааааааа

аааааааааааа

Buffer time delay on FALLING input between
V

= input switching threshold,

and V

output falling 50%.

аааааааа

аааааа

аааааааа

pull-up = 1500

, no

capacitive load, V

= 5 V

аааа

аа

аааа

аа

аааа

250

ааа

аааа

аа

аааа

ааааа

ааа

ааааа

rise delay

to V

аааааааааааа

аааааааааа

аааааааааааа

Buffer time delay on RISING input between
V

= input switching threshold,

and V

output reaching 50% V

аааааааа

аааааа

аааааааа

pull-up = 1500

no capacitive load, V

= 5 V

аааа

аа

аааа

аа

аааа

270

ааа

аааа

аа

аааа

аааааааааааааааааааааааааааааааааа

Input capacitance

ааааа

аааааааааааа

Effective input capacitance of any signal pin
measured by incremental bus rise times

аааааааа

аааа

ааа

аааа

NOTES ON RESPONSE TIME

The fall-time of V

from 5 V to 2.5 V in the test is approximately 15 ns.

The fall-time of V

from 5 V to 2.5 V in the test is approximately 50 ns.

The rise-time of V

from 0 V to 2.5 V in the test is approximately 20 ns.

The rise-time of V

from 0.9 V to 2.5 V in the test is approximately 70 ns.

Philips Semiconductors

Product data

P82B96

Dual bi-directional bus buffer

2004 Mar 26

SCL

SDA

P82B96

3 ґ 20 m CABLES

su01785

P82B96

CC1

+V CABLE DRIVE

C/DDC

MASTER

GND

BC
847B

470 k

4K7

C/DDC

CC1

CC2

GND

C/DDC

SLAVE

PC/TV RECEIVER/DECODER BOX

MONITOR/FLAT TV

VIDEO SIGNALS

100 k

BC
847B

100 nF

470 k

+V CABLE DRIVE

Figure 4. Extending a DCC bus

Figure 4 shows how a master I

C-bus can be protected against

short circuits or failures in applications that involve plug/socket
connections and long cables that may become damaged. A simple
circuit is added to monitor the SDA bus and if its LOW time exceeds
the design value then the master bus is disconnected. P82B96 will
free all its I/Os if its supply is removed, so one option is to connect
its V

to the output of a logic gate from, say, the 74LVC family. The

SDA and SCL lines could be timed and V

disabled via the gate if

one or other lines exceeds a design value of `LOW' period as in
Figure 28 of AN255. If the supply voltage of logic gates restricts the
choice of V

supply then the low-cost discrete circuit in Figure 4

can be used. If the SDA line is held LOW, the 100 nF capacitor will
charge and the R

input will be pulled towards V

. When it

exceeds V

/2 the R

input will set the S

input HIGH, which in

practice means simply releasing it.

In this example the SCL line is made uni-directional by tying the R

pin to V

. The state of the buffered SCL line cannot affect the

master clock line which is allowed when clock-stretching is not
required. It is simple to add an additional transistor or diode to
control the R

input in the same way as R

when necessary. The +V

cable drive can be any voltage up to 15 V and the bus may be run at

a lower impedance by selecting pull-up resistors for a static sink
current up to 30 mA. V

CC1

and V

CC2

may be chosen to suit the

connected devices. Because DDC uses relatively low speeds
(<100 kHz), the cable length is not restricted to 20 m by the I

signalling, but it may be limited by the video signalling.

Figure 5 shows that P82B96 can achieve high clock rates over long
cables. While calculating with lumped wiring capacitance yields

reasonable approximations to actual timing, even 25 meters of cable

is better treated using transmission line theory. Flat ribbon cables
connected as shown, with the bus signals on the outer edge, will
have a characteristic impedance in the range 100 ґ 200

. For

simplicity they cannot be terminated in their characteristic
impedance but a practical compromise is to use the minimum
pull-up allowed for P82B96 and place half this termination at each
end of the cable. When each pull-up is below 330

, the rising edge

waveforms have their first voltage `step' level above the logic
threshold at Rx and cable timing calculations can be based on the
fast rise/fall times of resistive loading plus simple one-way
propagation delays. When the pull-up is larger, but below 750

, the

threshold at Rx will be crossed after one signal reflection. So at the
sending end it is crossed after 2 times the one-way propagation
delay and at the receiving end after 3 times that propagation delay.
For flat cables with partial plastic dielectric insulation (by using outer
cores) the one-way propagation delays will be about 5 ns/meter.
The 10% to 90% rise and fall times on the cable will be between
20 ns and 50 ns, so their delay contributions are small. There will be
ringing on falling edges that can be damped, if required, using
Schottky diodes as shown.

When the Master SCL HIGH and LOW periods can be programmed
separately, e.g. using control registers I2SCLH and I2SCLL of
89LPC932, the timings can allow for bus delays. The LOW period
should be programmed to achieve the minimum 1300 ns plus the
net delay in the slave's response data signal caused by bus and
buffer delays. The longest data delay is the sum of the delay of the
falling edge of SCL from master to slave and the delay of the rising
edge of SDA from slave data to master. Because the buffer will
`stretch' the programmed SCL LOW period, the actual SCL

Philips Semiconductors

Product data

P82B96

Dual bi-directional bus buffer

2004 Mar 26

frequency will be lower than calculated from the programmed clock
periods. In the example for 25 meters the clock is stretched 400 ns,

the falling edge of SCL is delayed 490 ns and the SDA rising edge is

delayed 570 ns. The required additional LOW period is
(490 + 570) = 1060 ns and the I

C-bus specifications already

include an allowance for a worst case bus risetime 0 to 70% of
425 ns. (The bus risetime can be 300 ns 30% to 70%, which means
it can be 425 ns 0ґ70%. The 25-meter cable delay times as quoted

already include all rise/fall times.) Therefore, the micro only needs to

be programmed with an addtional (1060 ґ 400 ґ 425) = 235 ns,
making a total programmed LOW period 1535 ns. The programmed
LOW will the be stretched by 400 ns to yield an actual bus LOW
time of 1935 ns, which, allowing the minimum HIGH period of
600 ns, yields a cycle period of 2535 ns or 394 kHz.

Note that in both the 100-meter and 250-meter examples the
capacitive loading on the I

C-buses at each end is within the

maximum allowed Standard mode loading of 400 pF, but exceeds

the Fast mode limit. This is an example of a `hybrid' mode because it

relies on the response delays of Fast mode parts but uses
(allowable) Standard mode bus loadings with rise times that
contribute significantly to the system delays. The cables cause large

propagation delays so these systems need to operate well below the

400 kHz limit but illustrate how they can still exceed the 100 kHz
limit provided all parts are capable of Fast mode operation. The
fastest example illustrates how the 400 kHz limit can be exceeded
provided master and slave parts have delay specifications smaller

than the maximum allowed. Many Philips slaves have delays shorter

than 600 ns, but none have that guaranteed.

SCL

SDA

su01786

P82B96

MASTER

GND

CC1

CC2

SCL

SDA

P82B96

SLAVE(S)

GND

BAT54A

CABLE

PROPAGATION

DELAY

5 ns/m

+V CABLE DRIVE

Figure 5. Driving ribbon or flat telephone cables

EXAMPLES OF BUS CAPABILITY (refer to Figure 5)

CABLE

SET MASTER

NOMINAL SCL

EFFECTIVE

BUS

MAXIMUM

SLAVE

CC1

CABLE

CC2

(pF)

LENGTH

CAPACITANCE

DELAY

HIGH

PERIOD

LOW

PERIOD

CLOCK

SPEED

RESPONSE

DELAY

5 V

12 V

5 V

750

2.2 k

400

250 m

Not applicable

(delay based)

1.25

╣

600 ns

4000 ns

120 kHz

Normal spec.

400 kHz

parts

5 V

12 V

5 V

750

2.2 k

220

100 m

Not applicable

(delay based)

500 ns

600 ns

2600 ns

185 kHz

Normal spec.

400 kHz

parts

3.3 V

5 V

3.3 V

330

1 k

220

25 m

1 nF

125 ns

600 ns

1500 ns

390 kHz

Normal spec.

400 kHz

parts

3.3 V

5 V

3.3 V

330

1 k

100

3 m

120 pF

15 ns

600 ns

1000 ns

500 kHz

600 ns

Philips Semiconductors

Product data

P82B96

Dual bi-directional bus buffer

2004 Mar 26

Cm = MASTER BUS
CAPACITANCE

Cb = BUFFERED BUS
WIRING CAPACITANCE

Cs = SLAVE BUS
CAPACITANCE

MASTER

SLAVE

P82B96

CCM

SDA

CCS

SDA

Tx/Rx

GND/0 V

RISING EDGE OF SDA AT SLAVE IS DELAYED BY THE BUFFERS AND BUS RISE TIMES

EFFECTIVE DELAY OF SDA AT MASTER = 270 + 0.2RsCs + 0.7 (RbCb + RmCm) (ns),

C = F,

R =

LOCAL MASTER BUS

BUFFERED EXPANSION BUS

REMOTE SLAVE BUS

su01789

CCB

Figure 8.

Figures 6, 7, and 8 show the P82B96 used to drive extended bus
wiring, with relatively large capacitance, linking two Fast mode
I

C-bus nodes. It includes simplified expressions for making the

relevant timing calculations for 3.3/5 V operation. Because the
buffers and the wiring introduce timing delays, it may be necessary
to decrease the nominal SCL frequency below 400 kHz. In most
cases the actual bus frequency will be lower than the nominal
Master timing due to bit-wise stretching of the clock periods.

The delay factors involved in calculation of the allowed bus speed
are:

A) The propagation delay of the Master signal through the buffers

and wiring to the Slave. The important delay is that of the falling
edge of SCL because this edge `requests' the data or
Acknowledge from a Slave.

B) The effective stretching of the nominal LOW period of SCL at the

Master caused by the buffer and bus rise times

C) The propagation delay of the Slave's response signal through the

buffers and wiring back to the Master. The important delay is
that of a rising edge in the SDA signal. Rising edges are always
slower and are therefore delayed by a longer time than falling
edges. (The rising edges are limited by the passive pull-up while
falling edges are actively driven)

The timing requirement in any I

C system is that a Slave's data

response (which is provided in response to a falling edge of SCL)
must be received at the Master before the end of the corresponding
low period of SCL as appears on the bus wiring at the Master. Since
all Slaves will, as a minimum, satisfy the worst case timing
requirements of a 400 kHz part, they must provide their response

within the minimum allowed clock LOW period of 1300 ns. Therefore

in systems that introduce additional delays it is only necessary to

extend that minimum clock low period by any "effective" delay of the
Slave's response. The effective delay of the slaves response = total
delays in SCL falling edge from the Master reaching the Slave (A) ґ
the effective delay (stretch) of the SCL rising edge (B) + total delays
in the Slave's response data, carried on SDA, reaching the
Master (C).

The Master microcontroller should be programmed to produce a
nominal SCL LOW period = (1300 + A ґ B + C) ns, and should be
programmed to produce the nominal minimum SCL HIGH period of
600 ns. Then a check should be made to ensure the cycle time is
not shorter than the minimum 2500 ns. If found necessary, just
increase either clock period.

Due to clock stretching, the SCL cycle time will always be longer
than (600 + 1300 + A + C) ns.

Example:

The Master bus has an RmCm product of 100 ns and V

CCM

= 5 V.

The buffered bus has a capacitance of 1 nF and a pull-up resistor of
160 ohms to 5 V giving an RbCb product of 160 ns. The Slave bus
also has an RsCs product of 100 ns.

The microcontroller LOW period should be programmed to

(1300 + 372.5 ґ 482 + 472) ns, that is

1662.5 ns.

Its HIGH period may be programmed to the minimum 600 ns.

The nominal microcontroller clock period will be

(1662.5 + 600) ns = 2262.5 ns, equivalent to a frequency of

442 kHz.

The actual bus clock period, including the 482 ns clock stretch
effect, will be below (nominal + stretch) = (2262.5 + 482) ns or

2745 ns, equivalent to an allowable frequency of 364 kHz.

Philips Semiconductors

Product data

P82B96

Dual bi-directional bus buffer

2004 Mar 26

REVISION HISTORY

Rev

Date

Description

20040326

Product data (9397 750 12932). Supersedes data of 2003 Apr 02 (9397 750 11351).

Modifications:

Page 2:
ґ Features section re-written.

ґ Add "TSSOP" to heading for pin configurations

Page 3, Ordering information table: correct description of TSSOP8 package.

Page 5, (continued) Characteristics table, Note 1,
ґ third sentence:

from "... the LOW from on S

output ..."

to "... the LOW from one S

output ..."

ґ fourth sentence:

from "In any design the S

pins of different ICs because the resulting ..."

to "In any design the S

pins of different ICs should never be linked because the resulting ..."

Figure 4: Change 2 transistors to bipolar type. Add dashed line between V

CC1

and V

, and between V

CC2

and V

to indicate optional/allowed links.

Figure 5: Add dashed line between V

CC1

and V

, and between V

CC2

and V

to indicate optional/allowed

links.

Page 8, table "Examples of bus capability":
ґ cable capacitance 1 nF:

change LOW period from "1600 ns" to "1500 ns"
change Effective bus clock speed from "380 kHz" to "390 kHz"

ґ change cable capacitance "120 nF" to "120 pF"

Add title "Calculating system delays and bus clock frequency for a Fast mode system" on page 9.

Add V

CCB

label to Figures 6, 7 and 8.

Page 10, "Example:" paragraphs 3, 5 and 6: values corrected in equations.

Add signal names to Figure 9.

Add package outline drawing SOT505-1.

20030402

Product data (9397 750 11351); ECN 853-2241 29602 dated 28 February 2003.
Supersedes data of 2003 Jan 22 (9397 750 11093)

20030226

Product data (9397 750 11093); ECN 853-2241 29410 of 22 January 2003;
supersedes data of 2001 Mar 06 (9397 750 08122)

20010306

Product data (9397 750 08122); ECN 853-2241 25758 of 2001 Mar 06.

Philips Semiconductors

Product data

P82B96

Dual bi-directional bus buffer

2004 Mar 26

Purchase of Philips I

C components conveys a license under the Philips' I

C patent

to use the components in the I

C system provided the system conforms to the

C specifications defined by Philips. This specification can be ordered using the

code 9398 393 40011.

Definitions

Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described
or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.

Contact information

For additional information please visit
http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.

╘

Koninklijke Philips Electronics N.V. 2004

Date of release: 03-04

Document order number:

9397 750 12932

Philips
Semiconductors

Data sheet status

[1]

Objective data

Preliminary data

Product data

Product
status

[2] [3]

Development

Qualification

Production

Definitions

This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.

This data sheet contains data from the preliminary specification. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notification (CPCN).

Data sheet status

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Level

III

Part Number P82B96