DATA SHEET
Product specification
Supersedes data of 1998 Jul 29
File under Integrated Circuits, IC24
1999 Jun 15
INTEGRATED CIRCUITS
74LVC4245A
Octal dual supply translating
transceiver; 3-state
1999 Jun 15
2
Philips Semiconductors
Product specification
Octal dual supply translating transceiver; 3-state
74LVC4245A
FEATURES
·
In accordance with JEDEC
standard no. 8-1A
·
Wide supply voltage range:
3 V port: 1.5 to 3.6 V
5 V port: 1.5 to 5.5 V
·
CMOS low power consumption
·
Direct interface with TTL levels
·
Control inputs accept voltages up
to 5.5 V.
DESCRIPTION
The 74LVC4245A is a high-performance, low-power, low-voltage, Si-gate
CMOS device, superior to most advanced CMOS compatible TTL families.
The 74LVC4245A is an octal dual supply translating transceiver featuring
non-inverting 3-state bus compatible outputs in both send and receive
directions. It is designed to interface between a 3 and 5 V bus in a mixed 3/5 V
supply environment.
The 74LVC4245A features an output enable (OE) input for easy cascading and
a send/receive (DIR) input for direction control. (OE) controls the outputs so
that the buses are effectively isolated.
In suspend mode, when V
CCA
is zero, there will be no current flow from one
supply to the other supply. The A-outputs must be set 3-state and the voltage
on the A-bus must be smaller than V
diode
(typ. 0.7 V). V
CCA
V
CCB
(except in
suspend mode).
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
2.5 ns.
Note
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µ
W).
P
D
= C
PD
×
V
CC
2
×
f
i
+
(C
L
×
V
CC
2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
(C
L
×
V
CC
2
×
f
o
) = sum of the outputs.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
propagation delay
C
L
= 50 pF
A
n
to B
n
V
CCA
= 5.0 V
4.0
ns
B
n
to A
n
V
CCB
= 3.3 V
4.0
ns
C
I/O
input/output capacitance
10.0
pF
C
PDA
A port
A
n
to B
n
V
I
= GND to V
CC
; note 1
7.8
pF
B
n
to A
n
V
I
= GND to V
CC
; note 1
27.9
pF
C
PDB
B port
A
n
to B
n
V
I
= GND to V
CC
; note 1
26
pF
B
n
to A
n
V
I
= GND to V
CC
; note 1
10.4
pF
1999 Jun 15
3
Philips Semiconductors
Product specification
Octal dual supply translating transceiver; 3-state
74LVC4245A
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don't care;
Z = high-impedance OFF-state.
ORDERING INFORMATION
PINNING
INPUT
INPUT/OUTPUT
OE
DIR
A
n
B
n
L
L
A = B
inputs
L
H
inputs
B = A
H
X
Z
Z
OUTSIDE NORTH
AMERICA
NORTH AMERICA
PACKAGE
TEMPERATURE
RANGE
PINS
PACKAGE
MATERIAL
CODE
74LVC4245AD
74LVC4245AD
-
40 to +85
°
C
24
SO
plastic
SOT137-1
74LVC4245ADB
74LVC4245ADB
24
SSOP
plastic
SOT340-1
74LVC4245APW
74LVC4245ADH
24
TSSOP
plastic
SOT355-1
PIN
SYMBOL
DESCRIPTION
1
V
CCA
DC supply voltage (5 V bus)
2
DIR
direction control
3, 4, 5, 6, 7, 8, 9 and 10
A
0
to A
7
data inputs/outputs
11, 12 and 13
GND
ground (0 V)
14, 15, 16, 17, 18, 19, 20 and 21
B
7
to B
0
data inputs/outputs
22
OE
output enable input (active LOW)
23 and 24
V
CCB
DC supply voltage (3 V bus)
1999 Jun 15
4
Philips Semiconductors
Product specification
Octal dual supply translating transceiver; 3-state
74LVC4245A
Fig.1 Pin configuration.
handbook, halfpage
VCCA
GND
VCCB
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
4245
MNA451
DIR
A0
A1
A2
A3
A4
A5
A6
A7
GND
VCCB
OE
B0
B1
B3
B4
B2
B5
B6
B7
Fig.2 Logic symbol.
handbook, halfpage
3
2
DIR
21
22
B0
B1
B2
B3
B4
B5
B6
B7
4
20
5
19
6
18
7
17
8
16
9
15
10
A0
A1
A2
A3
A4
A5
A6
A7
14
OE
MNA453
Fig.3 IEC logic symbol.
handbook, halfpage
20
3
2
22
2
1
19
4
18
5
17
6
16
7
15
8
14
9
21
G3
3EN1
3EN2
10
MNA452
1999 Jun 15
5
Philips Semiconductors
Product specification
Octal dual supply translating transceiver; 3-state
74LVC4245A
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V).
Note
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
SYMBOL
PARAMETER
CONDITIONS
LIMITS
UNIT
MIN.
MAX.
V
CCA
DC supply voltage 5 V port
(for maximum speed performance)
V
CCA
V
CCB
(see Fig.5)
1.5
5.5
V
V
CCB
DC supply voltage 3 V port
(for low-voltage applications)
V
CCA
V
CCB
(see Fig.5)
1.5
3.6
V
V
I
DC input voltage range (control inputs)
0
5.5
V
V
I/O
DC input voltage range; output 3-state
0
5.5
V
DC output voltage range; output HIGH or
LOW state
0
V
CC
V
T
amb
operating ambient temperature range
see DC and AC characteristics
per device
-
40
+85
°
C
t
r
,t
f
input rise and fall times
V
CCB
= 2.7 to 3.0 V
0
20
ns/V
V
CCB
= 3.0 to 3.6 V
0
10
V
CCA
= 3.0 to 4.5 V
0
20
V
CCA
= 4.5 to 5.5 V
0
10
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
CCA
DC supply voltage 5 V port
-
0.5
+6.5
V
V
CCB
DC supply voltage 3 V port
-
0.5
+4.6
V
I
IK
DC input diode current
V
I
< 0
-
-
50
mA
V
I
DC input voltage
note 1
-
0.5
+6.5
V
I
OK
DC output diode current
V
O
> V
CC
or V
O
< 0
-
±
50
mA
V
I/O
DC output voltage; output HIGH or LOW note 1
-
0.5
V
CC
+ 0.5
V
DC input voltage; output 3-state
note 1
-
0.5
+6.5
V
I
O
DC output diode current
V
O
= 0 to V
CC
-
±
50
mA
I
GND
, I
CC
DC V
CC
or GND current
-
±
100
mA
T
stg
storage temperature
-
65
+150
°
C
P
tot
power dissipation per package
plastic mini-pack (SO)
above 70
°
C derate linearly
with 8 mW/K
-
500
mW
plastic shrink mini-pack (SSOP and
TSSOP)
above 60
°
C derate linearly
with 5.5 mW/K
-
500
mW
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