1
PS8164A 09/29/00
PI6C102
Precision Clock Synthesizer
for Mobile PCs
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PCICLK_F
VSSPCI0
PCICLK1
PCICLK3
VDDPCI0
PCICLK2
VDDPCI1
PCICLK4
PCICLK5
VSSPCI1
VSSCORE0
VSSREF
REF
VDDCPU
CPUCLK1
VSSCPU
VDDCORE1
VSSCORE1
PCISTOP#
CPUSTOP#
PWRDWN#
SEL
SEL100/66#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
XTAL_IN
XTAL_OUT
CPUCLK0
VDDREF
VDDCORE0
Pin Configuration
Block Diagram
Features
Two copies of CPU clock with V
DD
of 2.5V ±5%
100 MHz or 66.6 MHz operation
Six copies of PCI clock, (synchronous with CPU clock) 3.3V
One copy of Ref. Clock @ 14.31818 MHz (3.3V
TTL
)
Low cost 14.31818 MHz crystal oscillator input
Power management control
Isolated core V
DD
, V
SS
pins for noise reduction
28-pin SSOP package (H)
Description
The PI6C102 is a high-speed low-noise clock generator designed
to work with the Pericom's PI6C18x clock buffer to meet all clock
needs for Mobile Intel Architecture platforms. CPU and chipset
clock frequencies of 66.6 MHz and 100 MHz are supported.
Split supplies of 3.3V and 2.5V are used. The 3.3V power supply
powers a portion of the I/O and the core. The 2.5V is used to power
the remaining outputs. 2.5V signaling follows JEDEC standard 8-X.
Power sequencing of the 3.3V and 2.5V supplies is not required.
An asynchronous PWRDWN# signal may be used to orderly power
down (or up) the system.
28-Pin
H
REF
PCICLK
[1:5]
CPUCLK
[0:1]
REF
OSC
CPUSTOP#
*KBBAHI
2
5
PCICLK_F
PCISTOP#
DIV
XTAL_OUT
XTAL_IN
V
DDREF
V
DDCPU
V
DDCPU
0,1
SEL100/66#
SEL
PWRDWN#
PLL1
2
PS8164A 09/29/00
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PI6C102
Precision Clock Synthesizer for Mobile PCs
Pin Description
Select Functions
Clock Enable Configuration
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Notes:
TCLK is a test clock over driven on he XTAL_IN inpu during test mode.
3
PS8164A 09/29/00
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PI6C102
Precision Clock Synthesizer for Mobile PCs
Power Management Timing
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Notes:
1. Clock on/off latency is defined as the number of rising edges of free running PCICLKs
between when the clock disable goes low/high to when the first valid clock comes out of
the device.
2. Power-up latency is from when PWR_DWN# goes inactive (HIGH) to when the first valid
clocks are driven from the device.
CPU_STOP# is an input signal used to turn off the CPU clocks for
low power operation. CPU_STOP# is asserted asynchronously by
the external clock control logic with the rising edge of free running
PCI clock and is internally synchronized to the external PCICLK_F
output. All other clocks continue to run while the CPU clocks are
CPU_STOP# Timing Diagram
Notes:
1. All timing is referenced to the CPUCLK.
2. The Internal label means inside the chip and is a reference only.
3 CPU_STOP# is an input signal that must be made synchronous to the free running PCI_F.
4. ON/OFF latency shown in the diagram is 2 CPU clocks.
5. All other clocks continue to run undisturbed.
6. PWR_DWN# and PCI_STOP# are shown in a HIGH state.
7. Diagrams shown with respect to 66 MHz. Similar operation as CPU = 100 MHz.
disabled. The CPU clocks are always stopped in a LOW state and
started guaranteeing that the high pulse width is a full pulse. CPU
clock on latency is 2 or 3 CPU clocks and CPU clock off latency
is 2 or 3 CPU clocks.
CPUCLK
(Internal)
CPUCLK
(Internal)
PCICLK_F
(Free-running)
CPU_STOP#
PCI_STOP#
PWR_DWN#
CPUCLK
(External)
4
PS8164A 09/29/00
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PI6C102
Precision Clock Synthesizer for Mobile PCs
Notes:
1. All timing is referenced to the CPUCLK.
2. PCI_STOP# signal is an input signal which must be made synchronous to PCI_F output.
3 Internal means inside the chip.
4. All other clocks continue to run undisturbed.
5. PWR_DWN# and CPU_STOP# are shown in a high state.
6. Diagrams shown with respect to 66 MHz. Similar operation as CPU = 100 MHz.
PCI_STOP# is an input signal used to turn off PCI clocks for low
power operation. PCI clocks are stopped in the LOW state and
PCI_STOP# Timing Diagram
PWR_DWN# Timing Diagram
The PWR_DWN# is used to place the device in a very low power
state. PWR_DWN# is an asynchronous active low input. Internal
clocks are stopped after the device is put in power-down mode.
Notes:
1. All timing is referenced to the CPUCLK.
2. The Internal label means inside the chip and is a reference only.
3. PWR_DWN# is an asynchronous input and metastable conditions could exist. The signal is synchronized inside the part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown wth respect to 66 MHz. Similar operation as CPU = 100 MHz.
The power-on latency is less than 3ms. PCI_STOP# and CPU_STOP#
are dont cares during the power-down operations. The REF clock
is stopped in the LOW state as soon as possible.
started with a guaranteed full high pulse width. There is ONLY one
rising edge of external PCICLK after the clock control logic.
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK_F
(Free-running)
CPU_STOP#
PCI_STOP#
PWR_DWN#
PCICLK
(External)
CPUCLK
(Internal)
PCICLK
(Internal)
VCO
PWR_DWN#
CPUCLK
(External)
PCICLK
(External)
Crystal
5
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PI6C102
Precision Clock Synthesizer for Mobile PCs
Storage Temperature ............................................................... 65°C to +150°C
Ambient Temperature with Power Applied ................................ 0°C to +70°C
3.3V Supply Voltage to Ground Potential................................... 0.5V to +4.6V
2.5V Supply Voltage to Ground Potential................................... 0.5V to +3.6V
DC Input Voltage ....................................................................... 0.5V to +4.6V
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics
(V
DDQ3
= +3.3V ± 5%, V
DDQ2
= +2.5V ± 5%, T
A
= 0°C to +70°C)
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
2
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6
PS8164A 09/29/00
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PI6C102
Precision Clock Synthesizer for Mobile PCs
DC Operating Specifications
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PI6C102
Precision Clock Synthesizer for Mobile PCs
Type 1: CPU Clock Buffers (2.5V)
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Buffer Specifications
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PS8164A 09/29/00
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12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI6C102
Precision Clock Synthesizer for Mobile PCs
AC Timing
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PI6C102
Precision Clock Synthesizer for Mobile PCs
Figure 2. Clock Output Waveforms
Figure 1. Host Clock and PCI CLK Timing
Output
Buffer
Test
Point
2.0
1.25
0.4
tHKH
Duty Cycle
tHKP
2.5V
Clocking
Interface
tHKL
tHfall
tHrise
2.4
1.5
0.4
tPKH
tPKP
3.3V
Clocking
Interface
(TTL)
tPKL
tPfall
tPrise
Test Load
1.25V
2.5V
tHPOFFSET
Host CLK
PCI CLK
VSS
1.5V
3.3V
VSS
tHPOFFSET
1.25V
2.5V
Host CLK
VSS
tHSKW
PCI CLK
1.5V
3.3V
VSS
tPSKW
1.5V
1.25V
1.25V
10
PS8164A 09/29/00
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PI6C102
Precision Clock Synthesizer for Mobile PCs
PCB Layout Suggestion
Note:
This is only a suggested layout. There may be alternate solutions
depending on actual PCB design and layout.
As a general rule, C2-C7 should be placed as close as possible to
their respective V
DD
.
Recommended capacitor values:
C2-C7 ............... 0.1
µ
F, ceramic
C1, C8 ............. 22
µ
F
C2
C3
C4
C6
C5
C7
FB2
VCC
C8
22uF
Via to VDD Plane
Via to GND Plane
Void in Power Plane
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
VDD
VDD
VDD
VSS
VSS
VSS
VDD
VSS
VSS
VDD
VDD
FB1
VCC
C1
22uF
11
PS8164A 09/29/00
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PI6C102
Precision Clock Synthesizer for Mobile PCs
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1
Minimum and Maximum Expected Capacitive Loads
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load for each type of output buffer.
2. Minimum rise/fall times are guaranteed at minimum specified load for each type of output buffer.
3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an
additional 500
resistor in parallel.
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value
for CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall time
are still within the specified values.
2. Minimize the number of vias of the clock traces.
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock
traces from plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables or any external connectors.
Pericom Semiconductor Corporation
2380 Bering Drive · San Jose, CA 95131 · 1-800-435-2336 · Fax (408) 435-1100 · http://www.pericom.com
Ordering Information
N
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CPUCLK
PCICLK
REF
32
33
22
/33
2
6
CL
CL
CL
21$+
1 Device load
Meets PCI2.1 Req.
1 Device load
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