©
Semiconductor Components Industries, LLC, 2001
October, 2001 Rev. 8
1
Publication Order Number:
SN74LS373/D
SN74LS373, SN74LS374
Octal Transparent Latch
with 3-State Outputs;
Octal D-Type Flip-Flop
with 3-State Output
The SN74LS373 consists of eight latches with 3-state outputs for
bus organized system applications. The flip-flops appear transparent
to the data (data changes asynchronously) when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup times is
latched. Data appears on the bus when the Output Enable (OE) is
LOW. When OE is HIGH the bus output is in the high impedance state.
The SN74LS374 is a high-speed, low-power Octal D-type Flip-Flop
featuring separate D-type inputs for each flip-flop and 3-state outputs
for bus oriented applications. A buffered Clock (CP) and Output
Enable (OE) is common to all flip-flops. The SN74LS374 is
manufactured using advanced Low Power Schottky technology and is
compatible with all ON Semiconductor TTL families.
·
Eight Latches in a Single Package
·
3-State Outputs for Bus Interfacing
·
Hysteresis on Latch Enable
·
Edge-Triggered D-Type Inputs
·
Buffered Positive Edge-Triggered Clock
·
Hysteresis on Clock Input to Improve Noise Margin
·
Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
4.75
5.0
5.25
V
TA
Operating Ambient
Temperature Range
0
25
70
°
C
IOH
Output Current High
2.6
mA
IOL
Output Current Low
24
mA
LOW
POWER
SCHOTTKY
http://onsemi.com
PDIP20
N SUFFIX
CASE 738
20
1
20
1
x
= 3 or 4
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
SN74LS37xN
AWLYYWW
MARKING
DIAGRAMS
LS37x
AWLYYWW
SOIC20
DW SUFFIX
CASE 751D
1
1
20
1
SOEIAJ20
M SUFFIX
CASE 967
74LS37x
AWLYWW
1
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
SN74LS373, SN74LS374
http://onsemi.com
2
CONNECTION DIAGRAM DIP (TOP VIEW)
Data Inputs
Latch Enable (Active HIGH) Input
Clock (Active HIGH Going Edge) Input
Output Enable (Active LOW) Input
Outputs
D0 - D7
LE
CP
OE
O0 - O7
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
HIGH
LOW
(Note a)
LOADING
PIN NAMES
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In Line Package.
SN74LS373
SN74LS374
18
17
16
15
14
13
1
2
3
4
5
6
7
20
19
8
VCC
OE
O7 D7 D6 O6
D5
O5
D4
O0 D0 D1 O1 O2 D2 D3
9
10
O3 GND
12
O4 LE
18
17
16
15
14
13
1
2
3
4
5
6
7
20
19
8
VCC
OE
O7 D7 D6 O6
D5
O5
D4
O0 D0 D1 O1 O2 D2 D3
9
10
O3 GND
12
11
O4 CP
11
TRUTH TABLE
LS373
Dn
LE
OE
On
H
H
L
H
L
H
L
L
X
L
L
Q0
X
X
H
Z*
LS374
Dn
LE
OE
On
H
L
H
L
L
L
X
X
H
Z*
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
* Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE).
SN74LS373, SN74LS374
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3
LOGIC DIAGRAMS
SN74LS373
SN74LS374
D
D
G
Q
CP
Q Q
CP
OE
OE
LE
LATCH
ENABLE
O0
O1
O2
O3
O4
O5
O6
O7
D0
14
1
2
6
7
3
8
4
5
9
11
12
16
13
15
V
CC
= PIN 20
GND = PIN 10
= PIN NUMBERS
D
G
Q
D1
D
G
Q
D2
D
G
Q
D3
D
G
Q
D4
D
G
Q
D5
D
G
Q
D6
D
G
Q
D7
17
18
19
O0
O1
O2
O3
O4
O5
O6
O7
2
6
5
9
12
16
15
19
D0
14
7
3
8
4
13
D1
D2
D3
D4
D5
D6
D7
17
18
1
11
D
CP
Q Q
D
CP
Q Q
D
CP
Q Q
D
CP
Q Q
D
CP
Q Q
D
CP
Q Q
D
CP
Q Q
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK
Input Clamp Diode Voltage
0.65
1.5
V
VCC = MIN, IIN = 18 mA
VOH
Output HIGH Voltage
2.4
3.1
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL
Output LOW Voltage
0.25
0.4
V
IOL = 12 mA
VCC = VCC MIN,
VIN VIL or VIH
VOL
Output LOW Voltage
0.35
0.5
V
IOL = 24 mA
VIN = VIL or VIH
per Truth Table
IOZH
Output Off Current HIGH
20
µ
A
VCC = MAX, VOUT = 2.7 V
IOZL
Output Off Current LOW
20
µ
A
VCC = MAX, VOUT = 0.4 V
IIH
Input HIGH Current
20
µ
A
VCC = MAX, VIN = 2.7 V
IIH
Input HIGH Current
0.1
mA
VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
0.4
mA
VCC = MAX, VIN = 0.4 V
IOS
Short Circuit Current (Note 1)
30
130
mA
VCC = MAX
ICC
Power Supply Current
40
mA
VCC = MAX
1. Not more than one output should be shorted at a time, nor for more than 1 second.
SN74LS373, SN74LS374
http://onsemi.com
4
AC CHARACTERISTICS
(TA = 25
°
C, VCC = 5.0 V)
Limits
LS373
LS374
Symbol
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
Test Conditions
fMAX
Maximum Clock Frequency
35
50
MHz
tPLH
tPHL
Propagation Delay,
Data to Output
12
12
18
18
ns
CL = 45 pF
tPLH
tPHL
Clock or Enable
to Output
20
18
30
30
15
19
28
28
ns
CL = 45 pF,
RL = 667
tPZH
tPZL
Output Enable Time
15
25
28
36
20
21
28
28
ns
tPHZ
tPLZ
Output Disable Time
12
15
20
25
12
15
20
25
ns
CL = 5.0 pF
AC SETUP REQUIREMENTS
(TA = 25
°
C, VCC = 5.0 V)
Limits
LS373
LS374
Symbol
Parameter
Min
Max
Min
Max
Unit
tW
Clock Pulse Width
15
15
ns
ts
Setup Time
5.0
20
ns
th
Hold Time
20
0
ns
DEFINITION OF TERMS
SETUP TIME (ts) -- is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to LE transition from HIGH-to-LOW in order to
be recognized and transferred to the outputs.
HOLD TIME (th) -- is defined as the minimum time
following the LE transition from HIGH-to-LOW that the
logic level must be maintained at the input in order to ensure
continued recognition.
SN74LS373
AC WAVEFORMS
Figure 1.
tW
tW
LE
1.3 V
OUTPUT
Dn
ts
th
tPLH
tPHL
Figure 2.
Figure 3.
1.3 V
1.3 V
1.3 V
OE
VOUT
OE
VOUT
tPHZ
1.3 V
1.3 V
tPZL
tPLZ
VOL
1.3 V
VOH
0.5 V
tPZH
1.3 V
1.3 V
0.5 V
SN74LS373, SN74LS374
http://onsemi.com
5
SN74LS373
SW2
CL*
5.0 k
SW1
VCC
RL
TO OUTPUT
UNDER TEST
Figure 4.
* Includes Jig and Probe Capacitance.
AC LOAD CIRCUIT
SWITCH POSITIONS
Closed
Open
Closed
Closed
Open
Closed
Closed
Closed
tPZH
tPZL
tPLZ
tPHZ
SW2
SW1
SYMBOL
SN74LS374
AC WAVEFORMS
OE
VOUT
1.3 V
1.3 V
tPZL
tPLZ
VOL
1.3 V
1.3 V
0.5 V
CP
Dn
OUTPUT
tPLH
tWH
tWL
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
ts
th
tPHL
Figure 5.
1.3 V
1.3 V
1.3 V
OE
VOUT
tPHZ
VOH
0.5 V
tPZH
1.3 V
Figure 6.
Figure 7.
SN74LS373, SN74LS374
http://onsemi.com
6
SN74LS374
SW2
CL*
5.0 k
SW1
VCC
RL
TO OUTPUT
UNDER TEST
* Includes Jig and Probe Capacitance.
AC LOAD CIRCUIT
Figure 8.
SWITCH POSITIONS
Closed
Open
Closed
Closed
Open
Closed
Closed
Closed
tPZH
tPZL
tPLZ
tPHZ
SW2
SW1
SYMBOL
DEVICE ORDERING INFORMATION
Device Order Number
Package Type
Tape and Reel Size
SN74LS373N
PDIP20
1440 Units/Box
SN74LS373DW
SOICWIDE
38 Units/Rail
SN74LS373DWR2
SOICWIDE
2500/Tape and Reel
SN74LS373M
SOEIAJ20
See Note 2
SN74LS373MEL
SOEIAJ20
See Note 2
SN74LS374N
PDIP20
1440 Units/Box
SN74LS374DW
SOICWIDE
38 Units/Rail
SN74LS374DWR2
SOICWIDE
2500/Tape and Reel
SN74LS374M
SOEIAJ20
See Note 2
SN74LS374MEL
SOEIAJ20
See Note 2
2. For ordering information on the EIAJ version of the SOIC package, please contact your local ON Semiconductor representative.
SN74LS373, SN74LS374
http://onsemi.com
7
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 73803
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
M
L
J
20 PL
M
B
M
0.25 (0.010)
T
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
25.66
27.17
1.010
1.070
B
6.10
6.60
0.240
0.260
C
3.81
4.57
0.150
0.180
D
0.39
0.55
0.015
0.022
G
2.54 BSC
0.100 BSC
J
0.21
0.38
0.008
0.015
K
2.80
3.55
0.110
0.140
L
7.62 BSC
0.300 BSC
M
0
15
0
15
N
0.51
1.01
0.020
0.040
_
_
_
_
E
1.27
1.77
0.050
0.070
1
11
10
20
A
SEATING
PLANE
K
N
F
G
D
20 PL
T
M
A
M
0.25 (0.010)
T
E
B
C
F
1.27 BSC
0.050 BSC
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D05
ISSUE F
20
1
11
10
B
20X
H
10X
C
L
18X
A1
A
SEATING
PLANE
q
h
X 45
_
E
D
M
0.25
M
B
M
0.25
S
A
S
B
T
e
T
B
A
DIM
MIN
MAX
MILLIMETERS
A
2.35
2.65
A1
0.10
0.25
B
0.35
0.49
C
0.23
0.32
D
12.65
12.95
E
7.40
7.60
e
1.27 BSC
H
10.05
10.55
h
0.25
0.75
L
0.50
0.90
q
0
7
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
_
_
SN74LS373, SN74LS374
http://onsemi.com
8
PACKAGE DIMENSIONS
M SUFFIX
SOEIAJ PACKAGE
CASE 96701
ISSUE O
DIM
MIN
MAX
MIN
MAX
INCHES
---
2.05
---
0.081
MILLIMETERS
0.05
0.20
0.002
0.008
0.35
0.50
0.014
0.020
0.18
0.27
0.007
0.011
12.35
12.80
0.486
0.504
5.10
5.45
0.201
0.215
1.27 BSC
0.050 BSC
7.40
8.20
0.291
0.323
0.50
0.85
0.020
0.033
1.10
1.50
0.043
0.059
0
0.70
0.90
0.028
0.035
---
0.81
---
0.032
A1
HE
Q1
LE
_
10
_
0
_
10
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
HE
A1
LE
Q1
_
c
A
Z
D
E
20
1
10
11
b
M
0.13 (0.005)
e
0.10 (0.004)
VIEW P
DETAIL P
M
L
A
b
c
D
E
e
L
M
Z
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without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or
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PUBLICATION ORDERING INFORMATION
JAPAN: ON Semiconductor, Japan Customer Focus Center
4321 NishiGotanda, Shinagawaku, Tokyo, Japan 1410031
Phone: 81357402700
Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
SN74LS373/D
Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 3036752175 or 8003443860 Toll Free USA/Canada
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