Semiconductor Components Industries, LLC, 2004

April, 2004 - Rev. 2

Publication Order Number:

NCP5210/D

NCP5210

3-in-1 PWM Dual Buck
and Linear DDR Power
Controller

The NCP5210, 3-in-1 PWM Dual Buck and Linear DDR Power

Controller, is a complete power solution for MCH and DDR memory.
This IC combines the efficiency of PWM controllers for the VDDQ
supply and the MCH core supply voltage with the simplicity of linear
regulator for the VTT termination voltage.

This IC contains two synchronous PWM buck controller for driving

four external N-Ch FETs to form the DDR memory supply voltage
(VDDQ) and the MCH regulator. The DDR memory termination
regulator (VTT) is designed to track at the half of the reference voltage
with sourcing and sinking current.

Protective features include, soft-start circuitry, undervoltage

monitoring of 5VDUAL, and BOOT voltage, and thermal shutdown.
The device is housed in a thermal enhanced space-saving
QFN-20 package.

Features

Incorporates Synchronous PWM Buck Controllers for VDDQ and

VMCH

Integrated Power FETs with VTT Regulator Source/Sink up to 2.0 A

All External Power MOSFETs are N-Channel

Adjustable VDDQ and VMCH by External Dividers

VTT Tracks at Half the Reference Voltage

Fixed Switching Frequency of 250 kHz for VDDQ and VMCH

Doubled Switching Frequency (500 kHz) for VDDQ Controller in

Standby Mode to Optimize Inductor Current Ripple and Efficiency

Soft-start Protection for all Controllers

Undervoltage Monitor of Supply Voltages

Overcurrent Protections for DDQ and VTT Regulators

Fully Complies with ACPI Power Sequencing Specifications

Short Circuit Protection Prevents Damage to Power Supply Due to

Reverse DIMM Insertion

Thermal Shutdown

5x6 QFN-20 Package

Typical Applications

DDR I and DDR II Memory and MCH Power Supply

PIN CONNECTIONS

ORDERING INFORMATION

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NCP5210 = Specific Device Code
A

= Assembly Location

= Wafer Lot

= Year

= Work Week

MARKING
DIAGRAM

COMP

SW_DDQ

FBDDQ

PGND

BOOT

VTT

5VDUAL

VDDQ

AGND

FBVTT

DDQ_REF

FB1P5

BG_DDQ

TG_TDQ

COMP_1P5

BUF_Cut

TG_1P5

BG_1P5

GND_1P5

QFN-20

MN SUFFIX

CASE 505AB

NCP5210

AWLYYWW

For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

NOTE: Pin 21 is the thermal pad
on the bottom of the device.

Device

Package

Shipping

NCP5201MNR2

5x6 mm

QFN-20

2500 Tape and

Reel

NCP5210

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GND_1P5

VDDQ

ILIM

VOCP

OSC

CONTROL

LOGIC

TG_DDQ

PGND

SW_DDQ

BG_DDQ

VOLTAGE

and CURRENT

REFERENCE

VREF

_VREFGD

BOOT_

UVLO

VREF

R10

R11

VCC

THERMAL

SHUTDOWN

TSD

5VDUAL_

UVLO

R12

R13

5VDUAL

VREF

_5VDLGD

_BOOTGD

S0
S3

BUF_CUT

COUT1

VDDQ

COMP

RZ2

CZ2

CP1

RZ1

CZ1

FBDDQ

AMP

VREF

PGND

CSS

VTT

Regulation

Control

AGND

VDDQ

FBVTT

R18

R19

R17

R16

AGND

5VDUAL

AGND

PGND

COUT2

DDQ_REF

5VDUAL

12 V

BOOT

13 V

Zener

AMP_MCH

VREF

PGND

COMP_1P5

RZM2

CZM2

CPM1

RZM1

CZM1

FBDDQ

RM1

5VDUAL

COUT2

VMCH

TP_1P5

BG_1P5

RM2

5VDUAL

and

V1P5

PWM

LOGIC

Figure 2. Internal Block Diagram

180

Phase

Shift

VTT

PGND

NCP5210

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PIN DESCRIPTION

Pin

Symbol

Description

COMP

VDDQ error amplifier compensation node.

FBDDQ

DDQ regulator feedback pin.

Soft-start pin of DDQ and MCH.

PGND

Power ground.

VTT

VTT regulator output.

VDDQ

Power input for VTT linear regulator.

AGND

Analog ground connection and remote ground sense.

FBVTT

VTT regulator pin for closed loop regulation.

DDQ_REF

Reference voltage input of VTT regulator.

FB1P5

V1P5 switching regulator feedback pin.

GND_1P5

Power ground for V1P5 regulator.

BG_1P5

Gate driver output for V1P5 regulator low side N-Channel Power FET.

TG_1P5

Gate driver output for V1P5 regulator high side N-Channel Power FET.

BUF_Cut

Active HIGH control signal to activate S3 sleep state.

COMP_1P5

V1P5 error amplifier compensation node.

5VDUAL

5.0 V Dual supply input, which is monitored by undervoltage lock out circuitry.

BOOT

Gate driver input supply, which is monitored by undervoltage lock out circuitry, and a boost capacitor
connection between SWDDQ and this pin.

TG_DDQ

Gate driver output for DDQ regulator high side N-Channel Power FET.

BG_DDQ

Gate driver output for DDQ regulator low side N-Channel Power FET.

SW_DDQ

DDQ regulator switch node and current limit sense input.

TH_PAD

Copper pad on bottom of IC used for heatsinking. This pin should be connected to the ground plane under
the IC.

MAXIMUM RATINGS

Rating

Symbol

Value

Unit

Power Supply Voltage (Pin 16) to AGND (Pin 7)

5VDUAL

-0.3, 6.0

BOOT (Pin 17) to AGND (Pin 7)

BOOT

-0.3, 14

Gate Drive (Pins 12, 13, 18, 19) to AGND (Pin 7)

-0.3 DC,

-4.0 for

100 ns; 14

Input / Output Pins to AGND (Pin 7)

Pins 1-3, 5-6, 8-10, 14-15, 20

-0.3, 6.0

PGND (Pin 4), GND_1P5 (Pin 11) to AGND (Pin 7)

GND

-0.3, 0.3

Thermal Characteristics

QFN-20 Plastic Package
Thermal Resistance Junction-to-Air

C/W

Operating Junction Temperature Range

0 to + 150

Operating Ambient Temperature Range

0 to + 70

Storage Temperature Range

stg

- 55 to +150

Moisture Sensitivity Level

MSL

2.0

1. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM)

2.0 kV per JEDEC standard:

JESD22A114. Machine Model (MM)

200 V per JEDEC standard: JESD22A115.

2. Latchup Current Maximum Rating:

150 mA per JEDEC standard: JESD78.

NCP5210

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ELECTRICAL CHARACTERISTICS

(5VDUAL = 5 V, BOOT = 12 V, 5VATX = 5 V, DDQ_REF = 2.5 V, T

= 0

C to 70

C, L = 1.7

COUT1 = 3770

F, COUT2 = 470

F, COUT3 = NA, CSS = 33 nF, R1 = 2.166 k

, R2 = 2 k

, RZ1 = 20 k

, RZ2 = 8

, CP1 = 10 nF,

CZ1 = 6.8 nF, CZ2 = 100 nF, RM1 = 2.166 k

, RM2 = 2 k

, RZM1 = 20 k

, RZM2 = 8

, CPM1 = 10 nF, CZM1 = 6.8 nF, CZM2 = 100 nF

for min/max values unless otherwise noted.) duplicate component values of MCH regulator from DDQ.

Characteristic

Symbol

Test Conditions

Min

Typ

Max

Unit

SUPPLY VOLTAGE

5VDUAL Operating Voltage

V5VDUAL

4.5

5.0

5.5

BOOT Operating Voltage

VBOOT

12.0

13.2

SUPPLY CURRENT

S0 Mode Supply Current from 5VDUAL

I5VDL_S0

BUF_Cut = LOW, BOOT = 12 V

S3 Mode Supply Current from 5VDUAL

I5VDL_S3

BUF_Cut = HIGH

5.0

S5 Mode Supply Current from 5VDUAL

I5VDL_S5

BUF_Cut = LOW,

1.0

S0 Mode Supply Current from BOOT

IBOOT_S0

BUF_Cut = LOW, BOOT = 12 V,

TGDDQ, BGDDQ , TG_1P5 and

BG_1P5 Open

S3 Mode Supply Current from BOOT

IBOOT_S3

BUF_Cut = HIGH, TGDDQ,

BGDDQ, TG_1P5 and BG_1P5 Open

UNDER-VOLTAGE-MONITOR

5VDUAL UVLO Upper Threshold

V5VDLUV+

4.4

5VDUAL UVLO Hysteresis

V5VDLhys

250

400

550

BOOT UVLO Upper Threshold

VBOOTUV+

10.4

BOOT UVLO Hysteresis

VBOOThys

1.0

THERMAL SHUTDOWN

Thermal Shutdown

Tsd

(Note 3)

145

Thermal Shutdown Hysteresis

Tsdhys

(Note 3)

DDQ SWITCHING REGULATOR

FBDDQ Feedback Voltage,
Control Loop in Regulation

VFBQ

= 25

= 0

C to 70

1.178

1.166

1.190

1.202

1.214

Feedback Input Current

IDDQFB

V(FBDDQ) = 1.3 V

1.0

Oscillator Frequency in S0 Mode

FDDQS0

217

250

283

KHz

Oscillator Frequency in S3 Mode

FDDQS3

434

500

566

KHz

Oscillator Ramp Amplitude

VOSC

(Note 3)

1.3

Vp-p

Current Limit Blanking Time in S0 Mode

TDDQbk

(Note 3)

400

Current Limit Threshold Offset from 5VDUAL

OCP

(Note 3)

0.8

Minimum Duty Cycle

Dmin

Maximum Duty Cycle

Dmax

100

Soft-Start Pin Current for DDQ

Iss1

V(SS) = 0.5 V

4.0

DDQ ERROR AMPLIFIER

DC Gain

GAINDDQ

(Note 3)

Gain-Bandwidth Product

GBWDDQ

COMP PIN to GND = 220 nF,

1.0

in Series (Note 3)

MHz

Slew Rate

SRDDQ

COMP PIN TO GND = 10 pF

8.0

3. Guaranteed by design, not tested in production.

Part Number NCP5210