©
Semiconductor Components Industries, LLC, 2004
December, 2004 - Rev. 0
1
Publication Order Number:
NB7L86M/D
NB7L86M
2.5V/3.3V SiGe Differential
Smart Gate with CML Output
The NB7L86M is a multi-function differential Logic Gate, which
can be configured as an AND/NAND, OR/NOR, XOR/XNOR, or 2:1
MUX. This device is part of the GigaComm
family of high
performance Silicon Germanium products. The NB7L86M is an
ultra-low jitter multi-logic gate with a maximum data rate of 12 Gb/s
and input clock frequency of 8 GHz suitable for Data Communication
Systems, Telecom Systems, Fiber Channel, and GigE applications.
The device is housed in a low profile 3x3 mm 16-pin QFN package.
Differential inputs incorporate internal 50
W termination resistors
and accept LVNECL (Negative ECL), LVPECL (Positive ECL),
LVCMOS, LVTTL, CML, or LVDS. The differential 16 mA CML
output provides matching internal 50
W termination, and 400 mV
output swing when externally terminated 50
W to V
CC
.
Application notes, models, and support documentation are available
on www.onsemi.com.
Features
·
Maximum Input Clock Frequency up to 8 GHz
·
Maximum Input Data Rate up to 12 Gb/s Typical
·
30 ps Typical Rise and Fall Times
·
90 ps Typical Propagation Delay
·
2 ps Typical Within Device Skew
·
CML Output with Operating Range: V
CC
= 2.375 V to 3.465 V with
V
EE
= 0 V
·
CML Output Level (400 mV Peak-to-Peak Output) Differential
Output
·
50
W Internal Input and Output Termination Resistors
·
Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP
and SG Devices
Figure 1. Simplified Logic Diagram
D0
Q
SEL
VTD0
Q
SEL
VTD0
50
W
50
W
D0
D1
VTD1
VTD1
50
W
50
W
D1
50
W
50
W
VTSEL
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QFN-16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
*For additional marking information, refer to
Application Note AND8002/D.
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
16
NB7L
86M
ALYW
1
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
NB7L86M
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2
VTD1 D1
D1
VTD1
VTD0
D0
D0 VTD0
V
EE
Q
Q
V
CC
V
CC
SEL
SEL
VTSEL
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NB7L86M
Exposed Pad (EP)
Figure 2. Pin Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1, 9
V
CC
Power Supply
Positive Supply Voltage. All V
CC
pins must be externally connected to Power
Supply to guarantee proper operation.
2
SEL
LVPECL, CML, LVCMOS,
LVTTL, LVDS Input
Inverted Differential Select Logic Input.
3
SEL
LVPECL, CML, LVCMOS,
LVTTL, LVDS Input
Non-inverted Differential Select logic Input.
4
V
TSEL
-
Common Internal 50
W
termination pin for SEL/SEL. See Table 6. (Note 1)
5
V
TD1
-
Internal 50
W
Termination Pin for D1. See Table 6. (Note 1)
6
D1
LVPECL, CML, LVCMOS,
LVTTL, LVDS Input
Non-inverted Differential Clock/Data Input D1. (Note 1)
7
D1
LVPECL, CML, LVCMOS,
LVTTL, LVDS Input
Inverted Differential Clock/Data Input D1. (Note 1)
8
V
TD1
-
Internal 50
W
Termination Pin for D1. See Table 6. (Note 1)
10
Q
CML Output
Non-inverted Output with Internal 50
W
Source Termination Resistor. (Note 2)
11
Q
CML Output
Inverted Output with Internal 50
W
Source Termination Resistor. (Note 2)
12
V
EE
Power Supply
Negative Supply Voltage. All V
EE
pins must be externally connected to Power
Supply to guarantee proper operation.
13
V
TD0
-
Internal 50
W
Termination Pin for D0. (Note 1)
14
D0
LVPECL, CML, LVCMOS,
LVTTL, LVDS Input
Non-inverted Differential Clock/Data Input D0. (Note 1)
15
D0
LVPECL, CML, LVCMOS,
LVTTL, LVDS Input
Non-inverted differential clock/data input D0. (Note 1)
16
V
TD0
-
Internal 50
W
Termination Pin for D0. (Note 1)
-
EP
-
Exposed Pad. Thermal pad on the package bottom must be attached to a
heatsinking conduit to improve heat transfer.
1. In the differential configuration when the input termination pins (V
TDx
, V
TDx
) are connected to a common termination voltage or left open,
and if no signal is applied on Dx and Dx then the device will be susceptible to self-oscillation.
2. CML output require 50
W
receiver termination resistor to VCC for proper operation.
NB7L86M
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3
Q
SEL
VTD0
Q
SEL
VTD0
50
W
50
W
VTD1
VTD1
50
W
50
W
50
W
50
W
VTSEL
Figure 3. Configuration for AND/NAND Function
V
CC
VT or
V
BB
b
m
D0
D0
D1
D1
R
D
V
EE
V
CC
Table 2. AND/NAND TRUTH TABLE
(Note 3)
b
AND b
D0
D1
SEL
Q
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
1
3. D0, D1, SEL are complementary of D0, D1, SEL unless
specified otherwise.
Figure 4. Configuration for OR/NOR Function
Table 3. OR/NOR TRUTH TABLE
(Note 4)
0
0
1
1
D0
m
1
1
1
1
D1
b
0
1
0
1
SEL
m
or
b
0
1
1
1
Q
Q
SEL
VTD0
Q
SEL
VTD0
50
W
50
W
VTD1
VTD1
50
W
50
W
50
W
50
W
VTSEL
V
CC
VT or V
BB
b
m
D0
D0
D1
D1
4. D0, D1, SEL are complementary of D0, D1, SEL unless
specified otherwise.
Q
SEL
VTD0
Q
SEL
VTD0
50
W
50
W
VTD1
VTD1
50
W
50
W
50
W
50
W
VTSEL
b
m
D0
D0
D1
D1
Figure 5. Configuration for XOR/XNOR Function
1
0
0
D1
0
1
0
1
SEL
m
XOR
b
0
1
1
0
Q
Table 4. XOR/XNOR TRUTH TABLE
(Note 5)
0
0
1
1
D0
m
1
b
5. D0, D1, SEL are complementary of D0, D1, SEL unless
specified otherwise.
NB7L86M
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4
D0
Q
SEL
VTD0
Q
SEL
VTD0
50
W
50
W
D0
D1
VTD1
VTD1
50
W
50
W
D1
50
W
50
W
VTSEL
Figure 6. Configuration for 2:1 MUX Function
D1
D0
Q
Table 5. 2:1 MUX TRUTH TABLE
(Note 6)
1
0
SEL
6. D0, D1, SEL are complementary of D0, D1, SEL
unless specified otherwise.
Table 6. ATTRIBUTES
Characteristics
Value
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 1500 V
> 50 V
> 500 V
Moisture Sensitivity (Note 7)
QFN-16
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
Transistor Count
TBD
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
7. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
Table 7. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
V
CC
Positive Power Supply
V
EE
= 0 V
3.6
V
V
I
Input Voltage
V
EE
= 0 V
V
EE
V
I
V
CC
3.6
V
V
INPP
Differential Input Voltage |D - D|
V
CC
- V
EE
2.8 V
V
CC
- V
EE
<
2.8 V
2.8
|V
CC
- V
EE
|
V
V
I
IN
Input Current Through R
T
(50
W
Resistor)
Continuous
Surge
25
50
mA
mA
I
out
Output Current
Continuous
Surge
25
50
mA
mA
T
A
Operating Temperature Range
QFN-16
-40 to +85
°
C
T
stg
Storage Temperature Range
-65 to +150
°
C
q
JA
Thermal Resistance (Junction-to-Ambient)
(Note 8)
0 lfpm
500 lfpm
QFN-16
QFN-16
42
36
°
C/W
°
C/W
q
JC
Thermal Resistance (Junction-to-Case)
2S2P (Note 8)
QFN-16
3 to 4
°
C/W
T
sol
Wave Solder
Pb
Pb-Free
< 3 Sec @ 248
°
C
< 3 Sec @ 260
°
C
265
265
°
C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
8. JEDEC standard multilayer board - 2S2P (2 signal, 2 power).
NB7L86M
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5
Table 8. DC CHARACTERISTICS (
V
CC
= 2.375 V to 3.465 V, V
EE
= 0 V, T
A
= -40
°
C to +85
°
C)
Symbol
Characteristic
Min
Typ
Max
Unit
I
CC
Power Supply Current (Inputs and Outputs Open)
20
30
40
mA
V
OH
Output HIGH Voltage (Notes 9 and 10)
V
CC
- 60
V
CC
- 30
V
CC
mV
V
OL
Output LOW Voltage (Notes 9 and 10)
V
CC
- 460
V
CC
- 400
V
CC
- 310
mV
Differential Input Driven Single-Ended (see Figures 16 & 18)
V
th
Input Threshold Reference Voltage Range (Note 11)
1125
V
CC
- 75
mV
V
IH
Single-ended Input HIGH Voltage (Note 12)
V
th
+ 75
V
CC
mV
V
IL
Single-ended Input LOW Voltage (Note 12)
V
EE
V
CC
- 150
mV
Differential Inputs Driven Differentially (see Figures 17 & 19)
V
IHD
Differential Input HIGH Voltage
1200
V
CC
mV
V
ILD
Differential Input LOW Voltage
V
EE
V
CC
- 75
mV
V
CMR
Input Common Mode Range (Differential Configuration)
1163
V
CC
38
mV
V
ID
Differential Input Voltage (V
IHD -
V
ILD
)
75
2500
mV
I
IH
Input HIGH Current
D0/D0/D1/D1
SEL/SEL
0
-50
50
20
100
100
m
A
I
IL
Input LOW Current
D0/D0/D1/D1
SEL/SEL
0
-50
50
20
100
50
m
A
R
TIN
Internal Input Termination Resistor
45
50
55
W
R
TOUT
Internal Output Termination Resistor
45
50
55
W
R
Temp Coef
Internal I/O Termination Resistor Temperature Coefficient
-3.75
m
W
/
°
C
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board
with maintained airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range.
Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually
under normal operating conditions and not valid simultaneously.
9. CML outputs require 50
W
receiver termination resistors to V
CC
for proper operation.
10. Input and output parameters vary 1:1 with V
CC
.
11. V
th
is applied to the complementary input when operating in single-ended mode.
12. V
CMR
min varies 1:1 with V
EE
, V
CMR
max varies 1:1 with V
CC
.
NB7L86M
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6
Table 9. AC CHARACTERISTICS
(V
CC
= 2.375 V to 3.465 V, V
EE
= 0 V; Note 13)
Symbol
Characteristic
-40
_
C
25
_
C
85
_
C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
V
OUTPP
Output Voltage Amplitude (@V
INPPmin
) f
in
4 GHz
(See Figure 7)
f
in
8 GHz
240
125
350
230
240
125
350
230
240
125
350
230
mV
f
data
Maximum Operating Data Rate
10.7
12
10.7
12
10.7
12
Gb/s
t
PLH
,
t
PHL
Propagation Delay to
Dx/Dx to Q/Q
Output Differential @ 1 GHz
SEL/SEL to Q/Q
(See Figure 7)
70
110
90
135
120
160
70
110
90
135
120
160
70
110
90
135
120
160
ps
t
SKEW
Duty Cycle Skew (Note 14)
Device-to-Device Skew (Note 15)
2.0
5.0
10
20
2.0
5.0
10
20
2.0
5.0
10
20
ps
t
JITTER
RMS Random Clock Jitter (Note 16)
f
in
= 4 GHz
f
in
=8 GHz
Peak-to-Peak Data Dependent Jitter
f
in
= 4 Gb/s
(Note 17)
f
in
=10 Gb/s
0.2
0.2
4.0
4.0
0.7
0.7
10
10
0.2
0.2
4.0
4.0
0.7
0.7
10
10
0.2
0.2
4.0
4.0
0.7
0.7
10
10
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 18)
75
400
2600
75
400
2600
75
400
2600
mV
t
r
t
f
Output Rise/Fall Times @ 1 GHz
Q, Q
(20% - 80%)
35
60
35
60
35
60
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board
with maintained airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range.
Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually
under normal operating conditions and not valid simultaneously.
13. Measured by forcing V
INPP
(TYP) from a 50% duty cycle clock source. All loading with an external R
L
= 50
W
to V
CC
.
Input edge rates 40 ps (20% - 80%).
14. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw- and Tpw+ @1 GHz.
15. Device to device skew is measured between outputs under identical transition @ 1 GHz.
16. Additive RMS jitter with 50% duty cycle clock signal at 4 GHz and 10 GHz.
17. Additive peak-to-peak data dependent jitter with input NRZ data (PRBS 2
^23
-1) at 4 Gb/s and 10 Gb/s.
18. V
INPP
(MAX) cannot exceed V
CC
- V
EE
. Input voltage swing is a single-ended measurement operating in differential mode.
INPUT FREQUENCY (GHz)
Figure 7. Output Voltage Amplitude (V
OUTPP
) versus
Input Clock Frequency (f
in
) at Ambient Temperature (Typical)
OUTPUT VOL
T
AGE AMPLITUDE
(mV)
500
400
300
200
100
0
12
11
10
9
8
7
6
5
4
3
2
1
0
V
CC
- V
EE
= 3.3 V
V
CC
- V
EE
= 2.5 V
NB7L86M
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7
Figure 8. Typical Output Waveform at 2.488 GB/s
with PRBS 2
^23
-1 (V
inpp
= 75 mV)
Figure 9. Typical Output Waveform at 2.488 GB/s
with PRBS 2
^23
-1 (V
inpp
= 400 mV)
Figure 10. Typical Output Waveform at 10 GB/s
with PRBS 2
^23
-1 (V
inpp
= 75 mV)
Figure 11. Typical Output Waveform at 10 GB/s
with PRBS 2
^23
-1 (V
inpp
= 400 mV)
Figure 12. Typical Output Waveform at 12 GB/s
with PRBS 2
^23
-1 (V
inpp
= 75 mV)
Figure 13. Typical Output Waveform at 12 GB/s
with PRBS 2
^23
-1 (V
inpp
= 400 mV)
Time (72 ps/div)
Time (72 ps/div)
Time (20 ps/div)
Time (20 ps/div)
Time (16 ps/div)
Time (16 ps/div)
V
oltage (45 mV/div)
V
oltage (45 mV/div)
V
oltage (45 mV/div)
V
oltage (45 mV/div)
V
oltage (45 mV/div)
V
oltage (45 mV/div)
DDJ = 1.2 ps*
DDJ = 1.2 ps*
DDJ = 2 ps**
DDJ = 2 ps**
DDJ = 4 ps***
DDJ = 4 ps***
*Input signal DDJ = 10 ps
**Input signal DDJ = 12 ps
***Input signal DDJ = 14 ps
NB7L86M
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8
Figure 14. AC Reference Measurement
D
D
Q
Q
t
PHL
t
PLH
V
INPP
= V
IH
(D) - V
IL
(D)
V
OUTPP
= V
OH
(Q) - V
OL
(Q)
Driver
Device
Receiver
Device
Q
D
Figure 15. Typical Termination for Output Driver and Device Evaluation
(Refer to Application Note AND8020 - Termination of ECL Logic Devices)
Q
D
V
CC
50
W
50
W
Z = 50
W
Z = 50
W
Figure 16. Differential Input Driven
Single-Ended
Figure 17. Differential Inputs Driven
Differentially
Figure 18. V
th
Diagram
Figure 19. V
CMR
Diagram
D
V
CC
GND
V
IH
V
IHmin
V
IHmax
V
thmax
V
th
V
th
V
thmin
V
CMmax
V
CMmax
D
V
CMR
V
CC
GND
D
D
V
th
V
th
D
D
V
ILmax
V
IL
V
ILmin
D
V
ILDmax
V
IHDmax
V
ID
= V
IHD
- V
ILD
V
ILDtyp
V
IHDtyp
V
ILDmin
V
IHDmin
NB7L86M
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9
Q
Q
V
CC
16 mA
50
W
50
W
Figure 20. CML Output Structure
V
EE
Table 10. INTERFACING OPTIONS
INTERFACING OPTIONS
CONNECTIONS
CML
Connect VTD0, VTD0, VTD1, VTD1, VTSEL to V
CC
LVDS
Connect VTD0, VTD0 together for D0 input. Connect VTD1, VTD1 together for D0 input.
Leave VTSEL open for SEL input.
AC-COUPLED
Bias VTD0, VTD0, VTSEL and VTD1, VTD1 Inputs within (V
CMR
) Common Mode Range
RSECL, LVPECL
Standard ECL Termination Techniques. See AND8020/D.
LVTTL, LVCMOS
An external voltage should be applied to the unused complementary differential input.
Nominal voltage 1.5 V for LVTTL and V
CC
/2 for LVCMOS inputs.
NB7L86M
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10
Application Information
All inputs can accept PECL, CML, and LVDS signal
levels. The input voltage can range from V
CC
to 1.2 V.
Examples interfaces are illustrated below in a 50
W
environment (Z = 50
W).
50
W
V
CC
D
D
50
W
NB7L86M
V
CC
V
TD
V
EE
V
CC
Q
50
W
50
W
NB7L86M
V
EE
Figure 21. CML to CML Interface
Z
Q
Z
Figure 22. PECL to CML Receiver Interface
50
W
Z
V
CC
V
CC
LVDS
Driver
D
D
50
W
NB7L86M
V
EE
V
TD
V
EE
Figure 23. LVDS to CML Receiver Interface
50
W
Z
Z
V
CC
V
CC
PECL
Driver
D
D
50
W
NB7L86M
V
EE
V
BIAS
V
TD
V
EE
R
T
R
T
V
EE
V
CC
R
T
5.0 V 290
W
3.3 V 150
W
2.5 V
80
W
Recommended R
T
Values
50
W
50
W
V
TD
V
CC
V
TD
V
Bias
V
TD
Z
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11
ORDERING INFORMATION
Device
Package
Shipping
NB7L86MMN
QFN-16
123 Units/Rail
NB7L86MMNR2
QFN-16
3000 Tape & Reel
NB7L86MMNG
QFN-16
(Pb-Free)
123 Units/Rail
NB7L86MMNR2G
QFN-16
(Pb-Free)
3000 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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12
PACKAGE DIMENSIONS
16 PIN QFN
MN SUFFIX
CASE 485G-01
ISSUE B
16X
SEATING
PLANE
L
D
E
0.15 C
A
A1
e
D2
E2
b
1
4
5
8
12
9
16
13
ÇÇÇ
ÇÇÇ
ÇÇÇ
B
A
0.15 C
TOP VIEW
SIDE VIEW
BOTTOM VIEW
PIN 1
LOCATION
0.10 C
0.08 C
(A3)
C
16 X
e
16X
NOTE 5
0.10 C
0.05 C
A B
NOTE 3
K
16X
EXPOSED PAD
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. L
max
CONDITION CAN NOT VIOLATE 0.2 MM
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
DIM
MIN
MAX
MILLIMETERS
A
0.80
1.00
A1
0.00
0.05
A3
0.20 REF
b
0.18
0.30
D
3.00 BSC
D2
1.65
1.85
E
3.00 BSC
E2
1.65
1.85
e
0.50 BSC
K
0.20
---
L
0.30
0.50
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
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