Semiconductor Components Industries, LLC, 2005

June, 2005 - Rev. 0

Publication Order Number:

NB4N855S/D

NB4N855S
3.3 V, 1.5 Gb/s Dual

AnyLevelTM

to LVDS

Receiver/Driver/Buffer/

Translator

Description

NB4N855S is a clock or data Receiver/Driver/Buffer/Translator

capable of translating AnyLevel

input signal (LVPECL, CML,

HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the
distance, noise immunity of the system design, and transmission line
media, this device will receive, drive or translate data or clock signals
up to 1.5 Gb/s or 1.0 GHz, respectively. This device is pin-for-pin
plug in compatible to the SY55855V in a 3.3 V applications.

The NB4N855S has a wide input common mode range of

GND + 50 mV to V

- 50 mV. This feature is ideal for translating

differential or single-ended data or clock signals to 350 mV typical
LVDS output levels.

The device is offered in a small 10 lead MSOP package. NB4N855S

is targeted for data, wireless and telecom applications as well as high
speed logic interface where jitter and package size are main
requirements.

Application notes, models, and support documentation are available

at www.onsemi.com.

Features

Guaranteed Input Clock Frequency up to 1.0 GHz

Guaranteed Input Data Rate up to 1.5 Gb/s

490 ps Maximum Propagation Delay

1.0 ps Maximum RMS Jitter

180 ps Maximum Rise/Fall Times

Single Power Supply; V

= 3.3 V

±10%

Temperature Compensated TIA/EIA-644 Compliant LVDS Outputs

GND + 50 mV to V

- 50 mV V

CMR

Range

Figure 1. Typical Output Waveform at 1.5 Gb/s with K28.5

INPP

= 100 mV, Input Signal DDJ = 24 ps)

Device DDJ = 7 ps

TIME (133 ps/div)

VOL

AGE

(50 mV/div)

= Assembly Location

= Year

= Work Week

*For additional marking information, refer to

Application Note AND8002/D.

MARKING

DIAGRAM*

Micro 10

M SUFFIX

CASE 846B

http://onsemi.com

See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.

ORDERING INFORMATION

Functional Block Diagram

855S

AYW

NB4N855S

http://onsemi.com

GND

Figure 2. Pin Configuration and Block Diagram

(Top View)

Table 1. PIN DESCRIPTION

Pin

Name

I/O

Description

LVPECL, CML, LVCMOS,

LVTTL, LVDS

Noninverted Differential Clock/Data D0 Input.

LVPECL, CML, LVCMOS,

LVTTL, LVDS

Inverted Differential Clock/Data D0 Input.

LVPEL, CML, LVDS LVCMOS,

LVTTL

Noninverted Differential Clock/Data D1 Input.

LVPECL, CML, LVDS

LVCMOS LVTTL

Inverted Differential Clock/Data D1 Input.

GND

Ground. 0 V.

LVDS Output

Inverted Q1 output. Typically loaded with 100

receiver termination

resistor across differential pair.

LVDS Output

Noninverted Q1 output. Typically loaded with 100

receiver termination

resistor across differential pair.

LVDS Output

Inverted Q0 output. Typically loaded with 100

receiver termination

resistor across differential pair.

LVDS Output

Noninverted Q0 output. Typically loaded with 100

receiver termination

resistor across differential pair.

Positive Supply Voltage.

NB4N855S

http://onsemi.com

Table 2. ATTRIBUTES

Characteristics

Value

Moisture Sensitivity (Note 1)

Level 1

Flammability Rating

Oxygen Index: 28 to 34

UL 94 V-0 @ 0.125 in

ESD Protection

Human Body Model

Machine Model

Charged Device Model

> 2 kV

> 200 V

> 1 kV

Transistor Count

281

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

Table 3. MAXIMUM RATINGS

Symbol

Parameter

Condition 1

Condition 2

Rating

Unit

Positive Power Supply

GND = 0 V

3.8

Positive Input

GND = 0 V

= V

3.8

Input Current Through R

(50

Resistor)

Static
Surge

35
70

mA
mA

OSC

Output Short Circuit Current
Line-to-Line (Q to Q)
Line-to-End (Q or Q to GND)

Q or Q to GND
Q to Q

Continuous
Continuous

12
24

Operating Temperature Range

Micro 10

-40 to +85

stg

Storage Temperature Range

-65 to +150

Thermal Resistance (Junction-to-Ambient) (Note 2)

0 lfpm
500 lfpm

Micro 10
Micro 10

177
132

C/W

Thermal Resistance (Junction-to-Case)

1S2P (Note 4)

Micro 10

C/W

sol

Wave Solder

Pb-Free

<3 Sec @ 248

<3 Sec @ 260

265
265

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
2. JEDEC standard multilayer board - 1S2P (1 signal, 2 power).

NB4N855S

http://onsemi.com

Table 4. DC CHARACTERISTICS, CLOCK INPUTS, LVDS OUTPUTS

= 3.0 V to 3.6 V, GND = 0 V, T

= -40

C to +85

Symbol

Characteristic

Min

Typ

Max

Unit

Power Supply Current (Note 3)

DIFFERENTIAL INPUTS DRIVEN SINGLE-ENDED (Figures 10 and 12)

Input Threshold Reference Voltage Range (Note 4)

GND +100

- 100

Single-ended Input HIGH Voltage

+ 100

Single-ended Input LOW Voltage

GND

- 100

DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 11 and 13)

IHD

Differential Input HIGH Voltage

100

ILD

Differential Input LOW Voltage

GND

- 100

CMR

Input Common Mode Range (Differential Configuration)

GND + 50

- 50

Differential Input Voltage (V

IHD

- V

ILD

)

100

LVDS OUTPUTS (Note 5)

Differential Output Voltage

250

450

Change in Magnitude of V

for Complimentary Output States (Note 6)

1.0

Offset Voltage (Figure 9)

1125

1375

Change in Magnitude of V

for Complimentary Output States (Note 6)

1.0

Output HIGH Voltage (Note 7)

1425

1600

Output LOW Voltage (Note 8)

900

1075

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.

3. Dx/Dx at the DC level within V

CMR

and output pins loaded with R

= 100

across differential.

4. V

is applied to the complementary input when operating in single-ended mode.

5. LVDS outputs require 100

receiver termination resistor between differential pair. See Figure 8.

6. Parameter guaranteed by design verification not tested in production.
7. V

max = V

max +

max.

8. V

max = V

min -

max.

NB4N855S

http://onsemi.com

Table 5. AC CHARACTERISTICS

= 3.0 V to 3.6 V, GND

= 0 V; (Note 9)

Symbol

Characteristic

-40

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

OUTPP

Output Voltage Amplitude (@ V

INPPMIN

1.0 GHz

(Figure 3)

= 1.5 GHz

230
200

350
300

230
200

350
300

230
200

350
300

DATA

Maximum Operating Data Rate

1.5

2.5

1.5

2.5

1.5

2.5

Gb/s

PLH

PHL

Differential Input to Differential Output
Propagation Delay

330

410

490

330

410

490

330

410

490

SKEW

Duty Cycle Skew (Note 10)
Within -Device Skew (Note 11)
Device to Device Skew (Note 12)

10
20

45
35

100

10
20

45
35

100

10
20

45
35

100

JITTER

RMS Random Clock Jitter (Note 13)

= 1.0 GHz

= 1.5 GHz

Deterministic Jitter (Note 14)

DATA

= 622 Mb/s

DATA

= 1.5 Gb/s

DATA

= 2.488 Gb/s

Crosstalk Induced Jitter (Note 15)

0.5
0.5

6
7

10
20

1
1

15
20
25
40

0.5
0.5

6
7

10
20

1
1

15
20
25
40

0.5
0.5

6
7

10
20

1
1

15
20
25
40

INPP

Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 16)

100

GND

100

GND

100

GND

Output Rise/Fall Times @ 250 MHz

Q, Q

(20% - 80%)

110

180

110

180

110

180

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

9. Measured by forcing V

INPPMIN

with 50% duty cycle clock source and V

- 1400 mV offset. All loading with an external R

= 100

across

"D" and "D" of the receiver. Input edge rates 150 ps (20%-80%).

10. See Figure 7 differential measurement of t

skew

= |t

PLH

- t

PHL

| for a nominal 50% differential clock input waveform @ 250 MHz.

11. The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition.
12. Skew is measured between outputs under identical transition @ 250 MHz.
13. RMS jitter with 50% Duty Cycle clock signal.
14. Deterministic jitter with input NRZ data at PRBS 2

-1 and K28.5.

15. Crosstalk Induced Jitter is the additive Deterministic jitter to channel one with channel two active both running at 622 Gb/s PRBS 2

-1 as

an asynchronous signals.

16. Input voltage swing is a single-ended measurement operating in differential mode.

INPUT CLOCK FREQUENCY (GHz)

Figure 3. Output Voltage Amplitude (V

OUTPP

) versus

Input Clock Frequency (f

) and Temperature (@ V

= 3.3 V)

OUTPUT

VOL

AGE

AMPLITUDE

(mV)

100

150

200

250

300

350

400

0.5

1.5

2.5

-40

NB4N855S

http://onsemi.com

Figure 4. Typical Output Waveform at 1.5 Gb/s with 2

23-1

INPP

= 100 mV (left) & V

INPP

= 400 mV (right), Input Signal DDJ = 24 ps)

Device DDJ = 6 ps

TIME (322 ps/div)

VOL

AGE

(50 mV/div)

Figure 5. Typical Output Waveform at 2.488 Gb/s with 2

23-1

INPP

= 100 mV (left) & V

INPP

= 400 mV (right), Input Signal DDJ = 30 ps)

Device DDJ = 6 ps

TIME (322 ps/div)

VOL

AGE

(50 mV/div)

Device DDJ = 10 ps

TIME (80 ps/div)

VOL

AGE

(50 mV/div)

Device DDJ = 10 ps

TIME (80 ps/div)

VOL

AGE

(50 mV/div)

1.25 k

Figure 6. Input Structure

NB4N855S

http://onsemi.com

Figure 7. AC Reference Measurement

PHL

PLH

INPP

= V

(D) - V

(D)

OUTPP

= V

(Q) - V

(Q)

Figure 8. Typical LVDS Termination for Output Driver and Device Evaluation

Driver
Device

Receiver
Device

LVDS

100

LVDS

= 50

Figure 9. LVDS Output

Figure 10. Differential Input Driven

Single-Ended

Figure 11. Differential Inputs Driven

Differentially

IHmax

ILmax

IHmin

ILmin

thmax

thmin

GND

Figure 12. V

Diagram

IH(MAX)

IL(MIN)

CMR

Figure 13. V

CMR

Diagram

INPP

= V

IHD

- V

ILD

NB4N855S

http://onsemi.com

PACKAGE DIMENSIONS

Micro10

CASE 846B-03

ISSUE D

0.08 (0.003)

DIM

MIN

MAX

MIN

MAX

INCHES

MILLIMETERS

2.90

3.10

0.114

0.122

2.90

3.10

0.114

0.122

0.95

1.10

0.037

0.043

0.20

0.30

0.008

0.012

0.50 BSC

0.020 BSC

0.05

0.15

0.002

0.006

0.10

0.21

0.004

0.008

4.75

5.05

0.187

0.199

0.40

0.70

0.016

0.028

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION "A" DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE
BURRS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.

4. DIMENSION "B" DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. 846B-01 OBSOLETE. NEW STANDARD

846B-02

-B-

-A-

PIN 1 ID

8 PL

0.038 (0.0015)

-T-

SEATING

PLANE

inches

SCALE 8:1

10X

1.04

0.041

0.32

0.0126

5.28

0.208

4.24

0.167

3.20

0.126

0.50

0.0196

*For additional information on our Pb-Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

NB4N855S

http://onsemi.com

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
"Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800-282-9855 Toll Free
USA/Canada

Japan: ON Semiconductor, Japan Customer Focus Center

2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051
Phone: 81-3-5773-3850

NB4N855S/D

AnyLevel is a trademark of Semiconductor Components Industries, LLC.

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082-1312 USA
Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada
Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada
Email: orderlit@onsemi.com

ON Semiconductor Website: http://onsemi.com

Order Literature: http://www.onsemi.com/litorder

For additional information, please contact your
local Sales Representative.

Part Number NB4N855S