September, 2005 - Rev. 0

Publication Order Number:

NB4N840M/D

NB4N840M

3.3V 2.7Gb/s Dual
Differential Clock/Data 2 x 2
Crosspoint Switch with
CML Output and Internal
Termination

Description

The NB4N840M is a high-bandwidth fully differential dual

2 x 2 crosspoint switch with CML inputs/outputs that is suitable for
applications such as SDH/SONET DWDM and high speed switching.
Fully differential design techniques are used to minimize jitter
accumulation, crosstalk, and signal skew, which make this device
ideal for loop-through and protection channel switching applications.
Each 2 x 2 crosspoint switch can fan-out and/or multiplex up to
2.7 Gb/s data and 2.7 GHz clock signals.

Internally terminated differential CML inputs accept AC-coupled

LVPECL (Positive ECL) or direct coupled CML signals. By providing
internal 50

W input and output termination resistor, the need for

external components is eliminated and interface reflections are
minimized. Differential 16 mA CML outputs provide matching
internal 50

W terminations, and 400 mV output swings when

externally terminated, 50

W to V

Single-ended LVCMOS/LVTTL SEL inputs control the routing of

the signals through the crosspoint switch which makes this device
configurable as 1:2 fan-out, repeater or 2 x 2 crosspoint switch. The
device is housed in a low profile 5 x 5 mm 32-pin QFN package.

Features

Plug-in compatible to the MAX3840 and SY55859L

Maximum Input Clock Frequency 2.7 GHz

Maximum Input Data Frequency 2.7 Gb/s

225 ps Typical Propagation Delay

80 ps Typical Rise and Fall Times

7 ps Channel to Channel Skew

430 mW Power Consumption

< 0.5 ps RMS Jitter

7 ps Peak-to-Peak Data Dependent Jitter

Power Saving Feature with Disabled Outputs

Operating Range: V

= 3.0 V to 3.6 V with V

= 0 V

CML Output Level (400 mV Peak-to-Peak Output), Differential

Output

These are Pb-Free Devices

QFN32

MN SUFFIX

CASE 488AM

See detailed ordering and shipping information on page 8 of
this data sheet.

ORDERING INFORMATION

MARKING
DIAGRAM

http://onsemi.com

NB4N

840M

ALYWG

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb-Free Package

CML

0
1

Figure 1. Functional Block Diagram

QA0

QA0
ENA0
SELA0
QA1

QA1
ENA1

SELA1

QB0

QB0
ENB0

SELB0

QB1

QB1
ENB1

SELB1

DA0
DA0

DA1
DA1

DB0
DB0

DB1
DB1

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Table 2. PIN DESCRIPTION

Pin

Name

I/O

Description

ENB1

LVTTL

Channel B1 Output Enable. LVTTL low input powers down B1 output stage.

DB1

CML Input

Channel B1 Positive Signal Input

DB1

CML Input

Channel B1 Negative Signal Input

ENB0

LVTTL

Channel B0 Output Enable. LVTTL low input powers down B0 output stage.

SELB0

LVTTL

Channel B0 Output Select. See Table 1.

DB0

CML Input

Channel B0 Positive Signal Input

DB0

CML Input

Channel B0 Negative Signal Input

SELB1

LVTTL

Channel B1 Output Select. See Table 1.

9,24

GND

Supply Ground. All GND pins must be externally connected to power supply to guarantee

proper operation.

10, 13, 16,

17, 20, 23

Positive Supply. All V

pins must be externally connected to power supply to guarantee

proper operation.

QB0

CML Output

Channel B0 Negative Output.

QB0

CML Output

Channel B0 Positive Output.

QB1

CML Output

Channel B1 Negative Output.

QB1

CML Output

Channel B1 Positive Output.

QA1

CML Output

Channel A1 Negative Output.

QA1

CML Output

Channel A1 Positive Output.

QA0

CML Output

Channel A0 Negative Output.

QA0

CML Output

Channel A0 Positive Output.

SELA1

LVTTL

Channel A1 Output Select, LVTTL Input. See Table 1.

DA0

CML Input

Channel A0 Positive Signal Input.

DA0

CML Input

Channel A0 Negative Signal Input.

SELA0

LVTTL

Channel A0 Output Select, LVTTL Input. See Table 1.

ENA0

LVTTL

Channel A0 Output Enable. LVTTL low input powers down A0 output stage.

DA1

CML Input

Channel A1 Positive Signal Input.

DA1

CML Input

Channel A1 Negative Signal Input.

ENA1

LVTTL

Channel A1 Output Enable. LVTTL low input powers down A1 output stage.

GND

Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing)

must be attached to a heat-sinking conduit. The exposed pad must be soldered to the

circuit board GND for proper electrical and thermal operation.

NB4N840M

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Table 3. ATTRIBUTES

Characteristics

Value

ESD Protection

Human Body Model

Machine Model

> 2000 V

> 110 V

Moisture Sensitivity (Note 1)

QFN-32

Level 1

Flammability Rating

Oxygen Index: 28 to 34

UL 94 V-0 @ 0.125 in

Transistor Count

380

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, refer to Application Note AND8003/D.

Table 4. MAXIMUM RATINGS

Symbol

Parameter

Condition 1

Condition 2

Rating

Unit

Positive Power Supply

GND = 0 V

3.8

Positive Input

GND = 0 V

GND = V

= V

3.8

INPP

Differential Input Voltage

|D - D|

3.8

Input Current Through Internal 50 W Resistor

Static

Surge

OUT

Output Current

Continuous

Surge

Operating Temperature Range

QFN-32

-40 to +85

°C

stg

Storage Temperature Range

-65 to +150

°C

Thermal Resistance (Junction-to-Ambient)

(Note 2)

0 lfpm

500 lfpm

QFN-32

°C/W

Thermal Resistance (Junction-to-Case)

2S2P (Note 3)

QFN-32

°C/W

sol

Wave Solder

Pb-Free <3 sec @ 260 C

260

°C

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit

values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,

damage may occur and reliability may be affected.

2. JEDEC standard 51-6, multilayer board - 2S2P (2 signal, 2 power).

3. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.

NB4N840M

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Table 5. DC CHARACTERISTICS, CLOCK INPUTS, CML OUTPUTS

= 3.0 V to 3.6 V, T

= -40°C to +85°C

Symbol

Characteristic

Min

Typ

Max

Unit

Power Supply Current (All outputs enabled)

130

170

Vout

diff

CML Differential Output Swing (Note 4, Figures 5 and 12)

640

800

1000

CMR

(Note 6)

CML Output Common Mode Voltage (Loaded 50 W to V

)

- 200

CML Single-Ended Input Voltage Range

- 0.8

+ 0.4

Differential Input Voltage (V

IHD

- V

ILD

)

300

1600

LVTTL CONTROL INPUT PINS

Input HIGH Voltage (LVTTL Inputs)

2000

Input LOW Voltage (LVTTL Inputs)

800

Input HIGH Current (LVTTL Inputs)

-10

Input LOW Current (LVTTL Inputs)

-10

TIN

CML Single-Ended Input Resistance

42.5

57.5

TOUT

Differential Output Resistance

100

115

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.

4. CML outputs require 50 W receiver termination resistors to V

for proper operation (Figure 10).

5. Input and output parameters vary 1:1 with V

6. V

CMR

min varies 1:1 with V

, V

CMR

max varies 1:1 with V

Table 6. AC CHARACTERISTICS

= 3.0 V to 3.6 V, V

= 0 V (Note 7, Figure 9)

Symbol

Characteristic

-40°C

25°C

85°C

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

OUTPP

Output Voltage Amplitude (@ V

INPPmin

) f

2 GHz

(See Figure 3)

3 GHz

3.5 GHz

280

235

170

365

310

220

280

235

170

365

310

220

280

235

170

365

310

220

DATA

Maximum Operating Data Rate

2.7

3.2

2.7

3.2

2.7

3.2

Gb/s

PLH

PHL

Propagation Delay to Output Differential

D/D to Q/Q

140

225

340

140

225

340

140

225

340

SKEW

Duty Cycle Skew (Note 8)

Within-Device Skew (Figure 4)

Device-to-Device Skew (Note 12)

JITTER

RMS Random Clock Jitter (Note 10) f

v 3.2 GHz

Peak-to-Peak Data Dependent Jitter f

= 2.5 Gb/s

(Note 11)

= 3.2 Gb/s

0.15

0.5

0.15

0.5

0.15

0.5

Crosstalk-Induced RMS Jitter (Note 13)

0.5

INPP

Input Voltage Swing/Sensitivity

(Differential Configuration) (Note 9)

150

800

150

800

150

800

Output Rise/Fall Times @ 0.5 GHz

Q, Q

(20% - 80%)

135

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

7. Measured by forcing V

INPP

(MIN) from a 50% duty cycle clock source. All loading with an external R

= 50 W to V

. Input edge rates 40 ps

(20% - 80%).

8. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw- and Tpw+ @ 0.5 GHz.

9. V

INPP

(MAX) cannot exceed 800 mV. Input voltage swing is a single-ended measurement operating in differential mode.

10.Additive RMS jitter using 50% duty cycle clock input signal.

11. Additive peak-to-peak data dependent jitter using input data pattern with PRBS 2

-1 and K28.5, V

INPP

= 400 mV.

12.Device to device skew is measured between outputs under identical transition @ 0.5 GHz.

13.Data taken on the same device under identical condition.

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Figure 3. Output Voltage Amplitude (V

OUTPP

)

vs. Input Clock Frequency (f

) at Ambient

Temperature (Typ)

100

150

200

250

300

350

400

450

0.05 0.5

1.5 2

2.5

3.5

4.5

INPUT CLOCK FREQUENCY (GHz)

OUTPUT

VOL

T
AGE AMPLITUDE (mV)

Figure 4. Within-Device Skew vs. Temperature

at V

= 3.3 V

-40

TEMPERATURE (°C)

TIME (ps)

Channel B

Channel A

Figure 5. CML Differential Voltage vs.

Temperature

100

200

300

400

500

600

700

800

900

-40

TEMPERATURE (°C)

VOL

T
AGE (mV)

Figure 6. Supply Current vs. Temperature

(All 4 Outputs Enabled)

110

120

130

140

150

160

170

-40

TEMPERATURE (°C)

CURRENT (mA)

Figure 7. Typical Output Waveform at 2.488 Gb/s

with PRBS 2

-1 (Input Signal DDJ = 12 ps)

Figure 8. Typical Output Waveform at 3.2 Gb/s

with K28.5 (Input Signal DDJ = 14 ps)

TIME (80.4 ps/div)

VOL

T
AGE (50 mV/div)

TIME (62.5 ps/div)

VOL

T
AGE (50 mV/div)

DDJ = 4 ps

DDJ = 3 ps

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PACKAGE DIMENSIONS

QFN32 5*5*1 0.5 P

CASE 488AM-01

ISSUE O

SEATING

32 X

0.15 C

(A3)

2 X

32 X

BOTTOM VIEW

EXPOSED PAD

TOP VIEW

SIDE VIEW

0.15 C

ÉÉ

PIN ONE

LOCATION

0.10 C

0.08 C

0.10

0.05 C

NOTES:

1. DIMENSIONS AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.25 AND 0.30 MM TERMINAL

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

PLANE

DIM MIN

NOM

MAX

MILLIMETERS

0.800 0.900 1.000

0.000 0.025 0.050

0.200 REF

0.180 0.250 0.300

5.00 BSC

2.950 3.100 3.250

5.00 BSC

0.500 BSC

0.200

---

0.300 0.400 0.500

2.950 3.100 3.250

*For additional information on our Pb-Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.50 PITCH

3.20

0.28

3.20

32 X

28 X

0.63

32 X

5.30

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

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"Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights

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Phone: 81-3-5773-3850

NB4N840M/D

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Part Number NB4N840M