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Part Number NB100LVEP91

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Semiconductor Components Industries, LLC, 2003
January, 2003 - Rev. 2
1
Publication Order Number:
NB100LVEP91/D
NB100LVEP91
2.5V / 3.3V Any Level
Positive Input to -2.5V /
-3.3V / -5V NECL Output
Translator
The NB100LVEP91 is a triple any level positive input to NECL
output translator. The device accepts LVPECL, LVTTL, LVCMOS,
HSTL, CML or LVDS signals, and translates them to differential
NECL output signals (-2.5 V / -3.3 V / -5 V).
To accomplish the level translation the LVEP91 requires three
power rails. The V
CC
supply should be connected to the positive
supply, and the V
EE
pin should be connected to the negative power
supply. The GND pins are connected to the system ground plane. Both
V
EE
and V
CC
should be bypassed to ground via 0.01
mF capacitors.
Under open input conditions, the D input will be biased at V
CC
/2
and the D input will be pulled to GND. These conditions will force the
Q outputs to a low, ensuring stability.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
·
Typical Maximum Frequency > 2.0 GHz
·
430 ps Typical Propagation Delay
·
Operating Range: V
CC
= 2.375 V to 3.8 V;
V
EE
= -2.375 V to -5.5 V; GND = 0 V
·
Q Output will Default LOW with Inputs Open or at GND
Device
Package
Shipping
ORDERING INFORMATION
MARKING
DIAGRAM*
*For additional information, see Application Note
AND8002/D
NB100LVEP91DW
38 Units/Rail
NB100LVEP91DWR2
1000/Tape & Reel
SO-20
SO-20
SO-20
DW SUFFIX
CASE 751D
1
20
1
20
NB100LVEP91
AWLYYWW
http://onsemi.com
QFN-24
QFN-24
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
N100
LP91
ALYW
1
24
24 PIN QFN
MN SUFFIX
CASE 485L
24
1
NB100LVEP91MN
93 Units/Rail
NB100LVEP91MNR2
3000/Tape & Reel
NB100LVEP91
http://onsemi.com
2
PIN DESCRIPTION
FUNCTION
Any Level Inputs
ECL Outputs
PECL Reference Voltage Output
Positive Supply (2.5 V, 3.3 V)
Negative Supply (-2.5 V, -3.3 V, -5 V)
Ground
No Connect
PIN
Dn*, Dn**
Qn, Qn
V
BB
V
CC
V
EE
GND
NC
Warning: All V
CC
, V
EE
, and GND pins must be externally con-
nected to Power Supply to guarantee proper operation.
D1
D1
D2
Q0
Q1
Q1
V
EE
D0
Q0
D2
D0
V
CC
Figure 1. Logic Diagram
Q2
Q2
D1
D1
D2
17
18
16
15
14
13
12
4
3
5
6
7
8
9
Q0
11
10
Q1
Q1
Q2
Q2
NC
V
EE
D0
19
20
2
1
V
CC
Q0
D0
D2
V
CC
V
BB
NB100LVEP91
GND
V
BB
GND
GND
V
BB
Figure 2. SOIC-20 Lead Pinout (Top View)
V
EE
D2
GND
Q0
D1
V
CC
V
CC
GND GND
Q1
V
BB
NC
V
BB
V
CC
GND
Q1
D1
D2
Q2
V
EE
NB100LVEP91
Figure 3. QFN-24 Lead Pinout (Top View)
Q2
Q0
D0
D0
18
12
4
3
5
6
7
8
9
11
10
2
1
17
16
15
14
13
19
24
23
22
20
21
*Pins will default differentially LOW when left open.
**Pins will default to V
CC
/2 when left open.
Warning: All V
CC
, V
EE
, and GND pins must be externally con-
nected to Power Supply to guarantee proper operation.
The thermally conductive exposed pad on package bottom
(see case drawing) must be attached to a heat-sinking conduit.
Positive Level
Input
NECL Output
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
W
Internal Input Pullup Resistor
75 k
W
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 150 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
Transistor Count
446 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
NB100LVEP91
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3
MAXIMUM RATINGS
(Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
V
CC
PECL Power Supply
GND = 0 V
3.8 to 0
V
V
EE
NECL Power Supply
GND = 0 V
-5.5 to 0
V
V
I
PECL Input Voltage
GND = 0 V
V
I
V
CC
3.8 to 0
V
V
OP
Operating Voltage
GND = 0 V
V
CC
- V
EE
9.3 to 0
V
I
out
Output Current
Continuous
Surge
50
100
mA
mA
I
BB
PECL V
BB
Sink/Source
±
0.5
mA
TA
Operating Temperature Range
-40 to +85
°
C
T
stg
Storage Temperature Range
-65 to +150
°
C
q
JA
Thermal Resistance (Junction-to-Ambient)
JESD 51-3 (1S-Single Layer Test Board)
0 lFPM
500 LFPM
20 SOIC
20 SOIC
90
60
°
C/W
°
C/W
q
JA
Thermal Resistance (Junction-to-Ambient)
JESD 51- 6 (2S2P Multilayer Test Board) with Filled Thermal Vias
0 LFPM
24 QFN
47.3
°
C/W
q
JC
Thermal Resistance (Junction-to-Case)
std bd
20 SOIC
30 to 35
°
C/W
T
sol
Wave Solder
<2 to 3 sec @ 248
°
C
265
°
C
2. Maximum Ratings are those values beyond which device damage may occur.
LVPECL INPUT DC CHARACTERISTICS
V
CC
= 2.5 V, V
EE
= -2.375 to -5.5 V, GND = 0 V (Note 3)
-40
°
C
25
°
C
85
°
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
I
CC
Power Supply Current
10
14
20
10
14
20
10
14
20
mA
V
IH
Input HIGH Voltage
1335
V
CC
1335
V
CC
1275
V
CC
mV
V
IL
Input LOW Voltage
GND
875
GND
875
GND
875
mV
V
IHCMR
Input HIGH Voltage Common Mode Range
(Differential) (Note 4)
0
2.5
0
2.5
0
2.5
V
I
IH
Input HIGH Current
150
150
150
m
A
I
IL
Input LOW Current
D
D
0.5
-150
0.5
-150
0.5
-150
m
A
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
3. Input parameters vary 1:1 with V
CC
. V
CC
can vary +1.3 V / -0.125 V.
4. V
IHCMR
min varies 1:1 with GND. V
IHCMR
max varies 1:1 with V
CC
.
LVPECL INPUT DC CHARACTERISTICS
V
CC
= 3.3 V; V
EE
= -2.375 V to -5.5 V; GND = 0 V (Note 5)
-40
°
C
25
°
C
85
°
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
I
CC
V
CC
Power Supply Current
10
16
24
10
16
24
10
16
24
mA
V
IH
Input HIGH Voltage (Single-Ended)
2135
V
CC
2135
V
CC
2135
V
CC
mV
V
IL
Input LOW Voltage (Single-Ended)
GND
1675
GND
1675
GND
1675
mV
V
BB
Output Voltage Reference (Note 6)
1775
1875
1975
1775
1875
1975
1775
1875
1975
mV
V
IHCMR
Input HIGH Voltage Common Mode Range
(Differential) (Note 6)
0
3.3
0
3.3
0
3.3
V
I
IH
Input HIGH Current
150
150
150
m
A
I
IL
Input LOW Current
D
D
0.5
-150
0.5
-150
0.5
-150
m
A
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
5. Input parameters vary 1:1 with V
CC
. V
CC
can vary +0.5 / -0.925 V.
6. V
IHCMR
min varies 1:1 with GND. V
IHCMR
max varies 1:1 with V
CC
.
NB100LVEP91
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4
NECL OUTPUT DC CHARACTERISTICS
V
CC
= 2.375 V to 3.8 V; V
EE
= -2.375 V to -5.5 V; GND = 0 V (Note 7)
-40
°
C
25
°
C
85
°
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
I
EE
V
EE
Power Supply Current
40
50
60
38
50
68
38
50
68
mA
V
OH
Output HIGH Voltage (Note 8)
-1 145
-1020
-895
-1 145
1020
-895
-1030
-1020
-895
mV
V
OL
Output LOW Voltage (Note 8)
-1945
-1725
-1600
-1945
-1725
-1600
-1945
-1725
-1600
mV
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
7. Output parameters vary 1:1 with GND.
8. All loading with 50
W
resistor to GND-2 volts.
AC CHARACTERISTICS
V
CC
= 2.375 V to 3.8 V; V
EE
= -2.375 V to -5.5 V; GND = 0 V
-40
°
C
25
°
C
85
°
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
V
opp
Output Voltage Amplitude
f
in
< 1.0 GHz
(Figure 4)
f
in
< 1.5 GHz
575
525
800
750
600
525
800
750
550
400
800
750
mV
t
PLH
t
PHL0
Propagation Delay
Differential
D to Q
Single-Ended
375
300
500
450
600
650
375
300
500
450
600
675
400
300
550
500
650
750
ps
t
SKEW
Pulse Skew (Note 9)
Output-to-Output (Note 10)
Part-to-Part (Diff)
(Note 10)
15
25
50
75
95
125
15
30
50
75
105
125
15
30
70
80
105
150
ps
t
JITTER
RMS Random Clock Jitter (Note 11)
f
in
= 2.0 GHz
Peak-to-Peak Data Dependant Jitter f
in
= 2.0 Gbps
(Note 12)
0.5
20
2.0
0.5
20
2.0
0.5
20
2.0
ps
V
PP
Input Voltage Swing (Note 13)
200
800
1200
200
800
1200
200
800
1200
mV
t
r
, t
f
Output Rise/Fall Times Q
(20% - 80%)
75
150
250
75
150
250
75
150
275
ps
9. Pulse Skew = |t
PLH
- t
PHL
|
10. Skews are valid across specified voltage range, part-to-part skew is for a given temperature.
11. RMS Jitter with 50% Duty Cycle Input Clock Signal.
12. Peak-to-Peak Jitter with input NRZ PRBS 2
31- 1
at 2.0 Gbps.
13. Input voltage swing is a single-ended measurement operating in differential mode. The device has a DC gain of
50.
Figure 4.
FREQUENCY (GHz)
0.5
1.0
1.5
2.0
2.5
250
350
450
550
650
750
850
OUTPUT AMPLITUDE (mV)
RMS JITTER (ps)
9.0
8.0
10
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
RMS JITTER
Q AMP
NB100LVEP91
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5
Application Information
All NB100LVEP91 inputs can accept LVPECL, LVTTL,
LVCMOS, HSTL, CML, or LVDS signal levels. The
limitations for differential input signal (LVDS, HSTL,
LVPECL, or CML) are the minimum input swing of 150 mV
and the maximum input swing of 3.0 V. Within these
conditions, the input voltage can range from V
CC
to GND.
Examples interfaces are illustrated below in a 50
W
environment (Z = 50
W)
V
EE
GND
GND
V
EE
Z
Z
V
CC
V
CC
GND
LVPECL
Driver
LVPECL91
50
W
V
TT
= V
CC
- 2.0 V
50
W
D
D
V
CC
V
CC
LVDS
Driver
LVPECL91
Z
Z
D
D
100
W
Figure 5. Standard LVPECL Interface
Z
Z
V
CC
V
CC
HSTL
Driver
LVPECL91
50
W
50
W
D
D
GND
Z
Z
V
CC
V
CC
CML
Driver
LVPECL91
50
W
V
CC
50
W
D
D
Figure 6. Standard LVDS Interface
Figure 7. Standard HSTL Interface
Figure 8. Standard 50
W
Load CML Interface
GND
V
EE
GND
GND
V
EE
GND
GND
V
EE
GND
V
EE
GND
GND
Z
V
CC
V
CC
LVTTL
Driver
LVPECL91
D
D
1.5 V
(Reference Voltage)
Figure 9. Standard LVTTTL Interface
Z
V
CC
V
CC
LVCMOS
Driver
LVPECL91
D
D
Open
Figure 10. Standard LVCMOS Interface
(D will default to V
CC
/2 when left open. A
reference voltage of V
CC
/2 should be applied to
D input, if D is interfaced to CMOS signals.)
GND
NB100LVEP91
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6
V TT = V CC - 2.0 V
Figure 11. Typical Termination for Output Driver and Device
Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
W
Driver
Device
Receiver
Device
Q
D
50
W
50
V TT
Q
D
Resource Reference of Application Notes
AN1404
-
ECLinPS Circuit Performance at Non-Standard V
IH
Levels
AN1405
-
ECL Clock Distribution Techniques
AN1503
-
ECLinPS I/O SPICE Modeling Kit
AN1504
-
Metastability and the ECLinPS Family
AN1560
-
Low Voltage ECLinPS SPICE Modeling Kit
AN1650
-
Using Wire-OR Ties in ECLinPS Designs
AN1672
-
The ECL Translator Guide
AND8002
-
Marking and Date Codes
AND8020
-
Termination of ECL Logic Devices
NB100LVEP91
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7
PACKAGE DIMENSIONS
SO-20
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-05
ISSUE F
20
1
11
10
B
20X
H
10X
C
L
18X
A1
A
SEATING
PLANE
q
h
X 45
_
E
D
M
0.25
M
B
M
0.25
S
A
S
B
T
e
T
B
A
DIM
MIN
MAX
MILLIMETERS
A
2.35
2.65
A1
0.10
0.25
B
0.35
0.49
C
0.23
0.32
D
12.65
12.95
E
7.40
7.60
e
1.27 BSC
H
10.05
10.55
h
0.25
0.75
L
0.50
0.90
q
0
7
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
_
_
QFN 24
MN SUFFIX
24 PIN QFN, 4x4
CASE 485L-01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
SEATING
PLANE
D
B
0.15 C
A2
A
A3
A
E
PIN 1
IDENTIFICATION
2X
0.15 C
2X
0.08 C
0.10 C
A1
C
DIM
MIN
MAX
MILLIMETERS
A
0.80
1.00
A1
0.00
0.05
A2
0.60
0.80
A3
0.20 REF
b
0.23
0.28
D
4.00 BSC
D2
2.70
2.90
E
4.00 BSC
E2
2.70
2.90
e
0.50 BSC
L
0.35
0.45
24X
L
D2
b
1
6
7
18
13
19
e
12
E2
e
24
0.10
B
0.05
A
C
C
REF
NB100LVEP91
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8
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changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
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liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or
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Phone: 81-3-5773-3850
Email: r14525@onsemi.com
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For additional information, please contact your local
Sales Representative.
NB100LVEP91/D
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