Semiconductor Components Industries, LLC, 2005

February, 2005 - Rev. 4

Publication Order Number:

NB100ELT23L/D

NB100ELT23L

3.3V Dual Differential

LVPECL/LVDS to LVTTL

Translator

The NB100ELT23L is a dual differential LVPECL/LVDS to LVTTL

translator. Because LVPECL (Positive ECL) or LVDS levels are used,
only +3.3 V and ground are required. The small outline 8-lead package
and the dual gate design of the ELT23L makes it ideal for applications
which require the translation of a clock and a data signal.

The ELT23L is available in only the ECL 100K standard. Since

there are no LVPECL outputs or an external V

reference, the

ELT23L does not require both ECL standard versions. The LVPECL
inputs are differential. Therefore, the NB100ELT23L can accept any
standard differential LVPECL/LVDS input referenced from a V

+3.3 V.

2.1 ns Typical Propagation Delay

Maximum Operating Frequency > 160 MHz

24 mA LVTTL Outputs

Operating Range: V

3.0 V to 3.6 V with GND = 0 V

Q Output Will Default LOW with Inputs Open or at GND

Pb-Free Packages are Available*

*For additional information on our Pb-Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

*For additional information, see Application Note
AND8002/D

MARKING

DIAGRAMS*

A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week

ALYW

K23L

SO-8

D SUFFIX

CASE 751

TSSOP-8

DT SUFFIX

CASE 948R

See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.

ORDERING INFORMATION

http://onsemi.com

KT23L

ALYW

NB100ELT23L

http://onsemi.com

GND

Figure 1. 8-Lead Pinout (Top View) and

Logic Diagram

LVPECL

LVTTL

Table 1. PIN DESCRIPTION

PIN

FUNCTION

Q0, Q1

LVTTL Outputs

D0**, D1**
D0**, D1**

Differential LVPECL Inputs

Positive Supply

GND

Ground

**Pins will default to V

/2 when left open.

Table 2. ATTRIBUTES

Characteristics

Value

Internal Input Pulldown Resistor

50 k

Internal Input Pullup Resistor

50 k

ESD Protection

Human Body Model

Machine Model

Charged Device Model

> 1.5 kV

> 100 V

> 2 kV

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

Level 1

Flammability Rating

Oxygen Index: 28 to 34

UL 94 V-0 @ 1.25 in

Transistor Count

91 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

Table 3. MAXIMUM RATINGS

Symbol

Parameter

Condition 1

Condition 2

Rating

Units

Power Supply

GND = 0 V

3.8

Input Voltage

GND

0 V

3 8

Input Voltage

GND = 0 V

3.8

out

Output Current

Continuous
Surge

100

mA
mA

Operating Temperature Range

-40 to +85

stg

Storage Temperature Range

-65 to +150

Thermal Resistance (Junction-to-Ambient)

0 lfpm
500 lfpm

SO-8
SO-8

190
130

C/W

Thermal Resistance (Junction-to-Case)

Standard Board

SO-8

41 to 44

C/W

Thermal Resistance (Junction-to-Ambient)

0 lfpm
500 lfpm

TSSOP-8
TSSOP-8

185
140

C/W

Thermal Resistance (Junction-to-Case)

Standard Board

TSSOP-8

41 to 44

C/W

sol

Wave Solder

<2 to 3 sec @ 248

265

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.

NB100ELT23L

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Table 4. PECL DC CHARACTERISTICS

= 3.3 V, GND = 0 V (Note 2)

-40

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

CCH

Power Supply Current (Outputs set to HIGH)

CCL

Power Supply Current (Outputs set to LOW)

Input HIGH Voltage

2075

2420

2075

2420

2075

2420

Input LOW Voltage

1355

1675

1355

1675

1355

1675

IHCMR

Input HIGH Voltage Common Mode Range
(Note 3)

1.2

3.3

1.2

3.3

1.2

3.3

Input HIGH Current

150

Input LOW Current

-150

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.

2. All values vary 1:1 with V

3. V

IHCMR

min varies 1:1 with V

, V

IHCMR

max varies 1:1 with V

. The V

IHCMR

range is referenced to the most positive side of the differential

input signal.

Table 5. TTL DC CHARACTERISTICS

= 3.3 V, GND = 0.0 V, T

= -40

C to 85

Symbol

Characteristic

Condition

Min

Typ

Max

Unit

Output HIGH Voltage

= -3.0 mA

2.4

Output LOW Voltage

= 24 mA

0.5

Output Short Circuit Current

-180

-50

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

Table 6. AC CHARACTERISTICS

= 3.3 V

5%, GND = 0.0 V (Note 4)

-40

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

max

Maximum Frequency

160

MHz

PLH

PHL

Propagation Delay to Output Differential
(Note 5)

= 20 pF

1.95

2.5

2.95

1.95

2.5

2.95

1.95

2.6

3.25

SK+ +

SK- -

SKPP

Output-to-Output Skew++
Output-to-Output Skew- -
Part-to-Part Skew (Note 6)

60
25

500

60
25

500

60
25

500

JITTER

Random Clock Jitter (RMS)

6.0

Input Voltage Swing
(Differential Configuration)

150

800

1200

150

800

1200

150

800

1200

Output Rise/Fall Times
C

= 20 pF (0.8 V to 2.0 V)

700
300

900

1650
1000

700
300

900

1650
1000

700
300

900

1650
1000

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

4. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 500

to GND, C

= 20 pF.

5. Reference (V

= 3.3 V

5%; GND = 0 V).

6. Skews are measured between outputs under identical conditions.

NB100ELT23L

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Figure 2. TTL Output Loading Used for Device Evaluation

CHARACTERISTIC TEST

AC TEST LOAD

GND

includes

fixture
capacitance

APPLICATION

TTL RECEIVER

ORDERING INFORMATION

Device

Package

Shipping

NB100ELT23LD

SO-8

98 Units / Rail

NB100ELT23LDR2

SO-8

2500 Tape & Reel

NB100ELT23LDT

TSSOP-8

100 Units / Rail

NB100ELT23LDTG

TSSOP-8
(Pb-Free)

100 Units / Rail

NB100ELT23LDTR2

TSSOP-8

2500 Tape & Reel

NB100ELT23LDTR2G

TSSOP-8
(Pb-Free)

2500 Tape & Reel

For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

Resource Reference of Application Notes

AN1405/D

- ECL Clock Distribution Techniques

AN1406/D

- Designing with PECL (ECL at +5.0 V)

AN1503/D

- ECLinPS

I/O SPiCE Modeling Kit

AN1504/D

- Metastability and the ECLinPS Family

AN1568/D

- Interfacing Between LVDS and ECL

AN1642/D

- The ECL Translator Guide

AND8001/D

- Odd Number Counters Design

AND8002/D

- Marking and Date Codes

AND8020/D

- Termination of ECL Logic Devices

AND8066/D

- Interfacing with ECLinPS

AND8090/D

- AC Characteristics of ECL Devices

NB100ELT23L

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PACKAGE DIMENSIONS

SO-8

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751-07

ISSUE AE

SEATING
PLANE

X 45

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

6. 751-01 THRU 751-06 ARE OBSOLETE. NEW

STANDARD IS 751-07.

0.10 (0.004)

DIM

MIN

MAX

MIN

MAX

INCHES

4.80

5.00

0.189

0.197

MILLIMETERS

3.80

4.00

0.150

0.157

1.35

1.75

0.053

0.069

0.33

0.51

0.013

0.020

1.27 BSC

0.050 BSC

0.10

0.25

0.004

0.010

0.19

0.25

0.007

0.010

0.40

1.27

0.016

0.050

0.25

0.50

0.010

0.020

5.80

6.20

0.228

0.244

-X-

-Y-

0.25 (0.010)

-Z-

0.25 (0.010)

1.52

0.060

7.0

0.275

0.6

0.024

1.270
0.050

4.0

0.155

inches

SCALE 6:1

*For additional information on our Pb-Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

NB100ELT23L

http://onsemi.com

PACKAGE DIMENSIONS

DIM

MIN

MAX

MIN

MAX

INCHES

MILLIMETERS

2.90

3.10

0.114

0.122

2.90

3.10

0.114

0.122

0.80

1.10

0.031

0.043

0.05

0.15

0.002

0.006

0.40

0.70

0.016

0.028

0.65 BSC

0.026 BSC

4.90 BSC

0.193 BSC

SEATING

PLANE

PIN 1

DETAIL E

L/2

-U-

0.15 (0.006) T

0.10 (0.004)

-T-

-V-

-W-

0.25 (0.010)

8x REF

IDENT

0.25

0.40

0.010

0.016

TSSOP-8

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948R-02

ISSUE A

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED 0.25 (0.010)

PER SIDE.

5. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

6. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE -W-.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
"Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
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associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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PUBLICATION ORDERING INFORMATION

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USA/Canada

Japan: ON Semiconductor, Japan Customer Focus Center

2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051
Phone: 81-3-5773-3850

NB100ELT23L/D

ECLinPS is a trademark of Semiconductor Components Industries, LLC.

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Part Number NB100ELT23L