©
Semiconductor Components Industries, LLC, 2002
September, 2002 Rev. 2
1
Publication Order Number:
74ALVCH16374/D
74ALVCH16374
Low-Voltage 16-Bit D-Type
Flip-Flop with Bus Hold
1.8/2.5/3.3 V
(3State, NonInverting)
The 74ALVCH16374 is an advanced performance, noninverting
16bit Dtype flipflop. It is designed for very highspeed, very
lowpower operation in 1.8 V, 2.5 V or 3.3 V systems. The
VCXH16374 is byte controlled, with each byte functioning
identically, but independently. Each byte has separate Output Enable
and Clock Pulse inputs. These control pins can be tied together for full
16bit operation.
The 74ALVCH16374 consists of 16 edgetriggered flipflops with
individual Dtype inputs and 3.6 Vtolerant 3state outputs. The
clocks (CPn) and Output Enables (OEn) are common to all flipflops
within the respective byte. The flipflops will store the state of
individual D inputs that meet the setup and hold time requirements on
the LOWtoHIGH Clock (CP) transition. With the OE LOW, the
contents of the flipflops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. The OE input level
does not affect the operation of the flipflops. The data inputs include
active bushold circuitry, eliminating the need for external pullup
resistors to hold unused or floating inputs at a valid logic state.
·
Designed for Low Voltage Operation: V
CC
= 1.65 3.6 V
·
3.6 V Tolerant Inputs and Outputs
·
High Speed Operation:
3.6 ns max for 3.0 to 3.6 V
4.5 ns max for 2.3 to 2.7 V
7.8 ns max for 1.65 to 1.95 V
·
Static Drive:
±
24 mA Drive at 3.0 V
±
12 mA Drive at 2.3 V
±
4 mA Drive at 1.65 V
·
Supports Live Insertion and Withdrawal
·
Includes Active Bushold to Hold Unused or Floating Inputs at a Valid
Logic State
·
I
OFF
Specification Guarantees High Impedance When V
CC
= 0 V
·
Near Zero Static Supply Current in All Three Logic States (40
mA)
Substantially Reduces System Power Requirements
·
Latchup Performance Exceeds
±
250 mA @ 125
°
C
·
ESD Performance: Human Body Model >2000V; Machine Model >200V
·
Second Source to Industry Standard 74ALVCH16374
To ensure the outputs activate in the 3state condition, the output enable pins
should be connected to V
CC
through a pullup resistor. The value of the resistor is
determined by the current sinking capability of the output connected to the OE pin.
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MARKING DIAGRAM
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
TSSOP48
DT SUFFIX
CASE 1201
1
48
74ALVCH16374DT
AWLYYWW
1
48
Device
Package
Shipping
ORDERING INFORMATION
74ALVCH16374DTR
TSSOP
2500 / Reel
PIN NAMES
Function
Output Enable Inputs
Clock Pulse Inputs
Inputs
Outputs
Pins
OEn
CPn
D0D15
O0O15
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2
Figure 1. 48Lead Pinout
(Top View)
Figure 2. Logic Diagram
48
1
CP1
OE1
47
2
D0
O0
46
3
D1
O1
45
4
GND
GND
44
5
D2
O2
43
6
D3
O3
42
7
V
CC
V
CC
41
8
D4
O4
40
9
D5
O5
39
10
GND
GND
38
11
D6
O6
37
12
D7
O7
36
13
D8
O8
35
14
D9
O9
34
15
GND
GND
33
16
D10
O10
32
17
D11
O11
31
18
V
CC
V
CC
30
19
D12
O12
29
20
D13
O13
28
21
GND
GND
27
22
D14
O14
26
23
D15
O15
25
24
CP2
OE2
O0
D0
O1
D1
O2
D2
O3
D3
O4
D4
O5
D5
O6
D6
O7
D7
nCP
Q
D
nCP
Q
D
nCP
Q
D
nCP
Q
D
nCP
Q
D
nCP
Q
D
nCP
Q
D
nCP
Q
D
CP1
OE1
O8
D8
O9
D9
O10
D10
O11
D11
O12
D12
O13
D13
O14
D14
O15
D15
nCP
Q
D
nCP
Q
D
nCP
Q
D
nCP
Q
D
nCP
Q
D
nCP
Q
D
nCP
Q
D
nCP
Q
D
CP2
OE2
1
48
24
25
2
47
3
46
5
44
6
43
8
41
9
40
11
38
12
37
13
36
14
35
16
33
17
32
19
30
20
29
22
27
23
26
1
48
25
24
D0
47
D1
46
D2
44
D3
43
O0
2
EN1
OE1
CP1
CP2
OE2
O1
3
O2
5
O3
6
EN2
EN3
EN4
D4
41
D5
40
D6
38
D7
37
O4
8
O5
9
O6
11
O7
12
D8
36
D9
35
D10
33
D11
32
O8
13
O9
14
O10
16
O11
17
D12
30
D13
29
D14
27
D15
26
O12
19
O13
20
O14
22
O15
23
1
2
3
4
1
1
1
1
Figure 3. IEC Logic Diagram
Inputs
Outputs
Inputs
Outputs
CP1
OE1
D0:7
O0:7
CP2
OE2
D8:15
O8:15
L
H
H
L
H
H
L
L
L
L
L
L
X
L
X
O0
X
L
X
O0
X
H
X
Z
X
H
X
Z
H = High Voltage Level; L = Low Voltage Level; Z = High Impedance State;
= LowtoHigh Transition; X = High or Low Voltage Level and
Transitions Are Acceptable, for I
CC
reasons, DO NOT FLOAT Inputs. O0 = No Change.
74ALVCH16374
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3
MAXIMUM RATINGS
(Note 1)
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage
*
0.5 to
)
4.6
V
V
I
DC Input Voltage
*
0.5 to
)
4.6
V
V
O
DC Output Voltage
*
0.5 to
)
4.6
V
I
IK
DC Input Diode Current
V
I
< GND
*
50
mA
I
OK
DC Output Diode Current
V
O
< GND
*
50
mA
I
O
DC Output Sink Current
$
50
mA
I
CC
DC Supply Current per Supply Pin
$
100
mA
I
GND
DC Ground Current per Ground Pin
$
100
mA
T
STG
Storage Temperature Range
*
65 to
)
150
°
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
260
°
C
T
J
Junction Temperature Under Bias
)
150
°
C
q
JA
Thermal Resistance (Note 2)
90
°
C/W
MSL
Moisture Sensitivity
Level 1
F
R
Flammability Rating
Oxygen Index: 30 to 35
UL 94 VO @ 0.125 in
V
ESD
ESD Withstand Voltage
Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
u
2000
u
200
N/A
V
I
LATCHUP
LatchUp Performance
Above V
CC
and Below GND at 125
°
C (Note 6)
$
250
mA
Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute maximumrated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
1. I
O
absolute maximum rating must be observed.
2. Measured with minimum pad spacing on an FR4 board, using 10 mmby1 inch, 2ounce copper trace with no air flow.
3. Tested to EIA/JESD22A114A.
4. Tested to EIA/JESD22A115A.
5. Tested to JESD22C101A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
Supply Voltage
Operating
Data Retention Only
2.3
1.5
3.6
3.6
V
V
I
Input Voltage
(Note 7)
0.5
3.6
V
V
O
Output Voltage
(Active State)
(3State)
0
0
3.6
3.6
V
T
A
Operating FreeAir Temperature
*
40
)
85
°
C
D
t/
D
V
Input Transition Rise or Fall Rate
V
CC
= 2.5 V
$
0.2 V
V
CC
= 3.0 V
$
0.3 V
0
0
20
10
ns/V
7. Unused inputs may not be left open. All inputs must be tied to a highlogic voltage level or a lowlogic input voltage level.
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4
DC ELECTRICAL CHARACTERISTICS
T
A
=
*
40
5
C to
)
85
5
C
Symbol
Parameter
Condition
Min
Max
Unit
V
IH
HIGH Level Input Voltage
(N
)
1.65 V
v
V
CC
t
2.3 V
0.65
V
CC
V
(Note 8)
2.3 V
v
V
CC
v
2.7 V
1.7
2.7 V
t
V
CC
v
3.6 V
2.0
V
IL
LOW Level Input Voltage
(
)
1.65 V
v
V
CC
t
2.3 V
0.35
V
CC
V
(Note 8)
2.3 V
v
V
CC
v
2.7 V
0.7
2.7 V
t
V
CC
v
3.6 V
0.8
V
OH
HIGH Level Output Voltage
1.65 V
v
V
CC
v
3.6 V; I
OH
=
*
100
m
A
V
CC
*
0.2
V
V
CC
= 1.65 V; I
OH
=
*
4 mA
1.2
V
CC
= 2.3 V; I
OH
=
*
6 mA
2.0
V
CC
= 2.3 V; I
OH
=
*
12 mA
1.7
V
CC
= 2.7 V; I
OH
=
*
12 mA
2.2
V
CC
= 3.0 V; I
OH
=
*
12 mA
2.4
V
CC
= 3.0 V; I
OH
=
*
24 mA
2.0
V
OL
LOW Level Output Voltage
1.65 V
v
V
CC
v
3.6 V; I
OL
= 100
m
A
0.2
V
V
CC
= 1.65 V; I
OL
= 4 mA
0.45
V
CC
= 2.3 V; I
OL
= 6 mA
0.4
V
CC
= 2.3 V; I
OL
= 12 mA
0.7
V
CC
= 2.7 V; I
OL
= 12 mA
0.4
V
CC
= 3.0 V; I
OL
= 24 mA
0.55
I
I
Input Leakage Current
1.65 V
v
V
CC
v
3.6 V; 0 V
v
V
I
v
3.6 V
$
5.0
m
A
I
I(HOLD)
Minimum Bushold Input
Current
V
CC
= 3.6 V; V
IN
= 0 to 3.6 V
$
500
m
A
(
)
Current
V
CC
= 3.0 V, V
IN
= 0.8 V
75
V
CC
= 3.0 V, V
IN
= 2.0 V
*
75
V
CC
= 2.3 V, V
IN
= 0.7 V
45
V
CC
= 2.3 V, V
IN
= 1.7 V
*
45
V
CC
= 1.65 V, V
IN
= 0.58 V
25
V
CC
= 1.65 V, V
IN
= 1.07 V
*
25
I
OZ
3State Output Current
1.65 V
v
V
CC
v
3.6 V; 0 V
v
V
O
v
3.6 V; V
I
= V
IH
or V
IL
$
10
m
A
I
OFF
PowerOff Leakage Current
V
CC
= 0 V; V
I
or V
O
= 3.6 V
10
m
A
I
CC
Quiescent Supply Current
(N
)
1.65 V
v
V
CC
v
3.6 V; V
I
= GND or V
CC
40
m
A
(Note 9)
1.65 V
v
V
CC
v
3.6 V; 3.6 V
v
V
I
, V
O
v
3.6 V
$
40
D
I
CC
Increase in I
CC
per Input
2.7 V
t
V
CC
3.6 V; V
IH
= V
CC
*
0.6 V
750
m
A
8. These values of V
I
are used to test DC electrical characteristics only.
9. Outputs disabled or 3state only.
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5
AC CHARACTERISTICS (Note 10; t
R
= t
F
= 2.0 ns; C
L
= 30 pF; R
L
= 500
W
)
Limits
T
A
= 40
°
C to +85
°
C
Wave
V
CC
= 3.0 V to 3.6 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 1.65 V to 1.95 V
Symbol
Parameter
Wave
form
Min
Max
Min
Max
Min
Max
Unit
f
max
Clock Pulse Frequency
1
250
200
100
MHz
t
PLH
t
PHL
Propagation Delay
CP to On
1
1.0
1.0
3.6
3.6
1.0
1.0
4.5
4.5
1.0
1.0
7.8
7.8
ns
t
PZH
t
PZL
Output Enable Time to
High and Low Level
2
1.0
1.0
4.7
4.7
1.0
1.0
6.0
6.0
1.0
1.0
9.2
9.2
ns
t
PHZ
t
PLZ
Output Disable Time From
High and Low Level
2
1.0
1.0
4.1
4.1
1.0
1.0
5.1
5.1
1.5
1.5
6.8
6.8
ns
t
s
Setup Time, High or Low Dn to CP
3
1.5
0.5
2.5
ns
t
h
Hold Time, High or Low Dn to CP
3
1.0
0.5
1.0
ns
t
w
CP Pulse Width, High
3
1.5
0.5
4.0
ns
t
OSHL
t
OSLH
OutputtoOutput Skew
(Note 11)
0.5
0.5
0.5
0.5
0.75
0.75
ns
10. For C
L
= 50 pF, add approximately 300 ps to the AC maximum specification.
11. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGHtoLOW (t
OSHL
) or LOWtoHIGH (t
OSLH
); parameter
guaranteed by design.
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Condition
Typical
Unit
C
IN
Input Capacitance
Note 12
6
pF
C
OUT
Output Capacitance
Note 12
7
pF
C
PD
Power Dissipation Capacitance
Note 12, 10 MHz
20
pF
12. V
CC
= 1.8, 2.5 or 3.3 V; V
I
= 0 V or V
CC
.
WAVEFORM 1 - PROPAGATION DELAYS, SETUP AND HOLD TIMES
t
R
= t
F
= 2.0 ns, 10% to 90%; f = 1 MHz; t
W
= 500 ns
V
IH
0 V
Dn
CPn
Vm
On
V
IH
0 V
V
OH
V
OL
t
PLH
, t
PHL
t
h
t
s
Vm
Vm
f
max
WAVEFORM 2 - OUTPUT ENABLE AND DISABLE TIMES
t
R
= t
F
= 2.0 ns, 10% to 90%; f = 1 MHz; t
W
= 500 ns
V
IH
0 V
0 V
OEn
On
t
PZH
V
CC
t
PHZ
t
PZL
t
PLZ
On
Vm
Vm
Vm
V
OH
Vy
Vx
V
OL
Vm
Figure 4. AC Waveforms
Vm
Vm
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6
WAVEFORM 3 - PULSE WIDTH
t
R
= t
F
= 2.0 ns (or fast as required) from 10% to 90%
V
IH
0 V
V
IH
0 V
Vm
Vm
t
w
Vm
Vm
t
w
CPn
CPn
Figure 5. AC Waveforms
V
CC
Symbol
3.3 V
±
0.3 V
2.5 V
±
0.2 V
1.8 V
±
0.15 V
V
IH
2.7 V
V
CC
V
CC
V
m
1.5 V
V
CC
/2
V
CC
/2
V
x
V
OL
+ 0.3 V
V
OL
+ 0.15 V
V
OL
+ 0.15 V
V
y
V
OH
0.3 V
V
OH
0.15 V
V
OH
0.15 V
OPEN
PULSE
GENERATOR
R
T
DUT
V
CC
R
L
R
L
C
L
6 V or V
CC
×
2
GND
TEST
SWITCH
t
PLH
, t
PHL
Open
t
PZL
, t
PLZ
6 V at V
CC
= 3.3
±
0.3 V;
V
CC
×
2 at V
CC
= 2.5
±
0.2V; 1.8 V
±
0.15 V
t
PZH
, t
PHZ
GND
C
L
= 50 pF for V
CC
= 3.0
±
0.3 V
R
L
= 500
W
or equivalent
R
T
= Z
OUT
of pulse generator (typically 50
W
)
Figure 6. Test Circuit
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7
Figure 7. Carrier Tape Specifications
D
1
FOR COMPONENTS
10 PITCHES
CUMULATIVE
TOLERANCE ON
TAPE
±
0.2 mm
(
±
0.008")
2.0 mm
×
1.2 mm
AND LARGER
CENTER LINES
OF CAVITY
EMBOSSMENT
USER DIRECTION OF FEED
K
0
SEE
NOTE 2
P
0
P
2
D
E
F W
B
0
+
+
+
K
t
B
1
TOP
COVER
TAPE
P
SEE NOTE 2
A
0
FOR MACHINE REFERENCE
ONLY
INCLUDING DRAFT AND RADII
CONCENTRIC AROUND B
0
R MIN.
TAPE AND COMPONENTS
SHALL PASS AROUND RADIUS R"
WITHOUT DAMAGE
BENDING RADIUS
*TOP COVER
TAPE THICKNESS (t
1
)
0.10 mm
(0.004") MAX.
EMBOSSED
CARRIER
EMBOSSMENT
TYPICAL
COMPONENT CAVITY
CENTER LINE
TYPICAL
COMPONENT
CENTER LINE
MAXIMUM COMPONENT ROTATION
10
°
CAMBER (TOP VIEW)
ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250
mm
100 mm
(3.937")
1 mm
(0.039") MAX
250 mm
(9.843")
1 mm MAX
TAPE
EMBOSSED CARRIER DIMENSIONS (See Notes 1 and 2)
Tape
Size
B
1
Max
D
D
1
E
F
K
P
P
0
P
2
R
T
W
24mm
20.1mm
(0.791")
1.5 + 0.1mm
-0.0
(0.059
+0.004" -0.0)
1.5mm
Min
(0.060")
1.75
±
0.1 mm
(0.069
±
0.004")
11.5
±
0.10 mm
(0.453
±
0.004")
11.9 mm
Max
(0.468")
16.0
±
0.1 mm
(0.63
±
0.004")
4.0
±
0.1 mm
(0.157
±
0.004")
2.0
±
0.1 mm
(0.079
±
0.004")
30 mm
(1.18")
0.6 mm
(0.024")
24.3 mm
(0.957")
13. Metric Dimensions GovernEnglish are in parentheses for reference only.
14. A
0
, B
0
, and K
0
are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to
0.50 mm max. The component cannot rotate more than 10
°
within the determined cavity.
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8
Figure 8. Reel Dimensions
13.0 mm
±
0.2 mm
(0.512"
±
0.008")
1.5 mm MIN
(0.06")
50 mm MIN
(1.969")
20.2 mm MIN
(0.795")
FULL RADIUS
t MAX
G
A
REEL DIMENSIONS
Tape Size
A Max
G
t Max
24 mm
360 mm
(14.173")
24.4 mm + 2.0 mm, -0.0
(0.961" + 0.078", -0.00)
30.4 mm
(1.197")
Figure 9. Reel Winding Direction
DIRECTION OF FEED
BARCODE LABEL
HOLE
POCKET
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9
TAPE TRAILER
(Connected to Reel Hub)
NO COMPONENTS
160 mm MIN
TAPE LEADER
NO COMPONENTS
400 mm MIN
COMPONENTS
DIRECTION OF FEED
CAVITY
TAPE
TOP TAPE
Figure 10. Tape Ends for Finished Goods
Figure 11. Reel Configuration
User Direction of Feed
L
Figure 12. Package Footprint
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
É
É
É
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
É
É
É
F
K
G
ÉÉ
ÉÉ
ÉÉ
É
É
É
ÉÉ
ÉÉ
ÉÉ
É
É
É
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
É
É
É
ÉÉ
ÉÉ
ÉÉ
É
É
É
ÉÉ
ÉÉ
ÉÉ
48 Leads
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10
PACKAGE DIMENSIONS
TSSOP
DT SUFFIX
CASE 120101
ISSUE A
ÇÇÇ
ÇÇÇ
ÇÇÇ
S
U
M
0.12 (0.005)
V
S
T
S
U
M
0.254 (0.010)
T
V
B
A
L
K
U
48X REF
PIN 1
IDENT.
1
24
25
48
0.076 (0.003)
SEATING
D
T
PLANE
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
12.40
12.60
0.488
0.496
B
6.00
6.20
0.236
0.244
C
---
1.10
---
0.043
D
0.05
0.15
0.002
0.006
F
0.50
0.75
0.020
0.030
G
0.50 BSC
0.0197 BSC
H
0.37
---
0.015
---
J
0.09
0.20
0.004
0.008
J1
0.09
0.16
0.004
0.006
K
0.17
0.27
0.007
0.011
K1
0.17
0.23
0.007
0.009
L
7.95
8.25
0.313
0.325
M
0
8
0
8
_
_
_
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSIONS A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
ÉÉÉ
ÉÉÉ
ÉÉÉ
C
G
H
W
DETAIL E
J
K1
K
J1
SECTION NN
M
0.25 (0.010)
F
DETAIL E
N
N
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11
Notes
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12
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