TL H 10803

TP346

MICROWIR

Interfac

Devic

(MID)

July 1999

TP3465 MICROWIRE

Interface Device (MID)

General Description

The MICROWIRE

Interface Device MID gives a general

microprocessor (such as National Series 32000

proces-

sors Intel 80C188 80C86 or 80286 Motorola 6800 and
68000 family of processors) the ability to communicate effi-
ciently with up to eight peripheral devices via the serial MI-
CROWIRE interface The MID causes each of the peripheral
devices to appear to the mP as memory mapped locations
by performing all the data serialization and transfer proto-
cols to and from the peripherals

Applications

ISDN Terminal Adapters

Digital Line cards (ISDN and Non ISDN)

Analog Linecards using National COMBO

Interfacing to industry standard serial EEPROMs

Interfacing to industry standard MICROWIRE peripheral
devices such as Analog to Digital Converters LCD driv-
ers clock generators

Features

Multiplexed and Non-multiplexed microprocessor bus
compatible

National Intel and Motorola microprocessor bus
compatible

Microprocessor Clock (CKIN) up to 20 MHz

MICROWIRE clock speeds up to 5 MHz

Directly compatible with 8- and 16-bit MICROWIRE
peripherals

Commercial temperature range 0C to +70C

TP3465 for 8 Chip Select output

Memory mapped peripherals

Programmable MICROWIRE Clock to communicate with
devices of different speeds

Operates as MICROWIRE bus master or slave

28-pin PLCC Package

CMOS Low Power

Block Diagram

TL H 10803 1

FIGURE 1 MICROWIRE Interface Device MID

COMBO

Series 32000

and TRI-STATE

are registered trademarks of National Semiconductor Corporation

MICROWIRE

is a trademark of National Semiconductor Corporation

1999

National Semiconductor Corporation

Connection Diagrams

28-Pin PLCC

TL H 10803 3

Top View

Order Number TP3465V

See NS Package Number V28A

FIGURE 2. MICROWIRE Interface Device MID TP3465 Pinouts

Pin Description

Name

Pin No.

Type Function

28 Pkg.

28 I +5V Supply

GND 14 I 0V

CKIN 17 I Master Clock Input Used to Derive the SK Clock

MICROWIRE Interface

The MICROWIRE Interface consists of SK (clock out) SO (data out) SI (data in) and up to 8 chip select output lines

Name

Pin No.

Type Function

28 Pkg.

SK 13 O MICROWIRE clock output.

SO 15 O/I MICROWIRE data output. Can also be used for

MICROWIRE data input when communicating with special
devices See application section

SI 16 I MICROWIRE data input.

CS0-CS3 24-27 I/O Four input/output lines, normally used as outputs for chip

selects to MICROWIRE peripherals

CS4±CS7 6, 9, 20, I/O Four chip select lines accessible

23 when using the Multiplexed bus mode.

MultiplexedMicroprocessorBus Interface

The MULT INT pin is sampled on power-up and if LOW the microprocessor bus format is assumed to be Multiplexed and the
pin is considered an input pin to indicate Multiplexed bus format The pin has an internal pull-up and thus if pin is left floating it
will be considered as in Non-multiplexed mode The interface consists of an eight bit multiplexed Address Data microprocessor
bus (only the A0 A1 A2 and A3 address lines are decoded) and six control lines (CE RST AS MI RD DS WR (R W) and the
MULT input) which should be tied LOW

Name

Pin No.

Type Function

28 Pkg.

AD0-AD7 1, 2, 3, 4, I/O Address/Data bus. Transfers addresses and data

5 7 8 10 between the microprocessor and the MID

19 I Chip Enable. A LOW on this signal selects the MID for a

Read Write operation

/ 11 I Write or Read-Write direction. This signal indicates a Write

R W

operation or Read Write direction signal

/DS 12 I Read or Data Strobe. With an Intel mP this signal indicates

a Read operation (active low polarity signal) or with a
Motorola mP a Data strobe (active high polarity signal)

AS/MI 21 I Address Latch Enable or Address Strobe. A HIGH on this

line indicates an address on the external A D bus When
MULT

1 (non-multiplexed bus) the pin indicates the

type of bus MI

1 for NSC Intel format and MI

0 for

Motorola format

RST

22 I The RST

is the master Reset input when LOW forces the

device in the RESET condition (same as Power-on-
Reset)

MULT

/ 18 I Multiplexed Bus input or INTerrupt output. It is internally

INT

pulled HIGH to indicate a Non-Multiplexed bus format and
needs to be pulled LOW externally to indicate the
Multiplexed bus format

Non-Multiplexed Microprocessor Interface

The MULT INT pin is sampled on power-up and if not LOW the microprocessor bus format is assumed to be Non-multiplexed
This interface consists of a four-bit Address bus an eight-bit Data bus and six control lines (CE RST AS MI RD DS
WR (R WR) and the INT signal if enabled)

Name

Pin No

Type Function

28 Pkg

A0 A3 6 9 I Address bus These 4 pins (accessible in the 28-pin package)

20 23 are used to address the 16 registers

D0 D7 1 2 3 4 I O Data bus for data transfer between the microprocessor and the

5 7 8 10 MID

19 I Chip Enable A LOW on this signal selects the MID for a

Read Write operation

WR 11 I Write or Read-Write direction This signal indicates a Write
(R W) operation or Read Write direction signal

RD DS 12 I Read or Data Strobe With an Intel mP this signal indicates a

Read operation (active low polarity signal) or with a Motorola mP
a Data Strobe (active high polarity signal)

AS MI 21 I Address Latch Enable or Address Strobe A HIGH on this line

indicates an address on the external A D bus When MULT

(non-multiplexed bus) the pin indicates the type of bus MI

for NSC Intel format and MI

0 for Motorola format

Non-Multiplexed Microprocessor Interface

(Continued)

Name

Pin No

Type Function

28 Pkg

RST

22 I The RST is the master Reset input when LOW it forces the

device in the RESET condition (same as Power-on-Reset)

MULT 18 I Multiplexed Bus input or INTerrupt output It is internally pulled
INT

O HIGH to indicate a Non-multiplexed bus format and the pin can

be an INT output pin if enabled by setting the Inten bit in the
CKR register INT pulls low to indicate the completion of a
MICROWIRE transfer operation

Functional Description

The block diagram of the MICROWIRE Interface Device
(MID) is shown in

Figure 1 It essentially consists of a very

flexible microprocessor bus interface a serial MICROWIRE
interface and a Chip Select (output) port Internally it con-
tains a programmable clock divider to derive the MICRO-
WIRE clock speed from a system clock

MICROPROCESSOR INTERFACE

The Microprocessor bus interface supports both National
Intel and Motorola bus formats in the Multiplexed and Non-
multiplexed bus modes

The MULT INT pin is sampled on power-up and if LOW the
microprocessor bus format is assumed to be Multiplexed
and the pin is considered an input pin to indicate Multi-
plexed bus format The pin is internally pulled HIGH Upon
sampling if the pin is not LOW the bus format is assumed
to be Non-multiplexed

The microprocessor interface supports multiplexed Ad-
dress Data Formats for the Intel 8088 80188 and Motorola
6803 families to work in 8-bit mode Non-multiplexed busses
of the National 32000 Intel 80286 and Motorola 68000 se-
ries processors and similar are supported in the TP3465 28-
pin part Four address lines allow access to all MID regis-
ters

The MID incorporates a flexible bus interface logic to sup-
port the different address and data strobes required by the
different bus formats The timing specifications are shown in
a later section The following table shows microprocessor
bus control pin functions

MID Pin

NSC Intel Bus Motorola Bus

MUXed Non-MUXed MUXed Non-MUXed

AS MI ALE MI e 1

MI e 0

RD DS RD

DS DS

WR (R W)

(R W) (R W)

See

Figure 7 for connection of the AS and DS signals to

Motorola mPs

MICROWIRE COMMUNICATION MODES

The MID provides a MICROWIRE port to the main proces-
sor having two modes of operation with the MICROWIRE
peripherals software-controlled chip select and hard-
ware-generated chip select

modes

In the first scheme besides the 2 data byte registers there
is a third register which maps directly with the output CS

Chip Selects pins, which there eight pins for this function in
the TP3465 28-pin package . The software in the microproc-

essor then writes to the CS register to select and deselect
individual bits (corresponding to pins)

In the second scheme the CS pins are activated by a hard-
ware state machine when triggered by accessing the data
registers through other address locations (see section on
Register description) In this case the hardware will activate
the chip select pin send the appropriate number of MICRO-

WIRE data bits (8 or 16 ) and then deselect the pin. This

enhanced mode of communication allows the MICROWIRE
peripheral devices to appear as if I O mapped in the micro-
processor's memory space

CONTROL AND DATA REGISTERS

There are 6 control registers (PD MWM SKP SKR ST and
CS) and 1 set of Data registers (First MICROWIRE Byte
FMB and Second MICROWIRE Byte SMB)

for data com-

munication to MICROWIRE devices In normal mode the
Chip select pins CS0 C7 are controlled (via the CS register)
by software and data is transferred via the FMB and SMB
registers located at address 01h and 00h (see Table I)

Eight additional addresses (FMBD0 7) access the same
data register (FMB)

but provide additional information to

an internal state machine which drives appropriate chip se-
lect pins (e g

FMBD0 at address 02h controls CS0 pin

FMBD1 at address 03h controls CS1 pin etc ) There is
only 1 set of Data registers (FMB and SMB) which han-
dle the MICROWIRE communication

This latter method

of allocating special addresses to provide pin-select infor-
mation facilitates an enhanced MICROWIRE interface to
the host processor

Table I summarizes the Control and Data Registers and the
addresses at which they are accessed

Functional Description

(Continued)

TABLE I Control and Data Registers

Address

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

00h

SMB

01h

FMB

02h

FMBD0

03h

FMBD1

04h

FMBD2

05h

FMBD3

06h

FMBD4

07h

FMBD5

08h

FMBD6

09h

FMBD7

0Ah

cs7

cs6

cs5

cs4

cs3

cs2

cs1

cs0

0Bh

SKP

skp7

skp6

skp5

skp4

skp3

skp2

skp1

skp0

0Ch

MWM

mwm7

mwm6

mwm5

mwm4

mwm3

mwm2

mwm1

mwm0

0Dh

SKR

inten

soi

div2

div1

div0

0Eh

uwdone

0Fh

pd7

pd6

pd5

pd4

pd3

pd2

pd1

pd0

Pin Definition Register W Register

RESET condition is FFhex (all pins as Inputs)

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

pd7

pd6

pd5

pd4

pd3

pd2

pd1

pd0

pd0 7

bits configure the CS0 7 pins as inputs or outputs

For example pd0

1 sets the CS0 pin as an input pd0

0 sets CS0 pin as an output Upon chip RESET the pd0 7
bits are set to 1

SKP

MICROWIRE Clock (SK) Polarity W Register

RESET condition is 00hex (Normal MICROWIRE clock)

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

skp7

skp6

skp5

skp4

skp3

skp2

skp1

skp0

skp 0 7

bits set the polarity of the SK MICROWIRE clock

when communicating with device connected to each of the
pins CS0 7 For example skp0

0 normal MICROWIRE

mode (i e SO data output on negative edge of SK clock)
when sending data to device controlled by CS0 pin skp1

1 NSC COMBO II clock format for device controlled by CS1
(i e SO data output on the positive edge of SK clock)

MWM

MICROWIRE Mode Register W Register

RESET condition is 00hex

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

mwm7 mwm6 mwm5 mwm4 mwm3 mwm2 mwm1 mwm0

mwm0 7

bits specify whether 8 or 16 clocks are generated

for devices connected to CS0 7 pins For example mwm1

1 16 clocks will be generated for device controlled by

CS1 (16 data bits will be shifted out and 16 data bits will be
strobed in) mwm0

0 8 clocks will be generated for de-

vice controlled by CS0 (8 data bits will be shifted out and
strobed in)

SKR

MICROWIRE Clock (SK) Rate Register

W Register

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

inten

soi

div2

div1

div0

The 3 bits div0 2 give the divide-by value for deriving the
SK clock output rate from the CKIN The maximum CKIN
rate is 20 MHz and the slowest MICROWIRE peripheral
works at 256 kHz Table 2 below gives the division ratios
and some examples

div2

div1

div0

SK Ratio

e g CKIN

5 MHz

e g CKIN

20 MHz

CKIN

5 MHz

CKIN 2

2 5 MHz

CKIN 4

1 25 MHz

5 MHz

CKIN 8

625 kHz

2 5 MHz

CKIN 16

312 5 kHz

1 25 MHz

CKIN 32

156 25 kHz

625 kHz

CKIN 64

78 125 kHz

312 5 kHz

CKIN 128

39 06 kHz

156 25 kHz

TABLE 2 SK Clock Rate Control

Part Number TP3465