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Block Diagram

Configuration

Registers

Floppy Disk

Controller (FDC)

with

Digital Data

Separator (DDS)

(Enhanced 8477)

High Current Driver

Power-

Down

Logic

Plug and Play

Support

Micro-

Data and
Control

Floppy
Drive
Interface

IRQ

Data

Handshake

Configuration Input

Serial Interface

Serial

Interrupt

and DMA

SCC2

(16550 UART +

SCC1

(16550 UART)

Floppy

Drive

Interface

IEEE1284

Control

Parallel Port

Interface

Fast IR

Interface

DMA

IRQ Input

General

Chip Select

CS1,0

Channels

Signals

INFRARED)

Address

processor

87
33
8/

A
C

I
1.
0

d P

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9

9 C

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S
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I
/
O

General Description

The PC97338 is a fully ACPI 1.0 and PC98/99 com-
pliant, ISA based Super I/O. It is functionally compat-
ible with the PC87338. It includes a Floppy Disk
Controller (FDC), two Serial Communication Control-
lers (SCC) for UART and Infrared support, one
IEEE1284 compatible Parallel Port, and two general
purpose Chip Select signals for game port support.
The device supports power management as well as
3.3V and 5V mixed operation making it particularly
suitable for notebook and sub-notebook applications.

The PC87338 and PC97338 are fully compliant to the
Plug and Play specifications included in the "Hard-
ware Design Guide for Microsoft Windows 95".

Differences between the PC87338 and PC97338 are
indicated in italics. These differences are summarized
in Appendix A.

Features

Meets ACPI 1.0 and PC98/99 requirements

Backward compatible with PC87338

100% compatibility with Plug and Play require-
ments specified in the "

Hardware Design Guide for

Microsoft Windows 95

", ISA, EISA, and Micro-

Channel architectures

A special Plug and Play module includes:

-- Flexible IRQs, DMAs and base addresses

-- General Interrupt Requests (IRQs) that can be

multiplexed to the ten supported IRQs

November 1998

PC87338/PC97338
ACPI 1.0 and PC98/99 Compliant SuperI/O

TRI-STATE

is a registered trademark of National Semiconductor Corporation.

IBM

, MicroChannel

, PC-AT

and PS/2

are registered trademarks of International Business Machines Corporation.

Microsoft

and Windows

are registered trademarks of Microsoft Corporation.

1998 National Semiconductor Corporation

www.national.com

A new, high performance, on-chip Floppy Disk
Controller (FDC) provides:

-- Software compatibility with the PC8477, which

contains a superset of the floppy disk controller
functions in the

DP8473, the NEC

PD765A

and the N82077

-- A modifiable 13-bit address

-- Ten IRQ channel options

-- Four 8-bit DMA channel options

-- 16-byte FIFO

-- Burst and non-burst modes

-- Low-power CMOS with enhanced power-down

mode

-- A new, high-performance, on-chip, digital data

separator without external filter components

-- Support for 5.25"/3.5" floppy disk drives

-- Automatic media sense support

-- Perpendicular recording drive support

-- Three mode Floppy Disk Drive (FDD) support

-- Full support for IBM's Tape Drive Register

(TDR) implementation

-- Support for new fast tape drives (2 Mbps) and

standard tape drives (1 Mbps, 500 Kbps and
250 Kbps)

-- Support for both

and MFM modes

Two Serial Communication Controllers provide:

-- Software compatibility with the 16550A and the

16450

-- A modifiable 13-bit address

-- Ten IRQ channel options

-- MIDI baud rate support

-- Four 8-bit DMA channel options on SCC2

-- Shadow register support UART write-only bits

A fast universal Infrared interface on SCC2 sup-
ports the following:

-- Data rates of up to 115.2 Kbps (SIR)

-- A data rate of 1.152 Mbps (MIR)

-- A data rate of 4.0 Mbps (FIR)

-- Selectable internal or external modulation/de-

modulation (Sharp-IR)

-- Consumer Electronic IR mode

A bidirectional parallel port that includes:

-- A modifiable 13-bit address

-- Ten IRQ channel options

-- Four 8-bit DMA channel options

-- An Enhanced Parallel Port (EPP) compatible

with version EPP 1.9 (IEEE1284 compliant),
that also supports version EPP 1.7 of the Xir-
com specification.

-- An Extended Capabilities Port (ECP) that is

IEEE1284 compliant, including level 2

-- Bidirectional data transfer under either soft-

ware or hardware control

-- Compatibility with ISA, EISA, and MicroChan-

nel parallel ports

-- Multiplexing of additional external FDC signals

on parallel port pins that enables use of an ex-
ternal Floppy Disk Drive (FDD)

-- A protection circuit that prevents damage to the

parallel port when an external printer powers
up or operates at high voltages

-- 14 mA output drivers

Two general purpose pins for two programmable
chip select signals can be programmed for game
port control.

An address decoder that:

-- Selects all primary and secondary ISA ad-

dresses, including COM1-4 and LPT1-3

-- Decodes up to 16 address bits

Clock source:

-- An internal clock multiplier generates all re-

quired internal frequencies.

-- A clock input source 14.318 MHz, 24 MHz, or

48 MHz may be selected

Enhanced power management features:

-- Special power-down configuration registers

-- Enhanced programmable FDC command to

trigger power down

-- Programmable power-down and wake-up

modes

-- Two dedicated pins for FDC power manage-

ment

-- Low power-down current consumption (typical-

ly for PC97338, 400

A for 3.3V and 600

A for

5V application)

-- Reduced pin leakage current

-- Low power CMOS technology

-- The ability to shut off clocks to either the entire

chip or only to specific modules

Mixed voltage support provides:

-- Standard 5 V operation

-- Low voltage 3.3 V operation

-- Simultaneous internal 3.3 V operation and re-

ception or transmission to devices that have ei-
ther 3.3 V or 5 V power supply

100-pin TQFP VJG package - PC87338/PC97338

100-pin PQFP VLJ package - PC87338/PC97338

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Table of Contents

1.0 Pin Descriptions

1.1 CONNECTION DIAGRAMS ............................................................................................................. 18

1.2 SIGNAL/PIN DESCRIPTIONS .......................................................................................................... 22

2.0 Configuration

2.1 OVERVIEW ...................................................................................................................................... 36

2.2 CONFIGURATION REGISTER SETUP ........................................................................................... 36

2.2.1 Hardware Device Configuration .............................................................................................. 36

2.2.2 Software Device Configuration ................................................................................................ 38

2.2.3 Updating Configuration Registers ........................................................................................... 38

2.2.4 Reserved Bits in Configuration Registers ................................................................................ 38

2.2.5 INDEX and DATA Register Locations ..................................................................................... 38

2.2.6 Plug and Play Protocol ............................................................................................................ 39

2.3 THE CONFIGURATION REGISTERS .............................................................................................. 40

2.3.1 Configuration Register Bitmaps ............................................................................................... 41

2.3.2 Function Enable Register (FER), Index 00h ............................................................................ 45

2.3.3 Function Address Register (FAR), Index 01h .......................................................................... 47

2.3.4 Power and Test Register (PTR), Index 02h ............................................................................ 47

2.3.5 Function Control Register (FCR), Index 03h ........................................................................... 48

2.3.6 Printer Control Register (PCR), Index 04h .............................................................................. 49

2.3.7 Power Management Control Register (PMC), Index 06h ........................................................ 50

2.3.8 Tape, SCCs and Parallel Port Configuration Register (TUP), Index 07h ................................ 51

2.3.9 SuperI/O Chip Identification Register (SID), Index 08h ........................................................... 52

2.3.10 Advanced SuperI/O Chip Configuration Register (ASC), Index 09h ..................................... 52

2.3.11 Chip Select 0 Low Address Register (CS0LA), Index 0Ah .................................................... 53

2.3.12 Chip Select 0 Configuration Register (CS0CF), Index 0Bh ................................................... 53

2.3.13 Chip Select 1 Low Address Register (CS1LA), Index 0Ch .................................................... 54

2.3.14 Chip Select 1 Configuration Register (CS1CF), Index 0Dh ................................................... 54

2.3.15 Chip Select 0 High Address Register (CS0HA), Index 10h ................................................... 55

2.3.16 Chip Select 1 High Address Register (CS1HA), Index 11h ................................................... 55

2.3.17 SuperI/O Chip Configuration Register 0 (SCF0), Index 12h ................................................. 55

2.3.18 SuperI/O Chip Configuration Register 1 (SCF1), Index 18h ................................................. 56

2.3.19 Plug and Play Configuration 0 Register (PNP0), Index 1Bh ................................................. 57

2.3.20 Plug and Play Configuration 1 Register (PNP1), Index 1Ch ................................................. 58

2.3.21 SuperI/O Chip Configuration Register 2 (SCF2), Index 40h ................................................. 58

2.3.22 Plug and Play Configuration 2 Register (PNP2), Index 41h .................................................. 59

2.3.23 Parallel Port Base Address Low Byte Register (PBAL), Index 42h ....................................... 60

2.3.24 Parallel Port Base Address High Byte Register (PBAH), Index 43h ..................................... 60

2.3.25 SCC1 Base Address Low Byte Register (S1BAL), Index 44h ............................................... 61

2.3.26 SCC1 Base Address High Byte Register (S1BAH), Index 45h ............................................. 61

2.3.27 SCC2 Base Address Low Byte Register (S2BAL), Index 46h ............................................... 61

2.3.28 SCC2 Base Address High Byte Register (S2BAH), Index 47h ............................................. 62

2.3.29 FDC Base Address Low Byte Register (FBAL), Index 48h ................................................... 62

2.3.30 FDC Base Address High Byte Register (FBAH,) Index 49h .................................................. 62

Part Number PC97338