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PC87363 128-Pin LPC SuperI/O with MIDI and Game Ports, Extended Wake-Up and Protection
©
1999 National Semiconductor Corporation
General Description
The PC87363, a member of National Semiconductor's 128-
pin LPC SuperI/O family, introduces a Musical Instrument
Digital Interface (MIDI) Port and Game Port inputs for up to
two game devices. It also offers wake-up support for a wide
range of wake-up events, and new hardware and software
features to protect the system design. Like all members of
this family, it is PC99 and ACPI compliant, and offers a single-
chip solution to the most commonly used PC I/O peripherals.
The PC87363 also incorporates: Fan Speed Control and
Monitoring for two fans, a Floppy Disk Controller (FDC), a
Keyboard and Mouse Controller (KBC), a full IEEE 1284
Parallel Port, two enhanced Serial Ports (UARTs), one with
Infrared (IR) support, ACCESS.bus
®
Interface (ACB), Sys-
tem Wake-Up Control (SWC), General-Purpose Input/Out-
put (GPIO) support for a total of 49 ports and an enhanced
WATCHDOG
TM
timer.
Outstanding Features
q
MIDI Port compatible with MPU-401 UART mode
q
Game Port inputs for up to two game devices
q
Extended Wake-Up support, including legacy/ACPI
power button support, direct power supply control in
response to wake-up events, power-fail recovery
q
Protection features, including chassis intrusion detection,
GPIO lock and pin configuration lock
q
Serial IRQ support (15 options)
q
Bus interface, based on Intel's
LPC Interface Specifi-
cation Revision 1.0, September 29th, 1997
q
Fan Speed Control and Monitor for two fans
q
ACCESS.bus Interface, SMBus physical layer compatible
q
49 GPIO Ports (37 standard, including 23 with Assert
IRQ/SMI/PWUREQs interrupts; 12 V
SB
-powered)
q
Blinking LEDs
q
128-pin PQFP Package
Block Diagram
System Wake-Up
Serial Port 2
IEEE 1284
Wake-Up
Parallel Port
Ports
Keyboard &
Mouse I/F
SCL
ACCESS.bus
Floppy Disk
Controller
Floppy Drive
Interface
Keyboard &
Serial
Infrared
Interface Interface
Control
Events
Bus
Interface
LPC
Interface
I/O
2 Control
WATCHDOG
Timer
WDO
PWUREQ
Serial Port 1
Serial
Interface
V
DD
V
BAT
Outputs
Fan Speed
Control & Monitor
Interface
Mouse Controller
with IR
GPIO Ports
2 Monitor
Inputs
SDA
Serial
IRQ
Parallel Port
Interface
SMI
Ports
MIDI
Interface
MIDI Port
Game Port
Game Device
Interface
Power
Control
V
SB
PRELIMINARY
January 10, 1999
PC87363
128-Pin LPC SuperI/O with MIDI and Game Ports, Extended
Wake-Up and Protection
ACCESS.bus® is a registered trademark of Digital Equipment Corporation.
I2C® is a registered trademark of Philips Corporation.
IBM®, MicroChannel®, PC-AT® and PS/2® are registered trademarks of International Business Machines Corporation.
Microsoft® and Windows® are registered trademarks of Microsoft Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
WATCHDOG is a trademark of National Semiconductor Corporation.
SMBus® is a registered trademark of Intel Corporation.
2
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Features
·
Musical Instrument Digital Interface (MIDI) Port
-- Compatible with MPU-401 UART mode
-- 16-byte Receive and Transmit FIFOs
-- Loopback mode support
q
Game Port (GMP)
-- Compatible with the Legacy Game Port definition
-- Full digital implementation
-- Supports up to two analog game devices
·
Extended Wake-Up
-- Legacy and ACPI power button support
-- Direct power supply control in response to wake-up
events
-- Power-fail recovery
·
Protection
-- Chassis intrusion detection (CHASI, CHASO)
-- GPIO lock
-- Pin configuration lock
·
Fan Speed Control and Fan Speed Monitor (FSCM)
-- Supports different fan types
-- Speed monitoring for two fans
t
Digital filtering of the tachometer input signal
t
Alarm for fan slower than programmable thresh-
old speed
t
Alarm for fan stop
-- Two speed control lines with Pulse Width Modulation
(PWM)
t
Output signal in the range of 6 Hz to 93.75 KHz
t
Duty cycle resolution of 1/256
·
49 General-Purpose I/O (GPIO) Ports
-- 37 standard, with Assert IRQ/SMI/PWUREQ for 23
ports
-- 12 V
SB
-powered
-- Programmable drive type for each output pin (open-
drain, push-pull or output disable)
-- Programmable option for internal pull-up resistor on
each input pin
-- Output lock option
-- Input debounce mechanism
·
LPC System Interface
-- Synchronous cycles, up to 33 MHz bus clock
-- 8-bit I/O cycles
-- Up to four DMA channels
-- 8-bit DMA cycles
-- Basic read, write and DMA bus cycles are 13 clock
cycles long
·
PC99 and ACPI Compliant
-- PnP Configuration Register structure
-- Flexible resource allocation for all logical devices
t
Relocatable base address
t
15 IRQ routing options
t
4 optional 8-bit DMA channels (where applicable)
·
Floppy Disk Controller (FDC)
-- Programmable write protect
-- FM and MFM mode support
-- Enhanced mode command for three-mode Floppy
Disk Drive (FDD) support
-- Perpendicular recording drive support for 2.88 MB
-- Burst and non-burst modes
-- Full support for IBM Tape Drive register (TDR) im-
plementation of AT and PS/2 drive types
-- 16-byte FIFO
-- Software compatible with the PC8477, which con-
tains a superset of the FDC functions in the
µ
DP8473, the NEC
µ
PD765A and the N82077
-- High-performance, digital separator
-- Standard 5.25" and 3.5" FDD support
·
Parallel Port
-- Software or hardware control
-- Enhanced Parallel Port (EPP) compatible with new
version EPP 1.9 and IEEE 1284 compliant
-- EPP support for version EPP 1.7 of the Xircom spec-
ification
-- EPP support as mode 4 of the Extended Capabilities
Port (ECP)
-- IEEE 1284 compliant ECP, including level 2
-- Selection of internal pull-up or pull-down resistor for
Paper End (PE) pin
-- PCI bus utilization reduction by supporting a de-
mand DMA mode mechanism and a DMA fairness
mechanism
-- Protection circuit that prevents damage to the paral-
lel port when a printer connected to it powers up or
is operated at high voltages, even if the device is in
power-down
-- Output buffers that can sink and source 14 mA
·
Serial Port 1 (SP1)
-- Software compatible with the 16550A and the 16450
-- Shadow register support for write-only bit monitoring
-- UART data rates up to 1.5 Mbaud
·
Serial Port 2 with Infrared (SP2)
-- Software compatible with the 16550A and the 16450
-- Shadow register support for write-only bit monitoring
-- UART data rates up to 1.5 Mbaud
-- HP-SIR
-- ASK-IR option of SHARP-IR
-- DASK-IR option of SHARP-IR
-- Consumer Remote Control supports RC-5, RC-6,
NEC, RCA and RECS 80
-- Non-standard DMA support
-
1 or 2 channels
-- PnP dongle support
·
Keyboard and Mouse Controller (KBC)
-- 8-bit microcontroller
-- Software compatible with the 8042AH and PC87911
microcontrollers
-- 2 KB custom-designed program ROM
3
Features
(Continued)
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-- 256 bytes RAM for data
-- Five programmable dedicated open-drain I/O lines
-- Two data registers and one status register during
normal operation
-- Support for both interrupt and polling
-- 93 instructions
-- 8-bit timer/counter
-- Support for binary and BCD arithmetic
-- Operation at 8 MHz,12 MHz or 16 MHz (programma-
ble option)
-- Can be customized by using the PC87323, which in-
cludes a RAM-based KBC as a development plat-
form for KBC code
·
ACCESS.bus Interface (ACB)
-- Serial interface compatible with physical layer
-- Compatible with Philips' I
2
C
®
-- ACB master and slave
-- Supports polling and interrupt controlled operation
-- Optional internal pull-up on SDA and SCL pins
·
WATCHDOG Timer
-- Times out the system based on user-programmable
time-out period
-- System power-down capability for power saving
-- User-defined trigger events to restart WATCHDOG
-- Optional routing of WATCHDOG output on IRQ
and/or SMI lines
·
System Wake-Up Control (SWC)
-- Power-up request upon detection of Keyboard,
Mouse, RI1, RI2, RING activity and General-Pur-
pose Input Events, as follows:
t
Preprogrammed Keyboard or Mouse sequence
t
External modem ring on serial port
t
Ring pulse or pulse train on the RING input signal
t
Preprogrammed CEIR address in a preselected
standard (NEC, RCA or RC-5)
t
General-Purpose Input Events
t
IRQs of internal logical devices
-- Optional routing of power-up request on IRQ, SMI
and/or PWBTOUT
-- Battery-backed event configuration
-- Programmable VSB-powered output for blinking
LEDs (LED1, LED2) control
·
Clock Sources
-- 48 MHz clock input
-- LPC clock, up to 33 MHz
-- On-chip low frequency clock generator for wake-up
·
Power Supplies
-- 3.3V supply operation
-- Main (V
DD
)
-- Standby (V
SB
)
-- Battery backup (V
BAT
)
-- All pins are 5V tolerant and back-drive protected, ex-
cept LPC bus pins
·
Strap Configuration
-- Base Address (BADDR) strap to determine the base
address of the Index-Data register pair
-- Test strap to force the device into test mode (re-
served for National Semiconductor use)
-- Power Supply and LED Configuration (PSLDC0,1)
straps to determine the power suppy control func-
tions and the V
SB
power-up defaults of LED2
-- Power Supply On Polarity (PSONPOL) strap to set
PSON active state and output type
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Table of Contents
Datasheet Revision Record
.................................................................................................................... 4
1.0
Signal/Pin Connection and Description
1.1
CONNECTION DIAGRAM ......................................................................................................... 13
1.2
BUFFER TYPES AND SIGNAL/PIN DIRECTORY .................................................................... 14
1.3
PIN MULTIPLEXING ................................................................................................................. 19
1.4
DETAILED SIGNAL/PIN DESCRIPTIONS ................................................................................ 21
1.4.1
ACCESS.bus Interface (ACB) .................................................................................... 21
1.4.2
Bus Interface ............................................................................................................... 21
1.4.3
Clock ............................................................................................................................ 21
1.4.4
Fan Speed Control and Monitor (FSCM) ..................................................................... 21
1.4.5
Floppy Disk Controller (FDC) ...................................................................................... 22
1.4.6
Game Port .................................................................................................................. 23
1.4.7
General-Purpose Input/Output (GPIO) Ports ............................................................... 23
1.4.8
Infrared (IR) ................................................................................................................. 23
1.4.9
Keyboard and Mouse Controller (KBC)
..................................................................... 24
1.4.10
Musical Instrument Digital Interface (MIDI) Port .......................................................... 24
1.4.11
Parallel Port
............................................................................................................... 25
1.4.12
Power and Ground ..................................................................................................... 26
1.4.13
Protection .................................................................................................................... 26
1.4.14
Serial Port 1 and Serial Port 2 ..................................................................................... 26
1.4.15
Strap Configuration ...................................................................................................... 27
1.4.16
System Wake-Up Control ............................................................................................ 27
1.4.17
WATCHDOG Timer (WDT) ......................................................................................... 28
1.5
INTERNAL PULL-UP AND PULL-DOWN RESISTORS ............................................................ 29
2.0
Device Architecture and Configuration
2.1
OVERVIEW ............................................................................................................................... 31
2.2
CONFIGURATION STRUCTURE AND ACCESS ..................................................................... 31
2.2.1
The Index-Data Register Pair ...................................................................................... 31
2.2.2
Banked Logical Device Registers Structure ................................................................ 33
2.2.3
Standard Logical Device Configuration Register Definitions ....................................... 34
2.2.4
Standard Configuration Registers ............................................................................... 36
2.2.5
Default Configuration Setup ........................................................................................ 37
2.2.6
Power States ............................................................................................................... 37
2.2.7
Address Decoding ....................................................................................................... 38
2.3
PROTECTION ........................................................................................................................... 38
2.3.1
Chassis Intrusion Detection ......................................................................................... 38
2.3.2
Pin Configuration Lock ................................................................................................ 38
2.3.3
GPIO Pin Function Lock .............................................................................................. 39
2.4
POWER SUPPLY CONTROL (PSC) ......................................................................................... 39
2.5
LED OPERATION AND STATES .............................................................................................. 41
2.6
POWER SUPPLY CONTROL AND LED CONFIGURATION .................................................... 41
2.7
REGISTER TYPE ABBREVIATIONS ........................................................................................ 42
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