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PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O

General Description

The PC87307/PC97307 (VUL) are functionally identical
parts that offer a single-chip solution to the most commonly
used ISA, EISA and MicroChannel

peripherals. This fully

Plug and Play (PnP) compatible chip incorporates a Floppy
Disk Controller (FDC), a Keyboard and mouse Controller
(KBC), a Real-Time Clock (RTC), two fast full function
UARTs, Infrared (IR) support, a full IEEE 1284 parallel port,
three general purpose chip select signals that can be pro-
grammed for game port control, and a separate configura-
tion register set for each module. It also provides support for
power management (including a WATCHDOG timer) and
standard PC-AT address decoding for on-chip functions.

The Plug and Play (PnP) support in the device conforms to
the "

Plug and Play ISA Specification" Version 1.0a, May 5,

1994.

The Infrared (IR) interface complies with the IrDA 1.0 SIR
and SHARP-IR standards, and supports all four basic pro-
tocols for Consumer-IR (TV-Remote) circuitry (RC-5, RC-5
extended, RECS80 and NEC).

Features

100% compatible with Plug and Play requirements
specified in the "

Plug and Play ISA Specification", ISA,

EISA, and MicroChannel architectures

Meets PC97 requirements

PRELIMINARY

March 1998

PC87307/PC97307 Plug and Play Compatible and PC97
Compliant SuperI/O

Highlights

Block Diagram

Real-Time Clock

(Logical Device 2)

Floppy Disk

Controller (FDC)

with Digital Data

Separator (DDS)

(PC8477)

High Current Driver

Keyboard

Controller (KBC)

Power Management

Logic

P Address

Floppy
Drive
Interface

Data

Handshake

Data

Serial

Two UARTs + IR

(16550 or 16450)

X-Bus

IEEE1284

Control

Parallel Port

Interface

Infrared

Interface

Ports

(PnP)

IRQ

Control

DMA

Channels

(Logical Devices 5 & 6)

Interrupt

(RTC and APC)

Plug and Play

(Logical Device 8)

(Logical Device 0)

Data and

Control

(Logical Device 3)

Data and

Mouse

Controller

(Logical Device 1)

General Purpose

I/O Registers

(Logical Device 7)

I/O Ports

Data and

Control

(Logical Device 4)

Control

1998 National Semiconductor Corporation

TRI-STATE

is a registered trademark of National Semiconductor Corporation.

IBM

, MicroChannel

, PC-AT

and PS/2

are registered trademarks of International Business Machines Corporation.

Microsoft

and Windows

are registered trademarks of Microsoft Corporation.

Highlights

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A special Plug and Play (PnP) module that includes:

-- Flexible IRQs, DMAs and base addresses that meet

the Plug and Play requirements specified by Mi-
crosoft

in their 1995 hardware design guide for

Windows

and Plug and Play ISA Revision 1.0A

-- Plug and Play ISA mode (with isolation mechanism

Wait for Key state)

-- Motherboard Plug and Play mode

A Floppy Disk Controller (FDC) that provides:

-- A modifiable address that is referenced by a 16-bit

programmable register

-- Software compatibility with the PC8477, which con-

tains a superset of the floppy disk controller func-
tions in the

DP8473, the NEC

PD765A and the

N82077

-- 13 IRQ channel options

-- Four 8-bit DMA channel options

-- 16-byte FIFO

-- Burst and non-burst modes

-- A high-performance, internal, digital data separator

that does not require any external filter components

-- Support for standard 5.25" and 3.5" floppy disk

drives

-- Automatic media sense support

-- Perpendicular recording drive support

-- Three-mode Floppy Disk Drive (FDD) support

-- Full support for the IBM Tape Drive Register (TDR)

implementation of AT and PS/2 drive types

A Keyboard and mouse Controller (KBC) with:

-- A modifiable address that is referenced by a 16-bit

programmable register, reported as a fixed address
in resource data

-- 13 IRQ options for the keyboard controller

-- 13 IRQ options for the mouse controller

-- An 8-bit microcontroller

-- Software compatibility with the 8042AH and

PC87911 microcontrollers

-- 2 KB of custom-designed program ROM

-- 256 bytes of RAM for data

-- Five programmable dedicated open drain I/O lines

for keyboard controller applications

-- Asynchronous access to two data registers and one

status register during normal operation

-- Support for both interrupt and polling

-- 93 instructions

-- An 8-bit timer/counter

-- Support for binary and BCD arithmetic

-- Operation at 8 MHz,12 MHz or 16 MHz (programma-

ble option)

-- Can be customized using the PC87323VUL, which

includes a RAM-based KBC, as a development plat-
form for keyboard controller code

A Real-Time Clock (RTC) that has:

-- A modifiable address that is referenced by a 16-bit

programmable register

-- 13 IRQ options, with programmable polarity

-- DS1287, MC146818 and PC87911 compatibility

-- 242 bytes of battery backed up CMOS RAM in two

banks

-- Selective lock mechanism for the RTC RAM

-- Battery backed up century calendar in days, days of

the week, months and years, with automatic leap-
year adjustment

-- Battery backed-up time of day in seconds, minutes

and hours that allows a 12 or 24 hour format and ad-
justments for daylight savings time

-- BCD or binary format for time keeping

-- Three different maskable interrupt flags:

Periodic interrupts - At intervals from 122 msec
to 500 msec

Time-of-day alarm - At intervals from once per
second to once per day

Updated Ended Interrupt - Once per second
upon completion of update

-- Separate battery pin, 2.4 V operation that includes

an internal UL protection resistor

-- 2

A maximum power consumption during power

down

-- Double-buffer time registers

An Advanced Power supply Control (APC) that controls
the main power supply to the system, using open-drain
output, as follows:

Power turned on when:

-- The RTC reaches a pre-determined date and time.

-- A high to low transition occurs on the RI input signals

of the UARTs.

-- A ring pulse or pulse train is detected on the RING

input signal.

-- A SWITCH input signal indicates a Switch On event

Powered turned off when:

-- A SWITCH input signal indicates a Switch Off event

-- A Fail-safe event occurs (power-save mode detect-

ed but the system is hung up).

-- Software turns power off.

Two UARTs that provide:

-- Software compatibility with the 16550A and the

16450

-- A modifiable address that is referenced by a 16-bit

programmable register

-- 13 IRQ channel options

-- Shadow register support for write-only bits

-- Four 8-bit DMA options for the UART with Infrared

support (UART2)

An enhanced UART and Infrared (IR) interface on the
UART2 that supports:

-- UART data rates up to 1.5 Mbaud

-- IrDA 1.0 SIR

-- ASK-IR option of SHARP-IR

-- DASK-IR option of SHARP-IR

-- Consumer-IR (TV-Remote) circuitry

-- A Plug and Play compatible external transceiver

A bidirectional parallel port that includes:

-- A modifiable address that is referenced by a 16-bit

programmable register

Highlights

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-- Software or hardware control

-- 13 IRQ channel options

-- Four 8-bit DMA channel options

-- Demand mode DMA support

-- An Enhanced Parallel Port (EPP) that is compatible

with the new version EPP 1.9, and is IEEE1284
compliant

-- An Enhanced Parallel Port (EPP) that also supports

version EPP 1.7 of the Xircom specification.

-- Support for an Enhanced Parallel Port (EPP) as

mode 4 of the Extended Capabilities Port (ECP)

-- An Extended Capabilities Port (ECP) that is IEEE

1284 compliant, including level 2

-- Selection of internal pull-up or pull-down resistor for

Paper End (PE) pin

-- Reduction of PCI bus utilization by supporting a de-

mand DMA mode mechanism and a DMA fairness
mechanism

-- A protection circuit that prevents damage to the par-

allel port when a printer connected to it powers up or
is operated at high voltages

-- Output buffers that can sink and source14 mA

Three general purpose pins for three separate program-
mable chip select signals, as follows:

-- Can be programmed for game port control

-- The Chip Select 0 (CS0) signal produces open drain

output and is powered by the V

CCH

-- The Chip Select 1 (CS1) and 2 (CS2) signals have

push-pull buffers and are powered by the main V

-- Decoding of chip select signals depends on the ad-

dress and the Address Enable (AEN) signals, and
can be qualified using the Read (RD) and Write
(WR) signals.

16 single-bit General Purpose I/O ports (GPIO):

-- Modifiable addresses that are referenced by a 16-bit

programmable register

-- Programmable direction for each signal (input or

output) with configuration lock

-- Programmable drive type for each output pin (open-

drain or push-pull) with configuration lock

-- Programmable option for internal pull-up resistor on

each input pin with configuration lock

-- A back-drive protection circuit

An X-bus data buffer that connects the 8-bit X data bus
to the ISA data bus

Clock source options:

-- Source is a 32.768 KHz crystal - an internal frequen-

cy multiplier generates all the required internal fre-
quencies.

-- Source may be either a 48 MHz or 24 MHz clock in-

put signal.

Enhanced Power Management (PM), including:

-- Special configuration registers for power down

-- WATCHDOG timer for power-saving strategies

-- Reduced current leakage from pins

-- Low-power CMOS technology

-- Ability to shut off clocks to all modules

General features include:

-- All accesses to the SuperI/O chip activate a Zero

Wait State (ZWS) signal, except for accesses to the
Enhanced Parallel Port (EPP) and to configuration
registers

-- Access to all configuration registers is through an In-

dex and a Data register, which can be relocated
within the ISA I/O address space

-- 160-pin Plastic Quad Flatpack (PQFP) package

Table of Contents

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Table of Contents

Highlights ............................................................................................................................. 1

1.0

Signal/Pin Connection and Description

1.1

CONNECTION DIAGRAM ......................................................................................................... 14

1.2

SIGNAL/PIN DESCRIPTIONS ................................................................................................... 15

2.0

Configuration

2.1

HARDWARE CONFIGURATION ............................................................................................... 24

2.1.1

Wake Up Options ........................................................................................................ 24

2.1.2

The Index and Data Register Pair ............................................................................... 24

2.1.3

The Strap Pins ............................................................................................................. 25

2.2

SOFTWARE CONFIGURATION ............................................................................................... 25

2.2.1

Accessing the Configuration Registers ........................................................................ 25

2.2.2

Address Decoding ....................................................................................................... 25

2.3

THE CONFIGURATION REGISTERS ....................................................................................... 26

2.3.1

Standard Plug and Play (PnP) Register Definitions .................................................... 27

2.3.2

Configuration Register Summary ................................................................................ 30

2.4

CARD CONTROL REGISTERS ................................................................................................ 34

2.4.1

SID Register (In PC87307) .......................................................................................... 34

2.4.2

SID Register (In PC97307) .......................................................................................... 34

2.4.3

SuperI/O Configuration 1 Register, Index 21h ............................................................. 34

2.4.4

SuperI/O Configuration 2 Register, Index 22h ............................................................. 35

2.4.5

Programmable Chip Select Configuration Index Register, Index 23h ......................... 35

2.4.6

Programmable Chip Select Configuration Data Register, Index 24h .......................... 36

2.4.7

SRID Register (In PC97307 only) ................................................................................ 36

2.5

KBC CONFIGURATION REGISTER (LOGICAL DEVICE 0) .................................................... 36

2.5.1

SuperI/O KBC Configuration Register, Index F0h ....................................................... 36

2.6

FDC CONFIGURATION REGISTERS (LOGICAL DEVICE 3) .................................................. 36

2.6.1

SuperI/O FDC Configuration Register, Index F0h ....................................................... 36

2.6.2

Drive ID Register, Index F1h ....................................................................................... 37

2.7

PARALLEL PORT CONFIGURATION REGISTER (LOGICAL DEVICE 4) ............................... 37

2.7.1

SuperI/O Parallel Port Configuration Register, Index F0h ........................................... 37

2.8

UART2 AND INFRARED CONFIGURATION REGISTER (LOGICAL DEVICE 5) .................... 38

2.8.1

SuperI/O UART2 Configuration Register, Index F0h ................................................... 38

2.9

UART1 CONFIGURATION REGISTER (LOGICAL DEVICE 6) ................................................ 38

2.9.1

SuperI/O UART1 Configuration Register, Index F0h ................................................... 38

2.10

PROGRAMMABLE CHIP SELECT CONFIGURATION REGISTERS ...................................... 39

2.10.1

CS0 Base Address MSB, Second Level Index 00h ..................................................... 39

2.10.2

CS0 Base Address LSB Register, Second Level Index 01h ....................................... 39

2.10.3

CS0 Configuration Register, Second Level Index 02h ................................................ 39

2.10.4

Reserved, Second Level Index 03h ............................................................................. 39

2.10.5

CS1 Base Address MSB Register, Second Level Index 04h ...................................... 40

2.10.6

CS1 Base Address LSB Register, Second Level Index 05h ....................................... 40

Part Number PC87307