Äîêóìåíòàöèÿ è îïèñàíèÿ www.docs.chipfind.ru

TL V 11803

NSBMC290-16-20-25-33

Burst

Mode

Memory

Controller

July 1993

NSBMC290

-16 -20 -25 -33

Burst Mode Memory Controller

General Description

The

NSBMC290

functionally

equivalent

the

V29BMC

The NSBMC290 Burst Mode Memory Control-

ler is a single chip device designed to simplify the imple-
mentation of burst mode access in high performance sys-
tems using the Am29000

Streamlined Instruction Proces-

sor

The extremely high instruction rate achieved by this proces-
sor places extraordinary demands on memory system de-
signs if maximum throughput is to be sustained and costs
minimized

The most obvious solution to the problem of access speed
is to implement system memory using high-speed static
memories However the high cost and low density of these
devices make them an expensive and space consumptive
solution

A more cost effective method of solving this problem is via
the use of dynamic RAMs Their high density and low cost
make their use extremely attractive The impediment to their
use is their relatively slow access times

However when operated in page mode dynamic RAMs be-
have more like static memories Properly managed they
can yield access times approaching those of fully static
RAMs

The function of NSBMC290 is to interface the page mode
access protocol of dynamic RAMs with the more general
burst mode access protocol supported by the Am29000 lo-
cal channel The device manages a double banked arrang-
ment of dynamic RAMs such that when burst accesses are
permitted data can be read or written at the rate of one
word per system clock cycle

Packaged as a 124 pin PGA or 132 pin PQFP

the

NSBMC290 drives memory arrays directly thus minimizing
design complexity and package count

Features

Interfaces directly to Am29000 Local Channel

Manages Page Mode Dynamic Memory devices

Supports DRAMs from 64 KB to 16 MB

Manages Instruction and or Data Memory

Very Low Power Consumption

On-Chip Memory Address Multiplexer Drivers

Flexible Instruction Data Bus Buffer Management

Software-Configured operational parameters

Auto-Configured Bank Size and Location

High-Speed CMOS Technology

Block Diagram

Typical System Configuration

TL V 11803 1

Logic Symbol

TL V 11803 2

This document contains information concerning a product that has been developed by National Semiconductor Corporation V3 Corporation This information
is intended to help in evaluating this product National Semiconductor Corporation V3 Corporation reserves the right to change and improve the specifications
of this product without notice

TRI-STATE

is a registered trademark National Semiconductor Corporation

NSBMC290

is a trademark of National Semiconductor Corporation

V29BMC

is a trademark of V3 Corporation

Am29000

is a trademark of Advanced Micro Devices Sunnyvale California USA

C1995 National Semiconductor Corporation

RRD-B30M115 Printed in U S A

Pin Descriptions

PGA Pin

QFP Pin

Signal

A10

A11

132

A12

131

A13

129

A14

130

A15

128

A16

126

A17

125

A18

124

A19

123

A20

122

A21

127

A22

121

A23

120

A24

118

A25

119

A26

112

A27

110

A28

111

A29

113

A30

115

A31

K11

AA0

N13

AA1

L12

AA2

M13

AA3

K13

AA4

J12

AA5

J13

AA6

J11

AA7

H11

AA8

PGA Pin

QFP Pin

Signal

G13

AA9

G12

AA10

C11

AB0

B11

AB1

A12

AB2

A11

AB3

AB4

AB5

AB6

AB7

AB8

100

AB9

101

AB10

BINV

F11

CASA0

E13

CASA1

E12

CASA2

D13

CASA3

105

CASB0

106

CASB1

107

CASB2

108

CASB3

DBACK

M10

DBLEA

N12

DBLEB

DBREQ

N10

DBTXA

N11

DBTXB

DRDY

DREQ

DREQT0

DREQT1

IBACK

IBREQ

M11

IBTXA

M12

IBTXB

IRDY

IREQ

IREQT

B13

MWEA

B12

MWEB

PGA Pin

QFP Pin

Signal

OPT0

OPT1

OPT2

PDA

PEN

PIA

G11

RASA

102

RASB

A13

Reserved

C12

Reserved

D11

Reserved

RESET

L10

RSTOUT

SYSCLK

B10

D12

E11

F13

H12

103

L13

109

A10

C10

C13

F12

H13

K12

L11

104

114

Note

In order for the switching characteristics of this device to be guaranteed it is necessary to connect all of the power pins (V

) to the appropriate power

levels The use of low impedance wiring to the power pins is required In systems using the Am29000 with its attendant high switching rates multi-layer printed
circuit boards with buried power and ground planes are required

Pin Descriptions

Am29000 INTERFACE

The following pins have the same function as their counterparts on the Am29000 and are designed to be connected directly to
the Am29000 Synchronous Channel Interface

Description

A0-31

Address Bus (Input)

The address bus transfers byte addresses for all accesses to the memory array except in

burst mode The NSBMC290 can be software configured to any memory block address within the 4 Gbyte
address range

BINV

Bus Invalid (Input Active Low)

This input indicates that the address bus and related control signals are invalid

This signal must be 0 (high) in order for the NSBMC290 to accept any data or instruction requests

READ

WRITE (Input)

This input indicates whether data is being transferred to the data bus (R

high) or to

the memory array (R

low)

DBACK

Data Burst Acknowledge (Output 3-State Active Low)

This output signals that burst mode accesses between

the memory array and the data bus can be continued

DBREQ

Data Burst Request (Input Active Low)

This input is used to indicate when burst mode access for data is

desired

DRDY

Data Ready (Output 3-State Active Low)

This output is used to signal the completion of a data access cycle

DREQ

Data Request (Input Active Low)

This input signal the initiation of a memory access cycle for data

DREQT0 1

Data Request Type (Input Active Low)

These inputs specify the address space of the data access They must

both be 0 (low) in order for the NSBMC290 to accept a data request

OPT0 2

Data Options (Input Active Low)

These inputs specify the data transfer size and operating mode The

NSBMC290 responds only to cycles in which the values 0 1 2 are asserted The use of these signals is
compatible with the specifications for In-Circuit Emulators

PDA

Pipelined Data Access (Input Active Low)

This input indicates that the address bus has the address for the

next data access prior to the completion of the present data request

IBACK

Instruction Burst Acknowledge (Output 3-State Active Low)

This output signals that burst mode accesses

between the memory array and the instruction bus can be continued

IBREQ

Instruction Burst Request (Input Active Low)

This input is used to request burst mode instruction access

IRDY

Instruction Ready (Output 3-state Active Low)

This output signals are completion of each instruction access

IREQ

Instruction Request (Input Active Low)

This input signals the beginning of an instruction access cycle

IREQT

Instruction Request Type (Input Active High)

This input specifies the address space of the instruction access

It must be 0 (low) in order for the NSBMC290 to accept an instruction request

PIA

Pipelined Instruction Access (input Active Low)

This input indicates that the address bus has the address for

the next instruction access prior to the completion of the present instruction request

PEN

Pipeline Enable (Output 3-State Active Low)

This output indicates that the NSBMC290 is capable of

accepting the address for the next access before completion of the present access

RESET

Reset (Input Active Low)

This input initializes the NSBMC290 to accept the software configuration information

If more than one NSBMC290 is used for controlling memory the NSBMC290 chips should be daisy chained with
RSTOUT

from one NSBMC290 chip connecting to RESET of the next NSBMC290 Chip

RSTOUT

Reset Out (Output Active Low)

This output is active (low) whenever RESET is active and remains active until

the NSBMC290 has been software configured

SYSCLK

System Clock (Input)

This input is used to synchronize the NSBMC290 to the Am29000 local channel interface

Pin Descriptions

(Continued)

MEMORY INTERFACE

The NSBMC290 is designed to drive a memory array orga-
nized as 2 banks each of 32 bits The address and control
signals for the memory array are output through high current

drivers in order to minimize the propagation delay due to
memory input impedance and trace capacitance External
array drivers are not required The address and control sig-
nals however must be externally terminated

Description

A(A B)0 10

Multiplexed Addresses (Output High Current)

These two buses transfer the multiplexed row and column

addresses to the memory array banks A and B respectively

RAS(A B)

Row Address Strobes (Output High Current Active Low)

These signals are strobes that indicate the

existence of a valid row address on A(A B)0 10 These signals are to be connected to the two interleaved banks
of memory One is assigned to each bank

CAS(A B)0-3

Column Address Strobe (Output High Current Active Low)

These signals are strobes that indicate a valid

column address on A(A B)0 10 A set of each of these (A B) are assigned to each memory bank and within each
set one is assigned to each byte of the 32-bit memory

MWE(A B)

Memory Write Enable (Output High Current Active Low)

These signals are the write strobes for the DRAM

memories One is supplied for each of the two banks of memory although they are logically identical

BUFFER CONTROLS

In order not to limit system implementation strategies vis

vis instruction and data bus organization the NSBMC290
permits the designer to keep these busses separate or not

as performance criteria dictate In order to maintain bus
separation data buffers are required In order to maximize
performance these buffers are controlled directly by the
NSBMC290

Description

DBLE(A B)

Data Bus Latch Enable A and B (Output Active High)

These outputs are used to enable transparent latches to

latch data from the Processor data bus to each bank of memory during a write cycle (Data access only)

The following buffer control outputs are multi-mode signals The signal names as they appear on the logic symbol
are the default signal names (Mode

0) A more complete description is presented in the configuration section

DBTX(A B)

Data Bus Transmit A and B (Output Active Low)

These outputs are used during read cycles to enable data

from the individual banks of memory to drive the data bus

IBTX(A B)

Instruction Bus Transmit A and B (Output Active Low)

These outputs are used during instruction cycles to

enable data from the individual banks of memory to drive the instruction bus

Part Number NSBMC290-16