TL EE 5117
NS32202-10
Interrupt
Control
Unit
July 1991
NS32202-10 Interrupt Control Unit
General Description
The NS32202 Interrupt Control Unit (ICU) is the interrupt
controller for the Series 32000
microprocessor family It is
a support circuit that minimizes the software and real-time
overhead required to handle multi-level prioritized inter-
rupts A single NS32202 manages up to 16 interrupt sources
resolves interrupt priorities and supplies a single-byte interrupt
vector to the CPU
The NS32202 can operate in either of two data bus modes
16-bit or 8-bit In the 16-bit mode eight hardware and eight
software interrupt positions are available In the 8-bit mode
16 hardware interrupt positions are available 8 of which can
be used as software interrupts In this mode up to 16 addi-
tional ICUs may be cascaded to handle a maximum of 256
interrupts
Two 16-bit counters which may be concatenated under pro-
gram control into a single 32-bit counter are also available
for real-time applications
Features
Y
16 maskable interrupt sources cascadable to 256
Y
Programmable 8- or 16-bit data bus mode
Y
Edge or level triggering for each hardware interrupt with
individually selectable polarities
Y
8 software interrupts
Y
Fixed or rotating priority modes
Y
Two 16-bit DC to 10 MHz counters that may be con-
catenated into a single 32-bit counter
Y
Optional 8-bit I O port available in 8-bit data bus mode
Y
High-speed XMOS
TM
technology
Y
Single
a
5V supply
Y
40-pin dual in-line package
Basic System Configuration
TL EE 5117 1
Series 32000
is a registered trademark of National Semiconductor Corp
XMOS
TM
is a trademark of National Semiconductor Corp
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Table of Contents
1 0 PRODUCT INTRODUCTION
1 1 I O Buffers
1 2 Read Write Logic and Decoders
1 3 Timing and Control
1 4 Priority Control
1 5 Counters
2 0 FUNCTIONAL DESCRIPTION
2 1 Reset
2 2 Initialization
2 3 Vectored Interrupt Handling
2 3 1 Non-Cascaded Operation
2 3 2 Cascade Operation
2 4 Internal ICU Operating Sequence
2 5 Interrupt Priority Modes
2 5 1 Fixed Priority Mode
2 5 2 Auto-Rotate Mode
2 5 3 Special Mask Mode
2 5 4 Polling Mode
3 0 ARCHITECTURAL DESCRIPTION
3 1 HVCT - Hardware Vector Register (R0)
3 2 SVCT - Software Vector Register (R1)
3 3 ELTG - Edge Level Triggering Registers (R2 R3)
3 4 TPL - Triggering Polarity Registers (R4 R5)
3 5 IPND - Interrupt Pending Registers (R6 R7)
3 6 ISRV - Interrupt In-Service Registers (R8 R9)
3 7 IMSK - Interrupt Mask Registers (R10 R11)
3 8 CSRC - Cascaded Source Registers (R12 R13)
3 0 ARCHITECTURAL DESCRIPTION
(Continued)
3 9 FPRT - First Priority Registers (R14 R15)
3 10 MCTL - Mode Control Register (R16)
3 11 OSCASN - Output Clock Assignment (R17)
3 12 CIPTR - Counter Interrupt Pointer Register (R18)
3 13 PDAT - Port Dada Register (R19)
3 14 IPS - Interrupt Port Select Register (R20)
3 15 PDIR - Port Direction Register (R21)
3 16 CCTL - Counter Control Register (R22)
3 17 CICTL - Counter Interrupt Control Register (R23)
3 18 LCSV HCSV - L-Counter Starting Value H-Counter
Starting Value Registers (R24 R25 R26 and R27)
3 19 LCCV HCCV - L-Counter Current Value H-Counter
Current Value Registers (R28 R29 R30 and R31)
3 20 Register Initialization
4 0 DEVICE SPECIFICATIONS
4 1 NS32202 Pin Descriptions
4 1 1 Power Supply
4 1 2 Input Signals
4 1 3 Output Signals
4 1 4 Input Output Signals
4 2 Absolute Maximum Ratings
4 3 Electrical Characteristics
4 4 Switching Characteristics
4 4 1 Definitions
4 4 1 1 Timing Tables
4 4 1 2 Timing Diagrams
List of Illustrations
NS32202 ICU Block Diagram
1-1
Counter Output Signals in Pulsed Form and Square Waveform for Three Different Initial Values
1-2
Counter Configuration and Basic Operations
1-3
Interrupt Control Unit Connections in 16-Bit Bus Mode
2-1
Interrupt Control Unit Connections in 8-Bit Bus Mode
2-2
Cascaded Interrupt Control Unit Connections in 8-Bit Bus Mode
2-3
CPU Interrupt Acknowledge Sequence
2-4
Interrupt Dispatch and Cascade Tables
2-5
CPU Return from Interrupt Sequence
2-6
ICU Interrupt Acknowledge Sequence
2-7
ICU Return from Interrupt Sequence
2-8
ICU Internal Registers
3-1
HVCT Register Data Coding
3-2
Recommended ICU's Initialization Sequence
3-3
NS32202 ICU Connection Diagram
4-1
Timing Specification Standard
4-2
READ INTA Cycle
4-3
Write Cycle
4-4
Interrupt Timing in Edge Triggering Mode
4-5
Interrupt Timing in Level Triggering Mode
4-6
External Interrupt-Sampling-Clock to be Provided at Pin COUT SCIN When in Test Mode
4-7
Internal Interrupt-Sampling-Clock to be Provided at Pin COUT SCIN
4-8
Relationship Between Clock Input at Pin CLK and Counter Output Signals at Pins COUT SCIN or G0 R0 G3 R6
in Both Pulsed Form and Square Waveform
4-9
2
1 0 Product Introduction
The NS32202 ICU functions as an overall manager in an
interrupt-oriented system environment Its many features
and options permit the design of sophisticated interrupt sys-
tems
Figure 1 1 shows the internal organization of the NS32202
As shown the NS32202 is divided into five functional
blocks These are described in the following paragraphs
1 1 I O BUFFERS AND LATCHES
The I O Buffers and Latches block is the interface with the
system data bus It contains bidirectional buffers for the
data I O pins It also contains registers and logic circuits
that control the operation of pins G0 IR0
G7 IR14
when the ICU is in the 8-bit bus mode
1 2 READ WRITE LOGIC AND DECODERS
The Read Write Logic and Decoders manage all internal
and external data transfers for the ICU These include Data
Control and Status Transfers This circuit accepts inputs
from the CPU address and control buses In turn it issues
commands to access the internal registers of the ICU
1 3 TIMING AND CONTROL
The Timing and Control Block contains status elements that
select the ICU operating mode It also contains state ma-
chines that generate all the necessary sequencing and con-
trol signals
1 4 PRIORITY CONTROL
The Priority Control Block contains 16 units one for each
interrupt position These units provide the following func-
tions
Sensing the various forms of hardware interrupt sig-
nals e g level (high low) or edge (rising falling)
Resolving priorities and generating an interrupt re-
quest to the CPU
Handling cascaded arrangements
Enabling software interrupts
Providing for an automatic return from interrupt
Enabling the assignment of any interrupt position to
the internal counters
Providing for rearrangement of priorities by assigning
the first priority to any interrupt position
Enabling automatic rotation of priorities
1 5 COUNTERS
This block contains two 16-bit counters called the H-coun-
ter and the L-counter These are down counters that count
from an initial value to zero Both counters have a 16-bit
register (designated HCSV and LCSV) for loading their re-
starting values They also have registers containing the cur-
rent count values (HCCV and LCCV) Both sets of registers
are fully described in Section 3
TL EE 5117 2
FIGURE 1 1 NS32202 ICU Block Diagram
3
1 0 Product Introduction
(Continued)
The counters are under program control and can be used to
generate interrupts When the count reaches zero either
counter can generate an interrupt request to any of the 16
interrupt positions The counter then reloads the start value
from the appropriate registers and resumes counting
Figure
1 2 shows typical counter output signals available from the
NS32202
The maximum input clock frequency is 2 5 MHz
A divide-by-four prescaler is also provided When the pre-
scaler is used the input clock frequency can be up to 10
MHz
When intervals longer than provided by a 16-bit counter are
needed the L- and H-counters can be concatenated to form
a 32-bit counter In this case both counters are controlled
by the H-counter control bits Refer to the discussion of the
Counter Control Register in Section 3 for additional informa-
tion
Figure 1-3 summarizes counter read write operations
2 0 Functional Description
2 1 RESET
The ICU is reset when a logic low signal is present on the
RST pin At reset most internal ICU registers are affected
and the ICU becomes inactive
2 2 INITIALIZATION
After reset the CPU must initialize the NS32202 to establish
its configuration Proper initialization requires knowledge of
the ICU register's formats Therefore a flowchart of a rec-
ommended initialization sequence is shown in (
Figure 3 3 )
after the discussion of the ICU registers
The operation sequence shown in
Figure 3 3 ensures that
all counter output pins remain inactive until the counters are
completely initialized
2 3 VECTORED INTERRUPT HANDLING
For details on the operation of the vectored interrupt mode
for a particular Series 32000 CPU refer to the data sheet for
TL EE 5117 4
FIGURE 1 2 Counter Output Signals in Pulsed Form and Square Waveform for Three Different Initial Values
4
2 0 Functional Description
(Continued)
that CPU In this discussion it is assumed that the NS32202
is working with a CPU in the vectored interrupt mode Sever-
al ICU applications are discussed including non-cascaded
and cascaded operation
Figures 2 1 2 2 and 2 3 show
typical configurations of the ICU used with the NS32016
CPU
A peripheral device issues an interrupt request by sending
the proper signal to one of the NS32202 interrupt inputs If
the interrupt input is not masked the ICU activates its Inter-
rupt Output (INT) pin and generates an interrupt vector byte
The interrupt vector byte identifies the interrupt source in its
four least significant bits When the CPU detects a low level
on its Interrupt Input pin it performs one or two interrupt
acknowledge cycles depending on whether the interrupt re-
quest is from the master ICU or a cascaded ICU
Figure 2 4
shows a flowchart of a typical CPU Interrupt Acknowledge
sequence
TL EE 5117 5
BASIC OPERATIONS
WRITING TO LCSV HCSV
A
f
w
(IDB)
READING LCSV HCSV
A
f
x
(IDB)
WRITING TO LCCV HCCV
B
f
w
(IDB)
(only possible when counters are halted)
C
f
w
(IDB)
READING LCCV HCCV
C
f
x
(IDB)
(only possible when counter
readings are frozen)
COUNTER COUNTS AND READINGS ARE
NOT FROZEN
C
f
w
B
f
COUNTER RELOADS STARTING VALUE
B
f
w
A
f
(occurs on the clock cycle following
the one in which it reaches zero)
FIGURE 1 3 Counter Configuration and Basic Operations
5
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