TL F 5914
MM54C910MM74C910
256
Bit
TRI-STATE
Random
Access
ReadWrite
Memory
September 1989
MM54C910 MM74C910 256 Bit TRI-STATE
Random Access Read Write Memory
General Description
The MM54C910 MM74C910 is a 64 word by 4-bit random
access memory Inputs consist of six address lines four
data input lines a WE and a ME line The six address lines
are internally decoded to select one of the 64 word loca-
tions An internal address register latches the address infor-
mation on the positive to negative transition of ME The
TRI-STATE outputs allow for easy memory expansion
Address Operation
Address inputs must be stable (t
SA
)
prior to the positive to negative transition of ME and (t
HA
)
after the positive to negative transition of ME The address
register holds the information and stable address inputs are
not needed at any other time
Write Operation
Data is written into memory at the select-
ed address if WE goes low while ME is low WE must be
held low for t
WE
and data must remain stable t
HD
after WE
returns high
Read Operation
Data is nondestructively read from a
memory location by an address operation with WE held
high
Outputs are in the TRI-STATE (Hi-Z) condition when the
device is writing or disabled
Features
Y
Supply voltage range
3 0V to 5 5V
Y
High noise immunity
0 45V
CC
(typ )
Y
TTL compatible fan out
1 TTL load
Y
Input address register
Y
Low power consumption
250 nW package (typ )
(chip enabled or disabled)
Y
Fast access time
250 ns (typ ) at 5 0V
Y
TRI-STATE outputs
Y
High voltage inputs
Logic Diagrams
TL F 5914 1
Input Protection
TL F 5914 2
TRI-STATE
is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Voltage at Any Output Pin
b
0 3V to V
CC
a
0 3V
Voltage at Any Input Pin
b
0 3V to
a
15V
Power Dissipation
Dual-In-Line
700 mW
Small Outline
500 mW
Operating V
CC
Range
3 0V to 5 5V
Standby V
CC
Range
1 5V to 5 5V
Absolute Maximum (V
CC
)
6 0V
Lead Temperature (T
L
)
(Soldering 10 sec )
260 C
Operating Conditions
Min
Max
Units
Supply Voltage (V
CC
)
MM54C910
4 5
5 5
V
MM74C910
4 75
5 25
V
Temperature (T
A
)
MM54C910
b
55
a
125
C
MM74C910
b
40
a
85
C
DC Electrical Characteristics
Min Max limits apply accross the temperature and power supply range indicated
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
IN(1)
Logical ``1'' Input Voltage
Full Range
V
CC
b
1 5
V
V
IN(0)
Logical ``0'' Input Voltage
Full Range
0 8
V
I
IN(1)
Logical ``1'' Input Current
V
IN
e
15V
0 005
2 0
m
A
V
IN
e
5V
0 005
1 0
m
A
I
IN(0)
Logical ``0'' Input Current
V
IN
e
0V
b
1 0
b
0 005
m
A
V
OUT(1)
Logical ``1'' Output Voltage
I
O
e b
150 mA
V
CC
b
0 5
V
I
O
e b
400 mA
2 4
V
V
OUT(0)
Logical ``0'' Output Voltage
I
O
e
1 6 mA
0 4
V
I
OZ
Output Current in High
V
O
e
5V
0 005
1 0
m
A
Impedance State
V
O
e
0V
b
1 0
b
0 005
m
A
I
CC
Supply Current
V
CC
e
5V
5 0
300
m
A
AC Electrical Characteristics
T
A
e
25 C V
CC
e
5 0V C
L
e
50 pF
Symbol
Parameter
Min
Typ
Max
Units
t
ACC
Access Time from Address
250
500
ns
t
pd
Propagation Delay from ME
180
360
ns
t
SA
Address Input Set-Up Time
140
70
ns
t
HA
Address Input Hold Time
20
10
ns
t
ME
Memory Enable Pulse Width
200
100
ns
t
ME
Memory Enable Pulse Width
400
200
ns
t
SD
Data Input Set-Up Time
0
ns
t
HD
Data Input Hold Time
30
15
ns
t
WE
Write Enable Pulse Width
140
70
ns
t
1H
t
0H
Delay to TRI-STATE (Note 4)
100
200
ns
CAPACITANCE
C
IN
Input Capacity
5 0
pF
Any Input (Note 2)
C
OUT
Output Capacity
9 0
pF
Any Output (Note 2)
C
PD
Power Dissipation Capacity
350
pF
(Note 3)
2
AC Electrical Characteristics
(Continued)T
A
e
25 C V
CC
e
5 0V C
L
e
50 pF
MM54C910
MM74C910
T
A
e b
55 C to
a
125 C
T
A
e b
40 C to
a
85 C
Symbol
Parameter
V
CC
e
4 5V to 5 5V
V
CC
e
4 75V to 5 25V
Units
Min
Max
Min
Max
t
ACC
Access Time from Address
860
700
ns
t
pd1
t
pd0
Propagation Delay from ME
660
540
ns
t
SA
Address Input Set-Up Time
200
160
ns
t
HA
Address Input Hold Time
20
20
ns
t
ME
Memory Enable Pulse Width
280
260
ns
t
ME
Memory Enable Pulse Width
750
600
ns
t
SD
Data Input Set-Up Time
0
0
ns
t
HD
Data Input Hold Time
50
50
ns
t
WE
Write Enable Pulse Width
200
180
ns
t
1H
t
0H
Delay to TRI-STATE (Note 4)
200
200
ns
AC Parameters are guaranteed by DC correlated testing
Note 1
``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed Except for ``Operating Temperature Range''
they are not meant to imply that the devices should be operated at these limits The table of ``Electrical Characteristics'' provides conditions for actual device
operation
Note 2
Capacitance is guaranteed by periodic testing
Note 3
C
PD
determines the no load AC power consumption for any CMOS device For complete explanation see 54C 74C Family Characteristics application note
AN-90
Note 4
See AC test circuits for t
1H
t
0H
Typical Performance Characteristics
Typical Access Time vs
Ambient Temperature
TL F 5914 4
Truth Table
ME
WE
Operation
Outputs
L
L
Write
TRI-STATE
L
H
Read
Data
H
L
Inhibit Store
TRI-STATE
H
H
Inhibit Store
TRI-STATE
AC Test Circuits
t
0H
TL F 5914 5
t
1H
TL F 5914 6
3
AC Test Circuits
(Continued)
All Other AC Tests
TL F 5914 7
Switching Time Waveforms
Read Cycle
(See Note 1)
TL F 5914 8
Write Cycle
(See Note 1)
TL F 5914 9
4
Switching Time Waveforms
(Continued)
Read Modify Write Cycle
(See Note 1)
TL F 5914 10
t
0H
TL F 5914 11
t
1H
TL F 5914 12
Note 1
MEMORY ENABLE must be brought high for t
ME
nanoseconds between every address change
Note 2
t
r
e
t
f
e
20 ns for all inputs
Connection Diagram
Dual-In-Line Package
TL F 5914 3
Top View
Order Number MM54C910 or MM74C910
5
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