TL Z 12436
MCM28F256ACH
256-Mbit
(32-Mbit
x
8
16-Mbit
x
16)
Flash
Memory
Module
with
Internal
Decoding
and
Boundary
Scan
IO
Buffers
PRELIMINARY
July 1995
MCM28F256ACH
256-Mbit (32-Mbit x 8 16-Mbit x 16) Flash Memory Module
with Internal Decoding and Boundary Scan I O Buffers
General Description
The MCM28F256ACH is a 268 435 456-bit flash memory
module organized as 16 pages with 16 777 216 bytes
(8 388 608 words) per page Utilizing Intel's FlashFile
TM
Memory
and
National's
SCAN
TM
I O
buffers
the
MCM28F256ACH offers several revolutionary features in-
cluding a user-configurable x8 x16 architecture selective
block locking on-board write buffers pipelined command
execution and boundary scan test capability Several power
reduction features are also incorporated including Automat-
ic Power Savings (APS) which puts the module into a low
current state when it is being accessed by a slowed or
stopped CPU
The MCM28F256ACH includes sixteen 28F016SA flash
memories decoding logic and IEEE 1149 1 compliant I O
buffers The module is offered in a 68-lead hermetic pack-
age Both through-hole and surface mount lead configura-
tions are available
Features
Y
Read access time of 140 ns over the industrial temper-
ature range (160 ns over the military temperature
range)
Y
Utilizes Intel's FlashFile architecture with 512 indepen-
dently lockable blocks (16 pages with 32 blocks per
page)
Y
Choice of x8 or x16 architecture (user-configurable)
Y
Pipelined command execution
Y
Automated write and erase capability can be executed
simultaneously in all 16 pages greatly improving aver-
age write erase cycle times
Y
National's lEEE 1149 1 compliant SCAN I O buffers
simplify the integration of design and test
Y
TTL compatible inputs
Y
Low noise TRl-STATE
outputs drive 50X transmission
line to TTL levels (75X transmission line over military
temperature range)
Y
Hermetically sealed integral substrate package
Y
DIP and surface mount packaging available
Connection Diagram
TL Z 12436 1
Pin
Description
Names
A
0
Byte-Select Address Input
A
1
A
24
Word-Select Address Inputs
DQ
0
DQ
7
Low-Byte Data I O Bus
DQ
8
DQ
15
High-Byte Data I O Bus
CE
Chip Enable Input (Active LOW)
RP
Reset Power-Down Input (Active LOW)
OE
Output Enable Input (Active LOW)
WE
Write Enable Input (Active LOW)
RY BY
Ready Busy Output
WP
Write Protect Input (Active LOW)
BYTE
Byte Enable Input (Active LOW)
V
PP
Erase Write Power Supply
V
CC
Device Power Supply
GND
Ground
NC
No Connection
TRI-STATE
is a registered trademark of National Semiconductor Corporation
SCAN
TM
is a trademark of National Semiconductor Corporation
FlashFile
TM
is a trademark of Intel Corporation
C1995 National Semiconductor Corporation
RRD-B30M115 Printed in U S A
Block Diagram
TL Z 12436 2
Functional Description
The MCM28F256ACH is a 268 435 456-bit (256-Mbit) flash
memory module organized as 16 pages with 16 777 216
bytes (8 388 608 words) per page The module is segment-
ed into 512 independently lockable blocks (32 blocks per
page)
A Command User Interface (CUI) serves as the interface
between the system controller and each page of internal
memory Automation of the byte word write and block erase
functions allow these commands to be executed using a
two-write command sequence to the CUI An internal Write
State Machine (WSM) automatically executes the algo-
rithms timings and verifications necessary for the write and
erase operations thereby relieving the system controller of
these tasks
Each page of memory has three types of status registers
and a RY BY output to provide information on the progress
of the requested operation The Compatible Status Register
(CSR) is 100% compatible with status register used in previ-
ous FlashFile memory devices The Global Status Register
(GSR) informs the system of command queue status sector
buffer status and WSM status Block Status Registers (BSR)
provide block-specific status information such as the block
lock bit status A choice of four different RY BY configura-
tions can be selected via special CUI commands level-
mode (default) pulse-on-write pulse-on-erase or disabled
2
Functional Description
(Continued)
Memory data is written in byte word increments typically
within 6 ms Each page of memory incorporates two sector
buffers of 256 bytes (128-words) which allow sector data
writes at SRAM speeds Writes from sector buffers to the
flash array can be initiated with a single command and will
complete independently freeing the system controller for
other tasks
Any one of the 512 blocks can be erased typically within 0 6
seconds without affecting the contents of the remaining
blocks Write and erase operations can be executed simul-
taneously in all 16 pages greatly improving average write
erase cycle times
A write protection scheme has been incorporated that pro-
vides maximum flexibility for selecting which blocks can be
modified by the end user A non-volatile lock bit is assigned
to each block and is used in conjunction with the master
write protect input (WP) With WP at logic low block locking
capability is invoked and the WSM is notified if a requested
write or erase operation is not allowed With WP at logic
high the status of all lock bits is overridden allowing write
or erase operations in any block
The MCM28F256ACH reduces system overhead by allow-
ing a subset of commands to be pipelined to the CUI on
each page of memory Ordinarily the command queue is 3-
commands deep However if only single block erase com-
mands are queued the queue becomes virtually 32-com-
mands deep
Commands in the queue are prioritized In order to capture
data as it arrives in real time write commands are executed
before erase commands regardless of the command order
Also multiple erase commands are queued in conjunction
with write commands If the CUI receives a write command
affecting a block which is in queue to be erased it will priori-
tize that block erase command ahead of other erase opera-
tions allowing the complete block modification to occur as
quickly as possible
The BYTE input allows either x8 or x16 read writes to the
MCM28F256ACH With BYTE at logic low the device oper-
ates in the 8-bit mode Address A
0
selects either the low or
high byte and the high-byte data bus (DQ
8
DQ
15
) floats to
TRI-STATE With BYTE at logic high the device is in the 16-
bit mode of operation In this case A
1
becomes the lowest
order address A
0
is not used (don't care) and data is input
and output on all 16 bits of the data bus (DQ
0
DQ
15
)
The MCM28F256ACH offers several low power modes of
operation Standby mode is entered when the module is
deselected (CE at logic high) The typical I
CC
current draw in
this mode is 20 mA If a WSM is processing a command
when the module is deselected the operation continues
and power consumption remains at the non-standby level
until the command has completed
With RP at logic low enters deep power-down mode The
typical I
CC
current draw in this mode is 4 mA Bringing RP
low interrupts any current or pending commands and resets
all status registers CUI and WSM The contents of any
memory location being written or block being erased will no
longer be valid
The Sleep command puts a page of memory in sleep mode
which reduces the power consumption for that page of
memory to deep power-down levels The sleep command
allows any current or pending commands to execute before
going into sleep mode
Automatic Power Savings (APS) is a feature which puts the
module into a low current state when it is being accessed by
a slowed or stopped CPU After data is read from the mem-
ory array power reduction control circuitry reduces the typi-
cal I
CC
current draw to 20 mA until a new memory location
is accessed
To get the lowest possible power consumption in all modes
input pins should be held at V
CC
or GND (CMOS levels)
rather than V
IH
or V
IL
(TTL levels)
For detailed information regarding the operation of the
28F016SA FlashFile Memory refer to the Intel data sheet
(order number 290489) and user's manual (order number
297372)
3
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Device Power Supply Voltage (V
CC
)
b
0 2V to
a
7 0V
Erase Write Power Supply Voltage (V
PP
)
b
0 2V to
a
14 0V
DC Input Diode Current (I
IK
)
V
IN
e b
0 5V
b
20 mA
V
IN
e
V
CC
a
0 5V
a
20 mA
DC Output Diode Current (I
OK
)
V
OUT
e b
0 5V
b
20 mA
V
OUT
e
V
CC
a
0 5V
a
20 mA
DC Output Voltage (V
OUT
)
b
0 5V to V
CC
a
0 5V
DC Output Source Sink Current (I
OUT
)
g
70 mA
DC V
CC
or Ground Current
Per Output Pin (I
CC
or I
GND
)
g
70 mA
Thermal Resistance Junction to Case (i
JC
)
5 C W
Junction Temperature (T
J
)
a
150 C
Storage Temperature (T
STG
)
b
65 C to
a
150 C
Note 1
Absolute maximum ratings are those values beyond which damage
to the device may occur The databook specifications should be met without
exception to ensure that the system design is reliable over its power supply
temperature and output input loading variables National does not recom-
mend operation of this module outside the datasheet specifications
Recommended Operating
Conditions
Device Power Supply Voltage (V
CC
)
4 5V to 5 5V
Erase Write Power Supply Voltage (V
PP
) (Note 2)
Read-Only Operations (V
PPL
)
0 0V to 6 5V
Erase Write Operations (V
PPH
)
11 4V to 12 6V
Input Voltage (V
IN
)
0V to V
CC
Output Voltage (V
OUT
)
0V to V
CC
Case Operating Temperature (T
C
)
Industrial
b
45 C to
a
85 C
Military
b
55 C to
a
125 C
Minimum Input Edge Rate (dV dt)
125 mV ns
V
IN
from 0 8V to 2 0V
V
CC
4 5V 5 5V
Maximum Static Output Current
High Level (I
OH
)
b
32 mA
Low Level (I
OL
)
a
64 mA
Note 2
Erase and write operations are inhibited when V
PP
e
V
PPL
and not
guaranteed In the range betveeen V
PPL
and V
PPH
DC Electrical Characteristics
Military
Industrial
Symbol
Parameter
Conditions
T
C
e b
55 C to
a
125 C T
C
e b
45 C to
a
85 C Units
V
CC
e
4 5V to 5 5V
V
CC
e
4 5V to 5 5V
V
IH
Minimum High Input Voltage
2 0
2 0
V
V
IL
Maximum Low Input Voltage
0 8
0 8
V
I
IH
Maximum High Input Current
V
IN
e
V
CC
1 0
1 0
m
A
All inputs except TCK TDI TMS
V
IN
e
V
CC
15 0
15 0
m
A
TCK TDI TMS Inputs
I
IL
Maximum Low Input Current
V
IN
e
GND
b
1 0
b
1 0
m
A
All inputs except TCK TDI TMS
V
IN
e
GND
b
1 2
b
1 2
mA
TCK TDI TMS Inputs
I
OZT
Maximum I O Leakage Current V
I O
e
V
CC
or GND
g
15 0
g
10 0
m
A
V
OH
Minimum High Output Voltage
I
OUT
e b
50 mA
V
CC
b
1 35
V
CC
b
1 35
I
OUT
e b
32 mA
2 4
V
I
OUT
e b
24 mA
2 4
V
OL
Maximum Low Output Voltage
I
OUT
e
50 mA
0 1
0 1
I
OUT
e
64 mA
0 55
V
I
OUT
e
48 mA
0 55
I
OLD
Minimum Dynamic
V
OLD
e
0 8 V
Max
63
94
mA
I
OHD
Output Current
V
OHD
e
2 0 V
Min
b
27
b
40
I
OS
Minimum Output Short
V
OUT
e
0V
b
100
b
100
mA
Circuit Current
I
CCT
Maximum V
CC
Current
V
IN
e
V
CC
b
2 1V
2 0
2 0
mA
per Input at TTL HIGH
All inputs except TCK TDI TMS
I
CCS
Maximum V
CC
Standby
CE
e
RP
e
V
CC
25
25
mA
Current
Maximum test duration 2 0 ms one output loaded at a time
4
DC Electrical Characteristics
(Continued)
Symbol
Parameter
Conditions
Military
Industrial
Units
T
C
e b
55 C
T
C
e b
45 C
to
a
125 C
to
a
85 C
V
CC
e
4 5V to 5 5V
V
CC
e
4 5V to 5 5V
I
CCD
Maximum V
CC
Deep
RP
e
GND
5
5
mA
Power Down Current
TDI
e
TMS
e
V
CC
I
CCR
Maximum V
CC
Read Current
f
e
5 MHz I
OUT
e
0 mA
120
120
mA
I
CCW
Maximum V
CC
Write Current
Single Write Operation
70
70
mA
16 Simultaneous Write
650
650
mA
Operations
I
CCE
Maximum V
CC
Block
Single Erase Operation
60
60
mA
Erase Current
16 Simultaneous Erase Operations
480
480
I
CCES
Maximum V
CC
Erase
Single Erase Operation Suspended
45
45
mA
Suspend Current
16 Erase Operations
220
220
Simultaneously Suspended
I
PPS
Maximum V
PP
Standby Current
V
PP
t
V
CC
1
1
mA
I
PPD
Maximum V
PP
Deep
RP
e
GND
1
1
mA
Power Down Current
I
PPR
Maximum V
PP
Read Current
V
PP
e
V
PPH
5
5
mA
I
PPW
Maximum V
PP
Byte
Single Write Operation
18
18
mA
Write Current
16 Simultaneous Write Operations
290
290
I
PPE
Maximum V
PP
Block
Single Erase Operation
15
15
mA
Erase Current
16 Simultaneous Erase Operations
240
240
I
PPES
Maximum V
PP
Erase
1 16 Erase Operations
5
5
mA
Suspend Current
Suspended
Maximum test duration 2 0 ms one output loaded at a time
AC Electrical Characteristics
Read Operations
Military
Industrial
Symbol
Parameter
T
C
e b
55 C to
a
125 C
T
C
e b
45 C to
a
85 C
Units
V
CC
e
4 5V to 5 5V
V
CC
e
4 5V to 5 5V
Min
Max
Min
Max
t
AVAV
Read Cycle Time (No Page Change)
160
140
ns
Read Cycle Time (With Page Change)
180
160
t
AVEL
Address Setup to CE Going Low
20
15
ns
t
AVGL
Address Setup to OE Going Low
0
0
ns
t
AVQV
Address A
0
A
20
to Output Delay
160
140
ns
Address A
21
A
24
to Output Delay
180
160
t
ELQV
CE to Output Delay
200
180
ns
t
PHQV
RP to Output Delay
800
700
ns
t
GLQV
OE to Output Delay
80
70
ns
t
ELQX
CE to Output Low Z
0
0
ns
t
EHQZ
CE to Output High Z
50
40
ns
t
GLQX
OE to Output Low Z
0
0
ns
t
GHQZ
OE to Output High Z
70
60
ns
5
PDF 
ZIP