1
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General Description
The LM9833 is a complete USB image scanner system on a sin-
gle IC. The LM9833 provides all the functions (image sensor
control, illumination control, analog front end, pixel processing
function image data buffer/DRAM controller, microstepping
motor controller, and USB interface) necessary to create a high
performance color scanner. The LM9833 scans images in 48 bit
color/16 bit gray, and has output data formats for 48 and 24bit
color/16 and 8 bit gray. The LM9833 supports sensors with pixel
counts of up to 16384 pixels x 3 colors (1200 dpi x 13.6 inches).
The LM9833's low operating and suspend mode supply currents
allow design of USB bus-powered scanners. The only additional
active components required are an external 4Mbit or 16Mbit
DRAM for data buffering and power transistors for the stepper
motor.
Applications
·
Color Flatbed Document Scanners
·
Color Sheetfed Document Scanners
Key Specifications
·
Analog to Digital Converter Resolution
16 Bits
·
Maximum Pixel Conversion Rate
6MHz
·
A4 Color 150dpi scan time
<10 seconds
·
A4 Color 300dpi scan time
<40 seconds
·
A4 Color 600dpi scan time
<160 seconds
·
Supply Voltage
- LM9833
+4.75V to +5.25V
- LM9833 DRAM I/O
+2.85 to +5.25V
·
Maximum Operating Current Consumption
136mA
·
Maximum Suspend Current Consumption
175µA
Features
· 16 bit ADC digitizes at up to 6Mpixels/s (2M RGB pixels/sec).
· Digital Pixel Processing provides 1200, 800, 600, 400, 300,
200, 150, and 100dpi horizontal resolution from a 1200dpi
sensor and 600, 400, 300, 200, 150, 100, 75, and 50dpi
horizontal resolution from a 600dpi sensor.
· Provides 50-2400dpi vertical resolution in 1 dpi increments.
· Pixel rate error correction for gain (shading) and offset errors.
· Supports 4 or 16Mbit external DRAMs.
· Multiple CCD clocking rates allows matching of CCD clock to
scan resolution and pixel depth for maximum scan speed.
· Stepper motor control tightly coupled with image data buffer
management to maximize data transfer efficiency.
· PWM stepper motor current control allows microstepping for
the price of fullstepping.
· USB interface for Plug and Play operation on USB-equipped
computers.
· Serial EEPROM option for custom Vendor and Product IDs.
· Support for USB bus-powered operation.
· Pixel depths of 1, 2, or 4 bits are packed into bytes for faster
scans of line art and low pixel depth images.
· Supports 3 channel CCDs and 1 channel CIS sensors.
· 3 (R, G, and B) 12-bit, user-programmable gamma correction
tables.
· Compatible with a wide range of color linear CCDs and
Contact Image Sensors (CIS).
· Operates with 48MHz external crystal.
· Internal bandgap voltage reference.
· 100 pin TQFP package
LM9833 48-Bit Color, 1200dpi USB Image Scanner
CCD/CIS
Illumination
+12V
Stepper
Motor
1-3
1-3
2-6
Power
Transistors
DRAM
30
LM9833CCVJD
USB
Port
2
48MHz Crystal
Serial
EEPROM
2
8
MISC
I/O
LM9833 Scanner System Block Diagram
Ordering Information
Commercial (0°C
T
A
+70°C)
Package
LM9833CCVJD
VJD100A 100 Pin Thin Quad Flatpac
LM9833
48-
B
i
t Co
l
o
r 1200
d
p
i
USB Im
age
Sc
ann
e
r
©2000 National Semiconductor Corporation
October 2001
2
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Connection Diagram
Ordering Information
Commercial (0°C
T
A
+70°C)
Package
LM9833CCVJD
VJD100A 100 Pin Thin Quad Flatpac
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
V
BANDGAP
V
REF LO
OS
R
V
REF MID
OS
G
V
REF HI
OS
B
AGND
V
A
A
A
B
B
D0
D15
V
DRAM
DGND
D1
D14
D2
D13
D3
D12
D4
D11
D5
D1
0
D6
D9
V
DR
A
M
DGND
D7
D8
CA
S
WR
RA
S
RD
A9
A8
A0
A7
A1
V
DR
A
M
DGND
A6
A2
A5
A3
A4
SDA
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
ø1
TR2
TR1
MISC I/O 6
MISC I/O 5
MISC I/O 4
DGND
V
D
MISC I/O 3
MISC I/O 2
MISC I/O 1
PAPER SENSE 1
PAPER SENSE 2
V
D
DGND
LAMP
B
LAMP
G
LAMP
R
DGND
V
D
24/48
CRYSTAL/EXT CLK
CRYSTAL IN
CRYSTAL OUT
SCL
AG
N
D
V
A
DG
ND
V
D
TEST
SENSEG
ND
SENSEA
SENSEB
NC
CM
ODE
RESET
NC
NC
DG
ND
V
D
BUS PO
WR
D+
D-
V
RE
G
U
L
A
T
O
R
DG
ND
ACTI
VE/
SUSP
ENDED
CP2
CP1
RS
ø2
LM9833CCVJD
LM
983
3
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Pin Descriptions
USB Interface
D+, D-
Digital I/O. USB Interface signals
BUS POWER
Digital Input. Tie low for bus powered sys-
tems, tie high for external power.
ACTIVE/
SUSPENDED
Digital Output. Low in Suspend mode. High in
operational mode. Used to control external
regulators, other components.
SDA
Digital I/O. Serial Data to/from external
EEPROM.
SCL
Digital Output. Serial Clock Output to external
EEPROM.
Analog
OS
R
,
OS
G
,
OS
B
Analog Inputs. These inputs (for Red, Green,
and Blue) should be tied to the sensor's out-
put signal through DC blocking capacitors. If
unused, tie to ground through DC blocking
capacitors.
V
REF LO
Analog Output/Input. Bypass to AGND with a
0.047µF monolithic capacitor. Do not put a
DC load on this pin.
V
REF MID
Analog Output/Input. Bypass to AGND with a
0.047µF monolithic capacitor. Do not put a
DC load on this pin.
V
REF HI
Analog Output/Input. Bypass to AGND with a
0.047µF monolithic capacitor. Do not put a
DC load on this pin.
V
BANDGAP
Analog Output. Bypass to AGND with a
0.047µF monolithic capacitor. Do not put a
DC load on this pin.
DRAM
D0 (LSB) -D15
(MSB)
Digital Inputs/Outputs. This is the 16 bit data
path between the external DRAM and the
LM9833.
RD
Digital Output. Read signal to external DRAM.
WR
Digital Output. Write signal to external DRAM.
A0-A9
Digital Outputs. Address pins for up to 1M x
16 external DRAM.
RAS
Digital Output. Row Address Strobe signal.
CAS
Digital Output. Column Address Strobe sig-
nal.
Scanner Support I/O
PAPER
SENSE 1-2
Digital Inputs. Programmable, used for sens-
ing home position, paper, front panel
switches, etc.
MISC I/O 1-6
Digital Inputs/Outputs. Programmable, used
for front panel switches, status LEDs, etc. At
power-on and in Suspend Mode, MISC I/Os
1-3 are inputs and MISC I/Os 4-6 are outputs.
Stepper Motor
A, B, A, B
Digital Outputs. Pulses to stepper motor drive
circuitry.
SENSE
A
,
SENSE
B
Analog Inputs. Current sensing for stepper
motor's PWM current control.
SENSE
GND
Analog Input. Ground sense input for stepper
motor's PWM current control.
Sensor Control
ø1
Digital Output. CCD/CIS clock signal phase 1.
ø2
Digital Output. CCD/CIS clock signal phase 2.
RS
Digital Output. Reset pulse for the CCD/CIS.
CP1
Digital Output. Clamp pulse for the CCD/CIS.
CP2
Digital Output. Clamp pulse for the CCD/CIS.
TR1,
TR2
Digital Outputs. Transfer pulses for the
CCD/CIS.
LAMP
R
,
LAMP
G
,
LAMP
B
Digital Outputs. Used to control R, G, and B
LEDs of single output CIS, as well as bright-
ness of CCFL. The CDS signal can be seen
on LAMP
B
in a test mode (see register 5E, bit
7).
Master Clock Generation
CRYSTAL IN
Digital Input. Used with CRYSTAL OUT and
an external 48MHz crystal to form a crystal
oscillator.
CRYSTAL
OUT
Digital Output. Used with CRYSTAL IN and an
external 48MHz crystal to form a crystal oscil-
lator.
CRYSTAL/
EXT CLOCK
Digital Input. Tie to DGND for operation with
an external crystal. Pull up to V
D
to drive
CRYSTAL OUT with an external TTL or
CMOS clock source.
24/48
Digital Input. Tie to DGND for operation with a
48MHz crystal or external clock. Pull up to V
D
for operation with a 24MHz crystal or external
clock. NOTE: Operation at 24MHz is not guar-
anteed - always use a 48MHz crystal.
Miscellaneous
V
REGULATOR
Digital Output. This is the regulated 3.3V sup-
ply (generated from V
D
) that powers the USB
transceiver. It should be used as the terminal
voltage for the 1.5k D+ pullup resistor, and
bypassed to DGND with a 0.047µF monolithic
capacitor.
RESET
Digital input. Take high to force device into
Power On Reset state, low to exit reset state.
TEST
Analog Output.
CMODE
Digital Input. Test mode, always tie high.
LM
9
8
3
3
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Analog Power Supplies (4 pins)
V
A
(2)
This is the positive supply pin for the analog
supply. It should be connected to a voltage
source of +5V and bypassed to AGND with a
0.1µF monolithic capacitor in parallel with a
10µF tantalum capacitor.
AGND (2)
This is the ground return for the analog sup-
ply.
Digital Power Supplies (17 pins)
V
D
(5)
This is the positive supply pin for the digital
supply. It should be connected to a voltage
source of +5V and bypassed to DGND with a
0.1µF monolithic capacitor.
V
DRAM
(3)
This is the positive supply pin for the digital
supply for the LM9833's external DRAM I/O. It
also powers the A, B, A, and B stepper motor
outputs. It should be connected to a 3 or 5V
supply and bypassed to the closest DGND pin
with a 0.1µF monolithic capacitor.
DGND (9)
This is the ground return for V
D
and V
DRAM
.
Pin Descriptions
(Continued)
LM
983
3
5
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Electrical Characteristics
The following specifications apply for AGND=DGND=0V, V
A
=V
D
=V
DRAM
=+5.0V
DC
, f
CRYSTAL IN
= 48MHz, Analog Bias Current =
100%, unless otherwise noted. Boldface limits apply for T
A
=T
J
=T
MIN
to T
MAX
; all other limits T
A
=T
J
=25°C. (Notes 8, 9, & 10)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
Full Channel Characteristics (in units of 12 bit LSBs unless otherwise noted)
Resolution with No Missing Codes
16
12
bits (min)
DNL
Differential Non-Linearity
(Note 14)
Bias Current = 80%,
V
DRAM
=3.3V
-0.45
+0.75
-0.9
+2.4
LSB (min)
LSB (max)
INL
Integral Non-Linearity Error
(Notes 11 & 14)
Bias Current = 80%,
V
DRAM
=3.3V
-2.3
+1.7
-8.5
+7.5
LSB (min)
LSB (max)
C
Analog Channel Gain Constant
(ADC Codes/V), referred to 16 bits.
Includes voltage reference
variation, gain setting = 1
32768
29648
37200
LSB (min)
LSB (max)
V
OS1
Pre-Boost Analog Channel Offset Error
26
-34
+76
mV (min)
mV (max)
V
OS2
Pre-PGA Analog Channel Offset Error
-30
-80
+31
mV (min)
mV (max)
V
OS3
Post-PGA Analog Channel Offset Error
-26
-75
+26
mV (min)
mV (max)
Coarse Color Balance PGA Characteristics (Configuration Registers 3B, 3C, and 3D)
Monotonicity
5
bits (min)
G
0
(Minimum PGA Gain)
PGA Setting = 0
0.93
0.90
0.96
V/V (min)
V/V (max)
G
31
(Maximum PGA Gain)
PGA Setting = 31
3.00
2.95
3.10
V/V (min)
V/V (max)
x3 Boost Gain
x3 Boost Setting On
(bit B5 of Gain Register is set)
2.94
2.85
3.04
V/V (min)
V/V (max)
Gain Error at any gain (Note 13)
0.3
-0.6
+0.9
% (min)
% (max)
Static Offset DAC Characteristics (Configuration Registers 38, 39, and 3A)
Monotonicity
6
bits (min)
Offset DAC LSB size
PGA gain = 1
9
6
12
mV (min)
mV (max)
Offset DAC Adjustment Range
PGA gain = 1
±278
±256
mV (min)
Positive Supply Voltage (V
+
=V
A
=V
D
=V
DRAM
)
With Respect to GND=AGND=DGND
6.5V
Voltage On Any Input or Output Pin
-0.3V to V
+
+0.3V
Input Current at any pin (Note 3)
±25mA
Package Input Current (Note 3)
±50mA
Package Dissipation at T
A
= 25°C
(Note 4)
ESD Susceptibility (Note 5)
Human Body Model
2000 V
Machine Model
250 V
Soldering Information
Infrared, 10 seconds (Note 6)
235°C
Storage Temperature
-65°C to +150°
Operating Temperature Range
T
MIN
T
A
T
MAX
LM9833CCVJD
0°C
T
A
+70°C
V
A
Supply Voltage
+4.75V to +5.25V
V
D
Supply Voltage
+4.75V to +5.25V
V
DRAM
Supply Voltage
+2.85V
V
DRAM
V
D
+100mV
|V
A
-V
D
|
100mV
Input Voltage Range
-0.05V to V
+
+ 0.05V
Absolute Maximum Ratings
(Notes 1 & 2)
Operating Ratings
(Notes 1 & 2)
LM
9
8
3
3
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