DS92LV1021A
16-40 MHz 10 Bit Bus LVDS Serializer
General Description
The DS92LV1021A transforms a 10-bit wide parallel
LVCMOS/LVTTL data bus into a single high speed Bus
LVDS serial data stream with embedded clock. The
DS92LV1021A can transmit data over backplanes or cable.
The single differential pair data path makes PCB design
easier. In addition, the reduced cable, PCB trace count, and
connector size tremendously reduce cost. Since one output
transmits both clock and data bits serially, it eliminates clock-
to-data and data-to-data skew. The powerdown pin saves
power by reducing supply current when the device is not
being used. Upon power up of the Serializer, you can choose
to activate synchronization mode or use one of National
Semiconductor's Deserializers in the synchronization-to-
random-data feature. By using the synchronization mode,
the Deserializer will establish lock to a signal within specified
lock times. In addition, the embedded clock guarantees a
transition on the bus every 12-bit cycle. This eliminates
transmission errors due to charged cable conditions. Fur-
thermore, you may put the DS92LV1021A output pins into
TRI-STATE
®
to achieve a high impedance state. The PLL
can lock to frequencies between 16 MHz and 40 MHz.
Features
n
Guaranteed transition every data transfer cycle
n
Single differential pair eliminates multi-channel skew
n
Flow-through pinout for easy PCB layout
n
400 Mbps serial Bus LVDS bandwidth (at 40 MHz clock)
n
10-bit parallel interface for 1 byte data plus 2 control bits
n
Programmable edge trigger on clock
n
Bus LVDS serial output rated for 27
load
n
Small 28-lead SSOP package-MSA
Block Diagrams
20026901
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
January 2003
DS92L
V1021A
16-40
MHz
10
Bit
Bus
L
VDS
Serializer
© 2003 National Semiconductor Corporation
DS200269
www.national.com
Block Diagrams
(Continued)
Application
20026902
Functional Description
The DS92LV1021A is an upgrade to the DS92LV1021. The
DS92LV1021A no longer has a power-up sequence require-
ment. Like the DS92LV1021, the DS92LV1021A is a 10-bit
Serializer designed to transmit data over a differential back-
plane at clock speeds from 16 to 40MHz. It may also be used
to drive data over Unshielded Twisted Pair (UTP) cable.
The DS92LV1021A can be used with any of National's 10-bit
BLVDS Deserializers (DS92LV1212A for example) and has
three active states of operation: Initialization, Data Transfer,
and Resynchronization; and two passive states: Powerdown
and TRI-STATE.
The following sections describe each active and passive
state.
Initialization
Before data can be transferred, the Serializer must be initial-
ized. Initialization refers to synchronization of the Serializer's
PLL to a local clock.
When V
CC
is applied to the Serializer, the outputs are held in
TRI-STATE and internal circuitry is disabled by on-chip
power-on circuitry. When V
CC
reaches V
CC
OK (2.5V) the
Serializer's PLL begins locking to the local clock. The local
clock is the transmit clock, TCLK, provided by the source
ASIC or other device.
Once the PLL locks to the local clock, the Serializer is ready
to send data or SYNC patterns, depending on the levels of
the SYNC1 and SYNC2 inputs. The SYNC pattern is com-
posed of six ones and six zeros switching at the input clock
rate.
Control of the SYNC pins is left to the user. One recommen-
dation is a direct feedback loop from the LOCK pin. Under all
circumstances, the Serializer stops sending SYNC patterns
after both SYNC inputs return low.
Data Transfer
After initialization, the Serializer inputs DIN0DIN9 may be
used to input data to the Serializer. Data is clocked into the
Serializer by the TCLK input. The edge of TCLK used to
strobe the data is selectable via the TCLK_R/F pin.
TCLK_R/F high selects the rising edge for clocking data and
low selects the falling edge. If either of the SYNC inputs is
high for 5*TCLK cycles, the data at DIN0-DIN9 is ignored
regardless of the clock edge.
A start bit and a stop bit, appended internally, frame the data
bits in the register. The start bit is always high and the stop
bit is always low. The start and stop bits function as the
embedded clock bits in the serial stream.
Serialized data and clock bits (10+2 bits) are transmitted
from the serial data output (DO
±
) at 12 times the TCLK
frequency. For example, if TCLK is 40 MHz, the serial rate is
40 x 12 = 480 Mega bits per second. Since only 10 bits are
from input data, the serial "payload" rate is ten times the
TCLK frequency. For instance, if TCLK = 40 MHz, the pay-
load data rate is 40 x 10 = 400 Mbps. TCLK is provided by
the data source and must be in the range of 16 MHz to 40
MHz nominal.
The outputs (DO
±
) can drive a backplane or a point-to-point
connection. The outputs transmit data when the enable pin
(DEN) is high, PWRDN is high, and SYNC1 and SYNC2 are
low. The DEN pin may be used to TRI-STATE the outputs
when driven low.
Ideal Crossing Point
The ideal crossing point is the best case start and stop point
for a normalized bit. Each ideal crossing point is found by
dividing the clock period by twelve--two clock bits plus ten
data bits. For example, a 40 MHz clock has a period of 25ns.
The 25ns divided by 12 bits is approximately 2.08ns. This
means that each bit width is approximately 2.08ns, and the
ideal crossing points occur every 2.08ns. For a graphical
representation, please see Figure 9.
Resynchronization
The Deserializer LOCK pin driven low indicates that the
Deserializer PLL is locked to the embedded clock edge. If
the Deserializer loses lock, the LOCK output will go high and
the outputs (including RCLK) will be TRI-STATE.
The LOCK pin must be monitored by the system to detect a
loss of synchronization, and the system must decide if it is
necessary to pulse the Serializer SYNC1 or SYNC2 pin to
resynchronize. There are multiple approaches possible. One
recommendation is to provide a feedback loop using the
DS92L
V1021A
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2
Resynchronization
(Continued)
LOCK pin itself to control the sync request of the Serializer
(SYNC1 or SYNC2). At the time of publication, other than the
DS92LV1210, all other Deserializers from National Semicon-
ductor have random lock capability. This feature does not
require the system user to send SYNC patterns upon loss of
lock. However, lock times can only be guaranteed with trans-
mission of SYNC patterns. Dual SYNC pins are provided for
multiple control in a multi-drop application.
Powerdown
The Powerdown state is a low power sleep mode that the
Serializer and Deserializer may use to reduce power when
no data is being transferred. The device enters Powerdown
when the PWRDN pin is driven low on the Serializer. In
Powerdown, the PLL stops and the outputs go into TRI-
STATE, disabling load current and reducing supply current
into the milliamp range. To exit Powerdown, PWRDN must
be driven high.
Both the Serializer and Deserializer must reinitialize and
resynchronize before data can be transferred. The Deserial-
izer will initialize and assert LOCK high until it is locked to the
Bus LVDS clock.
TRI-STATE
For the Serializer, TRI-STATE is entered when the DEN pin
is driven low. This will TRI-STATE both driver output pins
(DO+ and DO-). When DEN is driven high, the serializer will
return to the previous state as long as all other control pins
remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F).
Ordering Information
Order Number NSID
Function
Package
DS92LV1021AMSA
Serializer
MSA28
DS92L
V1021A
www.national.com
3
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
-0.3V to +4V
CMOS/TTL Input Voltage
-0.3V to (V
CC
+0.3V)
CMOS/TTL Output
Voltage
-0.3V to (V
CC
+0.3V)
Bus LVDS Receiver Input
Voltage
-0.3V to +3.9V
Bus LVDS Driver Output
Voltage
-0.3V to +3.9V
Bus LVDS Output Short
Circuit
Duration
Continuous
Junction Temperature
+150°C
Storage Temperature
-65°C to +150°C
Lead Temperature
(Soldering, 4 seconds)
+260°C
Maximum Package Power Dissipation Capacity
@
25°C Package:
28L SSOP
1.27 W
Package Derating:
28L SSOP
10.2 mW/°C above
+25°C
ESD Rating (HBM)
>
2.0kV
(Note 1)
Note 1: With a limited Engineering sample size,
ESD (HBM) testing passed 2.5kV
Recommended Operating
Conditions
Min
Nom
Max
Units
Supply Voltage (V
CC
)
3.0
3.3
3.6
V
Operating Free Air
Temperature (T
A
)
-40
+25
+85
°C
Supply Noise Voltage
(V
CC
)
100 mV
P-P
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SERIALIZER CMOS/TTL DC SPECIFICATIONS (apply to DIN0-9, TCLK, PWRDN, TCLK_R/F, SYNC1, SYNC2, DEN)
V
IH
High Level Input Voltage
2.0
V
CC
V
V
IL
Low Level Input Voltage
GND
0.8
V
V
CL
Input Clamp Voltage
I
CL
= -18 mA
-1.5
V
I
IN
Input Current
V
IN
= 0V or 3.6V
-10
±
2
+10
µA
SERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins DO+ and DO-)
V
OD
Output Differential Voltage
(DO+)(DO-)
RL = 27
200
270
mV
V
OD
Output Differential Voltage
Unbalance
35
mV
V
OS
Offset Voltage
0.78
1.1
1.3
V
V
OS
Offset Voltage Unbalance
35
mV
I
OS
Output Short Circuit Current
D0 = 0V, DIN = High,PWRDN and DEN = 2.4V
-30
-40
mA
I
OZ
TRI-STATE Output Current
PWRDN or DEN = 0.8V, DO = 0V or VCC
-10
±
1
+10
µA
I
OX
Power-Off Output Current
VCC = 0V, DO = 0V or VCC
-20
±
1
+20
µA
SERIALIZER SUPPLY CURRENT (apply to pins DVCC and AVCC)
I
CCD
Worst Case Serializer Supply
Current
RL = 27
,
Figure 1
f = 40 MHz
40
55
mA
f = 16 MHz
28
35
mA
I
CCXD
Serializer Supply Current
Powerdown
PWRDN = 0.8V
88
300
µA
DS92L
V1021A
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4
Serializer Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
TCP
Transmit Clock Period
25
T
62.5
ns
t
TCIH
Transmit Clock High Time
0.4T
0.5T
0.6T
ns
t
TCIL
Transmit Clock Low Time
0.4T
0.5T
0.6T
ns
t
CLKT
TCLK Input Transition
Time
3
6
ns
t
JIT
TCLK Input Jitter
150
ps
(RMS)
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
LLHT
Bus LVDS
Low-to-High
Transition Time
R
L
= 27
,
Figure 2,
C
L
=10pF to GND
0.31
0.75
ns
t
LHLT
Bus LVDS
High-to-Low
Transition Time
0.30
0.75
ns
t
DIS
DIN (0-9) Setup to
TCLK
Figure 4,
R
L
= 27
,
C
L
=10pF to GND
0
ns
t
DIH
DIN (0-9) Hold from
TCLK
4.0
ns
t
HZD
DO
±
HIGH to
TRI-STATE Delay
Figure 5 ,(Note 4),
R
L
= 27
,
C
L
=10pF to GND
3.5
10
ns
t
LZD
DO
±
LOW to
TRI-STATE Delay
2.9
10
ns
t
ZHD
DO
±
TRI-STATE to
HIGH Delay
2.5
10
ns
t
ZLD
DO
±
TRI-STATE to
LOW Delay
2.7
10
ns
t
SPW
SYNC Pulse Width
Figure 7,
R
L
= 27
5*t
TCP
ns
t
PLD
Serializer PLL Lock
Time
Figure 6,
R
L
= 27
510*t
TCP
2049*t
TCP
ns
t
SD
Serializer Delay
Figure 8 , R
L
= 27
t
TCP
+1.0
t
TCP
+ 2.0
t
TCP
+4.0
ns
t
BIT
Bus LVDS Bit Width
R
L
= 27
,
C
L
=10pF to GND
t
CLK
/ 12
ns
t
DJIT
Deterministic Jitter
R
L
= 27
,
C
L
=10pF to GND,
(Note 5)
f = 40 MHz
-320
-110
150
ps
f = 16 MHz
-800
-160
380
ps
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of "Electrical Characteristics" specifies conditions of device operation.
Note 2: Typical values are given for V
CC
= 3.3V and T
A
= +25°C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD,
VOD,
VTH and VTL which are differential voltages.
Note 4: Due to TRI-STATE of the Serializer, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
Note 5: t
DJIT
specifications are Guranteed By Design (GBD) using statistical analysis.
DS92L
V1021A
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