DS3884A
BTL Handshake Transceiver
General Description
The DS3884A is one in a series of transceivers designed
specifically for the implementation of high performance Fu-
turebus+ and proprietary bus interfaces. The DS3884A is a
BTL 6-bit Handshake Transceiver designed to conform to
IEEE 1194.1 (Backplane Transceiver Logic -- BTL) as speci-
fied in the IEEE 896.2 Futurebus+ specification.
Features
n
Fast propagation delay (3 ns typ)
n
6-bit BTL transceiver
n
Selective receiver glitch filtering (FR1FR3)
n
Meets 1194.1 Standard on Backplane Transceiver Logic
(BTL)
n
Supports live insertion
n
Glitch free power-up/down protection
n
Typically less than 5 pF bus-port capacitance
n
Low Bus-port voltage swing (typically 1V) at 80 mA
n
TTL compatible driver and control inputs
n
Separate TTL I/O
n
Open collector bus-port outputs allow Wired-OR
connection
n
Controlled rise and fall time to reduce noise coupling to
adjacent lines
n
Built in Bandgap reference with separate QV
CC
and
QGND pins for precise receiver thresholds
n
Exceeds 2 kV ESD testing (Human Body Model)
n
Individual Bus-port ground pins
n
Product offered in PQFP package styles
Connection Diagram
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
DS011460-1
Order Number DS3884AVF
See NS Package VF44B
August 2000
DS3884A
BTL
Handshake
T
ransceiver
© 2000 National Semiconductor Corporation
DS011460
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Logic Diagram
DS011460-3
DS3884A
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2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
6.5V
Control Input Voltage
6.5V
Driver Input and Receiver Output
5.5V
Receiver Input Current
±
15 mA
Bus Termination Voltage
2.4V
Power Dissipation at 25°C
PQFP
1.3W
Derate PQFP Package
11.1 mW/°C
Storage Temperature Range
-65°C to +150°C
Lead Temperature
(Soldering, 4 seconds):
260°C
Recommended Operating
Conditions
Supply Voltage, V
CC
4.5V5.5V
Bus Termination Voltage (V
T
)
2.06V2.14V
Operating Free Air Temperature
0°C to 70°C
DC Electrical Characteristics
(Notes 2, 3)
T
A
= 0 to +70°C, V
CC
= 5V
±
10%
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRIVER AND CONTROL INPUT: (Dn, DE
*
, PS1 and PS2)
V
IH
Minimum Input High Voltage
2.0
V
V
IL
Maximum Input Low Voltage
0.8
V
I
I
Input Leakage Current
V
IN
= V
CC
= 5.5V
100
µA
I
IH
Input High Current
V
IN
= 2.4V
40
µA
I
IL
Input Low Current
V
IN
= 0.5V
-100
µA
V
CL
Input Diode Clamp Voltage
I
CLAMP
= -12 mA
-1.2
V
DRIVER OUTPUT/RECEIVER INPUT: (Bn)
V
OLB
Output Low Bus Voltage
Dn = 2.4V, DE
*
= 0V,
0.75
1.0
1.1
V
(Note 5)
I
OL
= 80 mA
I
OLBZ
Output Low Bus Current
Dn = 0.5V, DE
*
= 2.4V, Bn = 0.75V
100
µA
I
OHBZ
Output High Bus Current
Dn = 0.5V, DE
*
= 2.4V, Bn = 2.1V
100
µA
I
OLB
Output Low Bus Current
Dn = 0.5V, DE
*
= 0V, Bn = 0.75V
220
µA
I
OHB
Output High Bus Current
Dn = 0.5V, DE
*
= 0V, Bn = 2.1V
350
µA
V
TH
Receiver Input Threshold
DE
*
= 2.4V
1.47
1.55
1.62
V
V
CLP
Positive Clamp Voltage
V
CC
= Max or 0V, I
Bn
= 1 mA
2.4
3.4
4.5
V
V
CC
= Max or 0V, I
Bn
= 10 mA
2.9
3.9
5.0
V
V
CLN
Negative Clamp Voltage
I
CLAMP
= -12 mA
-1.2
V
RECEIVER OUTPUT: (FRn and Rn)
V
OH
Voltage Output High
Bn = 1.1V, DE
*
= 2.4V, I
OH
= -2 mA
2.4
3.2
V
V
OL
Voltage Output Low
Bn = 2.1V, DE
*
= 2.4V, I
OL
= 24 mA
0.35
0.5
V
Bn = 2.1V, DE
*
= 2.4V, I
OL
= 8 mA
0.35
0.4
V
I
OS
Output Short Circuit Current
Bn = 1.1V, DE
*
= 2.4V (Note 4)
-40
-70
-100
mA
SUPPLY CURRENT
I
CC
Supply Current: Includes V
CC
,
DE
*
= 0.5V, All Dn = 2.4V
50
70
mA
QV
CC
and LI
DE
*
= 2.4V, All Bn = 2.1V
50
70
mA
I
LI
Live Insertion Current
DE
*
= 2.4V, All Dn = 0.5V
1
3
mA
DE
*
= 0.5V, All Dn = 2.4V
2
5
mA
Note 1: "Absolute Maximum Ratings" are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should
be operated at these limits. The table of "Electrical Characteristics" provide conditions for actual device operation.
Note 2:
All input and/or output pins shall not exceed V
CC
plus 0.5V and shall not exceed the absolute maximum rating at anytime, including power-up and
power-down. This prevents the ESD structure from being damaged due to excessive currents flowing from the input and/or output pins to QV
CC
and V
CC
. There is
a diode between each input and/or output to V
CC
which is forward biased when incorrect sequencing is applied. Alternatively, a current limiting resistor can be used
when pulling-up the inputs to prevent damage. The current into any input/output pin shall be no greater than 50 mA. Exception, LI and Bn pins do not have power
sequencing requirements with respect to V
CC
and QV
CC
. Furthermore, the difference between V
CC
and QV
CC
should never be greater than 0.5V at any time including
power-up.
Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified.
All typical values are specified under these conditions.: V
CC
= 5V and T
A
= 25°C unless otherwise stated.
Note 4: Only one output should be shorted at a time, and duration of the short should not exceed one second.
Note 5: Referenced to appropriate signal ground. Do not exceed maximum power dissipation of package.
DS3884A
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3
AC Electrical Characteristics
(Note 6)
T
A
= 0°C to +70°C, V
CC
= 5V
±
10%
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRIVER
t
PHL
Dn to Bn
Prop. Delay
DE
*
= 0V
1
3
5
ns
t
PLH
(
Figure 1, Figure 2 )
1
3
5
ns
t
PHL
DE
*
to Bn
Enable Time
Dn = 3V
2
4
6
ns
t
PLH
Disable Time
(
Figure 1, Figure 3 )
2
4
6
ns
t
r
Transition Time -- Rise/Fall
(
Figure 1, Figure 2 )
1
2
3.5
ns
t
f
20% to 80%
1
2
3.5
ns
SR
Skew Rate is Calculated
(Note 11)
0.5
V/ns
from 1.3V to 1.8V
t
skew
Skew between Drivers in
(Note 7)
1
3
ns
the Same Package
RECEIVER
t
PHL
Bn to Rn
Prop. Delay
DE
*
= 3V
2
4
5
ns
t
PLH
(
Figure 4, Figure 5 )
2
4
6
ns
t
skew
Skew between Receivers in
(Note 7)
1
3
ns
Same Package
FILTERED RECEIVER
t
PHL
Bn to FRn
Prop. Delay
PS1 = 0V
PS2 = 0V
DE
*
= 3V
6
12
16
ns
(
Figure 4, Figure 5 ), R
EXT
= 13 k
PS1 = 0V
PS2 = 3V
DE
*
= 3V
11
16
21
ns
(
Figure 4, Figure 5 ), R
EXT
= 13 k
PS1 = 3V
PS2 = 0V
DE
*
= 3V
15
21
27
ns
(
Figure 4, Figure 5 ), R
EXT
= 13 k
PS1 = 3V
PS2 = 3V
DE
*
= 3V
25
33
45
ns
(
Figure 4, Figure 5 ), R
EXT
= 13 k
t
PLH
Bn to FRn
Prop. Delay
DE
*
= 3V (
Figure 4, Figure 5 )
(Note 8)
2
5
7
ns
R
EXT
= 13 k
t
GR
Glitch Rejection
PS1 = 0V
PS2 = 0V
DE
*
= 3V
5
9
16
ns
(
Figure 4, Figure 6 ), R
EXT
= 13 k
PS1 = 0V
PS2 = 3V
DE
*
= 3V
10
13
18
ns
(
Figure 4, Figure 6 ), R
EXT
= 13 k
PS1 = 3V
PS2 = 0V
DE
*
= 3V
14
18
24
ns
(
Figure 4, Figure 6 ), R
EXT
= 13 k
PS1 = 3V
PS2 = 3V
DE
*
= 3V
24
31
42
ns
(
Figure 4, Figure 6 ), R
EXT
= 13 k
FILTERED RECEIVER TIMING REQUIREMENTS
t
s
PSn to Bn
Set-Up Time
(
Figure 7 ), R
EXT
= 13 k
250
ns
PARAMETERS NOT TESTED
Coutput
Capacitance at Bn
(Note 9)
5
pF
t
NR
Noise Rejection
(Note 10)
1
ns
Note 6: Input waveforms shall have a rise/fall time of 3 ns.
Note 7: t
skew
is an absolute value defined as differences seen in propagation delays between drivers in the same package with identical load conditions.
Note 8: Filtered receiver t
PLH
is independent of filter setting.
Note 9: The parameter is tested using TDR techniques described in P1194.0 BTL Backplane Design Guide.
Note 10: This parameter is tested during device characterization. The measurements revealed that the part will reject 1 ns pulse width.
Note 11: Futurebus+ transceivers are required to limit bus signal rise and fall times to no faster than 0.5V/ns, measured between 1.3V and 1.8V (approximately 20%
to 80% of nominal voltage swing). The rise and fall times are measured with a transceiver loading equivalent to 12.5
tied to +2.1V DC.
DS3884A
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4
Pin Descriptions
Pin Name
Number of
Input/
Description
Pins
Output
B1B6
6
I/O
BTL receiver input and driver output
B1GNDB6GND
6
NA
Driver output ground reduces bounce due to high
current switching of driver outputs
(Note 12)
DE
*
1
I
Driver Enable Low
D1D6
6
I
TTL Driver Input
FR1FR3
3
O
TTL Filtered Receiver Output
GND
3
NA
Ground reference for switching circuits.
(Note 12)
LI
1
NA
Power supply for live insertion. Boards that require live
insertion should connect LI to the live insertion pin on
the connector. (Note 13)
NC
4
NA
No Connect
PS1, PS2
2
I
Pulse Width Selection pin determines glitch filter setting
(Note 14)
R1R6
6
O
TTL Receiver Output
REXT
1
NA
External Resistor pin. External resistor is used for
internal biasing of filter circuitry. The 13 k
resistor shall
be connected between REXT and GND. The resistor
shall have a tolerance of 1% and a temperature
coefficient of 100 ppm/°C or better.
QGND
2
NA
Ground reference for receiver input bandgap reference
and non-switching circuits (Note 12)
QV
CC
1
NA
V
CC
supply for bandgap reference and non-switching
circuits (Note 13)
V
CC
2
NA
V
CC
supply for switching circuits (Note 13)
Note 12: the multiplicity of grounds reduces the effective inductance of bonding wires and leads, which then reduces the noise caused by transients on the ground
path. The various ground pins can be tied together provided that the external ground has low inductance (i.e., ground plane with power pins and many signal pins
connected to the backplane ground). If the external ground floats considerably during transients, precautionary steps should be taken to prevent QGND from moving
with reference to the backplane ground. The receiver threshold should have the same ground reference as the signal coming from the backplane. A voltage offset
between their grounds will degrade the noise margin.
Note 13: The same considerations for ground are used for V
CC
in reducing lead inductance (see Note 12). QV
CC
and V
CC
should be tied together externally. If live
insertion is not supported, the LI pin can be tied together with QV
CC
and V
CC
.
Note 14: See AC characteristics for filter setting.
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