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Part Number µPD75116F

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© NEC Corporation 1991
DESCRIPTION
The
µ
PD75116F offers high-speed operation (t
CY
= 1.91
µ
s) at a low supply voltage (V
DD
= 2.7 V) which is not possible
with the
µ
PD75116.
It has the same functions as, and is pin compatible with, the
µ
PD75116, allowing low voltage sets to be developed
by making efficient use of previously developed and used software resources. Note, however, that the operating
voltage range is different from that of the
µ
PD75116.
A version of the
µ
PD75116F with on-chip PROM, the
µ
PD75P116*, is also available for evaluation during system
development.
* There are some differences in electrical specifications between the
µ
PD75116F and the
µ
PD75P116.
Functions are described in detail in the following User's Manual, which should be read when carrying out design
work.
µ
PD75116 User's Manual : IEM-922
FEATURES
·
µ
PD75116 low voltage high-speed operation product
· Instruction execution time
4-BIT SINGLE-CHIP MICROCOMPUTER
µ
PD75108F,75112F,75116F
MOS INTEGRATED CIRCUIT
DATA SHEET
The mark 5 shows major revised points.
Document No. IC-2810B
(O.D.No. IC-8224B)
Date Published April 1994P
Printed in Japan
The information in this document is subject to change without notice.
1.91
µ
s , 15.3
µ
s (operation at 4.19 MHz)
2
µ
s, 4
µ
s, 32
µ
s (operation at 2 MHz)
Ta = ­40 to +50
°
C
Ta = ­40 to +60
°
C
V
DD
= 2.7 to 5.0 V
1.91
µ
s , 15.3
µ
s (operation at 4.19 MHz)
2
µ
s, 4
µ
s, 32
µ
s (operation at 2 MHz)
V
DD
= 2.8 to 5.0 V
V
DD
= 4.5 to 5.0 V
0.95
µ
s, 1.91
µ
s, 15.3
µ
s (operation at 4.19 MHz)
·
43 systematically arranged instructions
· 8-bit data transfer, compare, operation and increment/decrement instructions
· GETI instruction allowing any 2-byte or 3-byte instruction to be implemented in 1 byte
·
Wide range of input/output ports : 58 ports
·
3 on-chip 8-bit timer channels : synchronous/asynchronous (start/stop)
·
8-bit serial interface on chip
·
Programmable threshold port : 4-bit resolution
×
4 channels
"Unless there are any particular functional differences, the
µ
PD75116F is described in this document as a representative
product."
2
µ
PD75108F,75112F,75116F
ORDERING INFORMATION
Ordering Code
Package
Quality Grade
µ
PD75108FGF-
×××
-3BE
64-pin plastic QFP (14
×
12 mm)
Standard
µ
PD75112FGF-
×××
-3BE
64-pin plastic QFP (14
×
12 mm)
Standard
µ
PD75116FGF-
×××
-3BE
64-pin plastic QFP (14
×
20 mm)
Standard
Remarks
×××:
ROM code number
APPLICATIONS
Cordless telephone subsets, portable radio equipment, pager, etc.
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
3
µ
PD75108F,75112F,75116F
OVERVIEW OF FUNCTIONS
Contents
43
0.95
µ
s, 1.91
µ
s, 15.3
µ
s (V
DD
= 4.5 to 5.0 V, 4.19 MHz operation)
2
µ
s, 4
µ
s, 32
µ
s (V
DD
= 2.7 to 5.0 V, 2 MHz operation)
3-stage switching capability
0.95
µ
s (operating at 4.5 to 5.0 V)
1.91
µ
s (operating at 2.7 V )
8064
×
8 bits (
µ
PD75108F)
12160
×
8 bits (
µ
PD75112F)
16256
×
8 bits (
µ
PD75116F)
512
×
4 bits
4-bits
×
8
×
4 banks (memory mapping)
3 accumulators for different manipulated data lengths
· 1-bit accumulator (CY), 4­bit acculumalor (A), 8-bit accumulator (XA)
Total 58
· CMOS input pins
: 10
· CMOS input/output pins (LED direct drive capability)
: 32
· Middle-high voltage N-ch open-drain input/output pins : 12
(LED direct drive capability, a pull-up resistor can be incorporated bit-wise.)
· Comparator input pins (4-bit precision)
: 4
· 8-bit timer/event counter
×
2
· 8-bit basic interval timer (watchdog timer applicable)
· 2 transfer modes
· Serial transmission/reception modes
· Serial reception mode
· LSB top/MSB top switchable
External : 3 Internal : 4
External : 2
· STOP/HALT mode
· Various bit manipulation instructions (set, reset, test, Boolean operation)
· 8-bit data transfer, comparison, operation, increment/decrement instructions
· 1-byte relative branch instruction
· GETI instruction that can implement arbitrary 2-byte/3-byte instructions with 1 byte
· Bit manipulation memory (bit sequential buffer) on chip
· 64-pin plastic QFP (14
×
20 mm)
Item
Basic instructions
Instruction cycle
Minimum instruction
execution time
On-chip memory
General register
Accumulator
Input/output port
Timer/counter
8-bit serial interface
Vector interrupt
Test input
Standby
Instruction set
Others
Package
ROM
RAM
4
µ
PD75108F,75112F,75116F
CONTENTS
1.
PIN CONFIGURATION (TOP VIEW) .....................................................................................................
6
2.
BLOCK DIAGRAM ..................................................................................................................................
7
3.
PIN FUNCTIONS ....................................................................................................................................
8
3.1
PORT PINS .....................................................................................................................................................
8
3.2
OTHER PINS ...................................................................................................................................................
9
3.3
PIN INPUT/OUTPUT CIRCUITS ...................................................................................................................
10
3.4
RECOMMENDED CONNECTION OF UNUSED PINS .................................................................................
11
3.5
PRECAUTIONS CONCERNING P00/INT4 PIN AND RESET PIN ...............................................................
12
4.
MEMORY CONFIGURATION ................................................................................................................ 13
5.
PERIPHERAL HARDWARE FUNCTIONS .............................................................................................. 18
5.1
DIGITAL INPUT/OUTPUT PORTS ................................................................................................................
18
5.2
CLOCK GENERATOR .....................................................................................................................................
19
5.3
CLOCK OUTPUT CIRCUIT .............................................................................................................................
20
5.4
BASIC INTERVAL TIMER ..............................................................................................................................
21
5.5
TIMER/EVENT COUNTER .............................................................................................................................
21
5.6
SERIAL INTERFACE .......................................................................................................................................
23
5.7
PROGRAMMABLE THRESHOLD PORT (ANALOG INPUT PORT) ............................................................
25
5.8
BIT SEQUENTIAL BUFFER ...........................................................................................................................
26
6.
INTERRUPT FUNCTION ........................................................................................................................ 27
7.
STANDBY FUNCTION ........................................................................................................................... 29
8.
RESET FUNCTION ................................................................................................................................. 30
9.
INSTRUCTION SET ................................................................................................................................ 32
10. APPLICATION EXAMPLE ...................................................................................................................... 41
10.1 CORDLESS TELEPHONE (SUBSET) ............................................................................................................
41
10.2 DISPLAY PAGER ............................................................................................................................................
42
11. MASK OPTION SELECTION .................................................................................................................. 43
12. ELECTRICAL SPECIFICATIONS ............................................................................................................ 44
12.1 WHEN Ta = ­40 to +50
°
C, V
DD
= 2.7 to 5.0 V ...........................................................................................
45
12.2 WHEN Ta = ­40 to +60
°
C, V
DD
= 2.8 to 5.0 V ...........................................................................................
55
5
µ
PD75108F,75112F,75116F
13. CHARACTERISTIC CURVES (REFERENCE) ......................................................................................... 65
14.
PACKAGE INFORMATION .....................................................................................................................................
71
15. RECOMMENDED SOLDERING CONDITIONS ..................................................................................... 73
APPENDIX A. FUNCTIONAL DIFFERENCES AMONG
µ
PD751
××
SERIES PRODUCTS .......................
74
APPENDIX B. DEVELOPMENT TOOLS ...................................................................................................... 76
APPENDIX C. RELATED DOCUMENTS ..................................................................................................... 77
µ
PD75108,75112F,75116F
6
1.
PIN CONFIGURATION (TOP VIEW)
64-Pin Plastic QFP (14
×
20 mm)
µ
PD75116FGF-
×××
-3BE
µ
PD75112FGF-
×××
-3BE
µ
PD75116FGF-
×××
-3BE
5
Pin Name
P00-P03
:
Port 0
SCK
:
Serial Clock
P10-P13
:
Port 1
SO
:
Serial Output
P20-P23
:
Port 2
SI
:
Serial Input
P30-P33
:
Port 3
PTO0, PTO1
:
Programmable Timer Output
P40-P43
:
Port 4
PCL
:
Programmable Clock
P50-P53
:
Port 5
PTH00-PTH03
:
Programmable Treshold Input
P60-P63
:
Port 6
INT0, INT1, INT4 :
External Vectored Interrupt Input
P70-P73
:
Port 7
INT2, INT3
:
External Test Input
P80-P83
:
Port 8
TI0, TI1
:
Timer Input
P90-P93
:
Port 9
X1, X2
:
Clock Oscillation
P120-P123 :
Port 12
RESET
:
Reset
P130-P133 :
Port 13
NC
:
No Connection
P140-P143 :
Port 14
V
DD
:
Positive Power Supply
V
SS
:
Ground
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
X2
X1
P41
P40
P53
P52
P51
P50
RESET
P63
P62
P61
P60
P73
P72
20 21 22 23 24 25 26 27 28 29 30 31 32
64
62 61 60 59 58 57 56 55 54 53 52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
P42
P43
P30
P31
P32
P33
V
DD
NC
P141
P142
P143
P130
P81
P71
63
35
34
33
P131
P132
P133
P120
P121
P122
P123
P00/INT4
P02/SO
P20/PTO0
P23
P01/SCK
P03/SI
P21/PTO1
P22/PCL
T11
T10
PTH00
PTH01
17
18
19
P70
P83
P82
P80
P93
P92
P91
P90
V
SS
P13/INT3
P12/INT2
P11/INT1
P10/INT0
PTH03
PTH02
P140
µ
PD75108F
,75112F
,75116F
7
P
ORT 0
PORT 1
4
4
P00-P03
P10-P13
PORT 3
PORT 4
PORT 5
PORT 6
4
4
4
4
PORT 2
4
P20-P23
P30-P33
P40-P43
P50-P53
P60-P63
PORT 7
4
P70-P73
SP(8)
BANK
GENERAL REG.
RAM
DATA
MEMORY
512
×
4 BITS
DECODE
AND
CONTROL
CY
ALU
PROGRAM*
COUNTER
RESET
V
SS
STAND BY
CONTROL
V
DD
CPU CLOCK
CLOCK
GENERATOR
CLOCK
DIVIDER
CLOCK
OUTPUT
CONTROL
X2
X1
PCL/P22
f
XX
/ 2
N
BASIC
INTERVAL
TIMER
INTER-
RUPT
CONTROL
INTT1
INTBT
PORT 14
4
P140-P143
PORT 12
4
P120-P123
TIMER/EVENT
COUNTER
#0
INTT0
TI0
PTO0/P20
TIMER/EVENT
COUNTER
#1
TI1
PTO1/P21
SERIAL
INTERFACE
INTSIO
SCK/P01
SO/P02
SI/P03
PROGRAM-
MABLE
THRESHOLD
PORT #0
PTH00-PTH03
INT4/P00
INT2/P12
INT1/P11
INT0/P10
INT3/P13
PORT 13
4
P130-P133
PORT 9
4
P90-P93
PORT 8
4
P80-P83
BIT SEQ.
BUFFER
(16)
4
*
The
µ
PD75108F program counter is composed of 13 bits and the
µ
PD75112F/75116F program counter is composed of 14 bits
2.
BLOCK DIAGRAM
ROM
PROGRAM
MEMORY
8064
×
8 BITS
(
µ
PD75108F)
12160
×
8 BITS
(
µ
PD75112F)
16256
×
8 BITS
(
µ
PD75116F)
8
µ
PD75108F,75112F,75116F
4-bit input port (PORT 0).
4-bit input port (PORT 1).
4-bit input/output port (PORT 2).
Programmable 4-bit input/output port (PORT 3).
Input/output can be specified bit-wise.
4-bit input/output port (PORT 4).
4-bit input/output port (PORT 5).
Programmable 4-bit input/output port (PORT 6).
Input/output can be specified bit-wise.
4-bit input/output port (PORT 7).
4-bit input/output port (PORT 8).
4-bit input/output port (PORT 9).
N-ch open-drain 4-bit input/output port (PORT
12).
On-chip pull-up resistor can be specified bit-wise
(mask option).
Open-drain: +10 V withstand voltage
N-ch open-drain 4-bit input/output port (PORT
13).
On-chip pull-up resistor can be specified bit-wise
(mask option).
Open-drain: +10 V withstand voltage
N-ch open-drain 4-bit input/output port (PORT
14).
On-chip pull-up resistor can be specified bit-wise
(mask option).
Open-drain: +10 V withstand voltage
P00
P01
P02
P03
P10
P11
P12
P13
P20 *3
P21 *3
P22 *3
P23 *3
P30 to P33 *3
P40 to P43 *3
P50 to P53 *3
P60 to P63 *3
P70 to P73 *3
P80 to P83
*3
P90 to P93
*3
P120 to P123 *3
P130 to P133 *3
P140 to P143 *3
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
*2
Input
*2
Input
*2
3.
PIN FUNCTIONS
3.1
PORT PINS
Input
Input/output
Input/output
Input
Input
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Dual-
Function Pin
INT4
SCK
SO
SI
INT0
INT1
INT2
INT3
PTO0
PTO1
PCL
--
--
--
--
--
--
--
--
--
--
--
I/OCircuit
Type *1
B
F
E
B
B
E
E
E
E
E
E
E
E
M
M
M
* 1.
q
q
: Schmitt trigger input
2.
Open-drain ... high impedance
On-chip pull-up resistor ... high level
3.
Direct LED drive capability
Pin Name
Input/Output
Function
×
×
--
8-bit I/O
After Reset
9
µ
PD75108F,75112F,75116F
PTH00 to PTH03
TI0
TI1
PTO0
PTO1
SCK
SO
SI
INT4
INT0
INT1
INT2
INT3
PCL
X1, X2
RESET
NC*2
V
DD
V
SS
3.2
OTHER PINS
Input
Input
Input/output
Input/output
Input/output
Input
Input
Input
Input
Input/output
Input
--
Dual-
Function Pin
--
--
P20
P21
P01
P02
P03
P00
P10
P11
P12
P13
P22
--
--
--
--
--
I/O Circuit
Type
*1
N
B
E
F
E
B
B
B
B
E
B
Input
Input
Input
Input
Input
Input
Input
Input
Variable threshold voltage 4-bit analog input port.
External event pulse input to timer/event counter. Or edge
detection vectored interrupt input or 1-bit input is also
possible.
Timer/event counter output
Serial clock input/output
Serial data output
Serial data input
Edge detection vector interrupt input (detection of both
rising and falling edges)
Edge detection vector interrupt input (detection edge se-
lectable)
Edge detection testable input (rising edge detection)
Clock output
System clock oscillation crystal/ceramic connection pin.
When an external clock is used, the clock is input to X1 and
the inverted clock is input to X2.
System reset input (low-level active).
No Connection
Positive power supply
GND potential
* 1.
q
q
: Schmitt trigger input
2.
When sharing a print board with
µ
PD75P116, NC pin should be connected to V
DD
.
After Reset
Function
Input/Output
Pin Name
10
µ
PD75108F,75112F,75116F
3.3
PIN INPUT/OUTPUT CIRCUITS
The input/output circuits of each pin of the
µ
PD75116F are shown in abbreviated form.
Fig. 3-1 Pin Input/Output Circuit List
Type A
Type F
Type B
Type D
Type E
Type M
Type N
IN/OUT
data
output
disable
Type D
P-ch
V
DD
IN
N-ch
IN
Pull-Up Resistor
V
DD
IN/OUT
N-ch
(+6 V
Withstand
Voltage)
data
output
disable
(Mask Option)
Middle-High Voltage Input Buffer
(+6 V Withstand Voltage)
IN/OUT
data
output
disable
Type D
Type A
P-ch
V
DD
OUT
N-ch
data
output
disable
+
­
V
REF
(Threshold Voltage)
CMOS standard input buffer
This is an input/output circuit made up of a Type D
push-pull output and Type B Schmitt-triggered input.
Schmitt-trigger input with hysteresis characteristic
Push-pull output that can be made high-
impedance output (P-ch and N-ch OFF)
This is an input/output circuit made up of a
Type D push-pull output and Type A input buffer.
Comparator
Type B
11
µ
PD75108F,75112F,75116F
3.4
RECOMMENDED CONNECTION OF UNUSED PINS
Pin
PTH00 to PTH03
TI0
TI1
P00
P01 to P03
P10 to P13
P20 to P23
P30 to P33
P40 to P43
P50 to P53
P60 to P63
P70 to P73
P80 to P83
P90 to P93
P120 to P123
P130 to P133
P140 to P143
NC
Recommended Connection
Connect to V
SS
or V
DD
.
Connect to V
SS
.
Connect to V
SS
or V
DD
.
Connect to V
SS
.
Input
: Connect to V
SS
or V
DD
.
Output : Leave open.
Leave open *
*
If a printed board is used with the
µ
PD75P116, NC pin should be connected to V
DD
directly.
12
µ
PD75108F,75112F,75116F
3.5
PRECAUTIONS CONCERNING P00/INT4 PIN AND RESET PIN
In addition to the functions shown in 3.1 and 3.2, the P00/INT4 pin and RESET pin are also used to set the test
mode for testing internal
µ
PD75116F operation (for IC testing).
The test mode is set when a voltage greater than V
DD
is applied to either of these pins. Consequently, if noise
exceeding V
DD
is applied during normal operation, the test mode may be entered, making it impossible for normal
operation to continue.
If, for example, inter-wiring noise is applied to the P00/INT4 or RESET pin due to the length of the wiring from
these pins, and the pin voltage exceeds V
DD
, misoperation may result.
Wiring should therefore be carried out so that interwiring noise is suppressed as far as possible. If it is completely
impossible to suppress noise, noise prevention measures should be taken using an external component as shown
below.
q
q
Capacitor connected between
P00/INT4 or RESET and V
DD
q
q
Diode with small V
F
(0.3 V or less) connected
between P00/INT4 or RESET and V
DD
V
DD
V
DD
P00/INT4, RESET
Diode with
small V
F
V
DD
V
DD
P00/INT4, RESET
13
µ
PD75108F,75112F,75116F
4.
MEMORY CONFIGURATION
·
Program memory (ROM)
: 8064
×
8 bits (0000H to 1F7FH) :
µ
PD75108F
12160
×
8 bits (0000H to 2F7FH) :
µ
PD75112F
16256
×
8 bits (0000H to 3F7FH) :
µ
PD75116F
· 0000H to 0001H
: Vector table in which a program start address after reset is written.
· 0002H to 000BH
: Vector table in which program start addresses after interruption are written.
· 0020H to 007FH
: Table area referred by GETI instruction
·
Data memory
· Data area : 512
×
4 bits (000H to 1FFH)
· Peripheral hardware area : 128
×
4 bits (F80H to FFFH)
14
µ
PD75108F,75112F,75116F
Fig. 4-1 Program Memory Map (
µ
PD75108F)
Remarks
Apart from the above instructions, branching is possible to an address at which only the PC low-order
8 bits have been changed by the BR PCDE or BR PCXA instruction.
MBE
0000H
0002H
0004H
0006H
0008H
000AH
0020H
007FH
0080H
07FFH
0800H
7
6
0
Address
Internal Reset Start Address (High-Order 5 Bits)
Internal Reset Start Address (Low-Order 8 Bits)
(High-Order 5 Bits)
INT0/INT1 Start Address (High-Order 5 Bits)
INTBT/INT4 Start Address (Low-Order 8 Bits)
INT0/INT1 Start Address (Low-Order 8 Bits)
INTSIO Start Address (High-Order 5 Bits)
INTSIO Start Address (Low-Order 8 Bits)
INTT0 Start Address (High-Order 5 Bits)
INTT0 Start Address (Low-Order 8 Bits)
INTT1 Start Address (High-Order 5 Bits)
INTT1 Start Address (Low-Order 8 Bits)
GETI Instruction Reference Table
CALLF
! faddr
Instruction
Entry
Address
BRCB
! caddr
Instruction
Branch
Address
BR ! addr
Instruction
Branch Address
RBE
MBE RBE
MBE RBE
MBE RBE
MBE RBE
MBE RBE
0FFFH
1000H
1F7FH
CALL ! addr
Instruction
Subroutine
Entry Address
BR $ addr
Instruction Relative
Branch Address
­15 to ­1,
+2 to +16
Branch Destination
Address and Subroutine
Entry Address by GETI
Instruction
BRCB !caddr
Instruction
Branch Address
0
0
0
0
0
0
INTBT/INT4 Start Address
5
15
µ
PD75108F,75112F,75116F
Fig. 4-2 Program Memory Map (
µ
PD75112F)
Remarks
Apart from the above instructions, branching is possible to an address at which only the PC low-order
8 bits have been changed by the BR PCDE or BR PCXA instruction.
MBE
0000H
0002H
0004H
0006H
0008H
000AH
0020H
007FH
0080H
07FFH
0800H
0FFFH
1000H
7
6
0
Address
Internal Reset Start Address (High-Order 6 Bits)
Internal Reset Start Address (Low-Order 8 Bits)
INTBT/INT4 Start Address (High-Order 6 Bits)
INT0/INT1 Start Address (High-Order 6 Bits)
INTBT/INT4 Start Address (Low-Order 8 Bits)
INT0/INT1 Start Address (Low-Order 8 Bits)
INTSIO Start Address (High-Order 6 Bits)
INTSIO Start Address (Low-Order 8 Bits)
INTT0 Start Address (High-Order 6 Bits)
INTT0 Start Address (Low-Order 8 Bits)
INTT1 Start Address (High-Order 6 Bits)
INTT1 Start Address (Low-Order 8 Bits)
GETI Instruction Reference Table
CALLF
! faddr
Instruction
Entry
Address
BRCB
! caddr
Instruction
Branch
Address
BR ! addr
Instruction
Branch Address
RBE
MBE
RBE
MBE
RBE
MBE
RBE
MBE
RBE
MBE
RBE
1FFFH
2000H
2F7FH
CALL ! addr
Instruction
Subroutine
Entry Address
BR $ addr
Instruction Relative
Branch Address
­15 to ­1,
+2 to +16
Branch Destination
Address and Subroutine
Entry Address by GETI
Instruction
BRCB !caddr
Instruction
Branch Address
BRCB !caddr
Instruction
Branch Address
16
µ
PD75108F,75112F,75116F
Fig. 4-3 Program Memory Map (
µ
PD75116F)
Remarks
Apart from the above instructions, branching is possible to an address at which only the PC low-order
8 bits have been changed by the BR PCDE or BR PCXA instruction.
MBE
0000H
0002H
0004H
0006H
0008H
000AH
0020H
007FH
0080H
07FFH
0800H
0FFFH
1000H
7
6
0
Address
Internal Reset Start Address (High-Order 6 Bits)
Internal Reset Start Address (Low-Order 8 Bits)
INTBT/INT4 Start Address (High-Order 6 Bits)
INT0/INT1 Start Address (High-Order 6 Bits)
INTBT/INT4 Start Address (Low-Order 8 Bits)
INT0/INT1 Start Address (Low-Order 8 Bits)
INTSIO Start Address (High-Order 6 Bits)
INTSIO Start Address (Low-Order 8 Bits)
INTT0 Start Address (High-Order 6 Bits)
INTT0 Start Address (Low-Order 8 Bits)
INTT1 Start Address (High-Order 6 Bits)
INTT1 Start Address (Low-Order 8 Bits)
GETI Instruction Reference Table
CALLF
! faddr
Instruction
Entry
Address
BRCB
! caddr
Instruction
Branch
Address
BR ! addr
Instruction
Branch Address
RBE
MBE
RBE
MBE
RBE
MBE
RBE
MBE
RBE
MBE
RBE
1FFFH
2000H
2FFFH
3000H
3F7FH
CALL ! addr
Instruction
Subroutine
Entry Address
BR $ addr
Instruction Relative
Branch Address
­15 to ­1,
+2 to +16
Branch Destination
Address and Subroutine
Entry Address by GETI
Instruction
BRCB !caddr
Instruction
Branch Address
BRCB !caddr
Instruction
Branch Address
BRCB !caddr
Instruction
Branch Address
17
µ
PD75108F,75112F,75116F
Fig. 4-4 Data Memory Map
256
×
4
256
×
4
128
×
4
(32
×
4)
Bank 0
Bank 1
Bank 15
000H
01FH
0FFH
100H
F80H
FFFH
General
Register Area
Stack Area
Data Area
Static RAM
(512
×
4)
Peripheral Hardware Area
Data Memory
Memory Bank
Not On-Chip
1FFH
18
µ
PD75108F,75112F,75116F
5.
PERIPHERAL HARDWARE FUNCTIONS
5.1
DIGITAL INPUT/OUTPUT PORTS
There are the following three digital input/output ports.
· CMOS input (PORT0, PORT1)
:
8
· CMOS input/output (PORT2 to PORT9)
:
32
· N-ch open-drain input/output (PORT12 to PORT14) :
12
Total
:
52
Table 5-1 List of Input/Output Pin Manipulation Commands
PORT 0
PORT 1
PORT 3
PORT 6
PORT 2
PORT 4
PORT 5
PORT 7
PORT 8
PORT 9
PORT12
PORT13
PORT14
Port Name
Function
Operation/Features
Remarks
4-bit input
4-bit input/output *
4-bit input/output *
(N-ch open-drain +10
V withstand voltage)
Regardless of the operating mode of the shared
pin, reading or test is always possible.
Can be set in the input or output bit-wise.
Can be set in the input or output mode as a 4-
bit unit. Ports 4 and 5, 6 and 7, and 8 and 9 are
paired and data input/output is possible as an
8-bit unit.
Can be set to input or output mode as a 4-bit
unit. Ports 12 and 13 are paired and data input/
output is possible as an 8-bit unit.
These pins are shared with SI,
SO, SCK, INT0 to INT4.
Port 2, PT00, PT01, and PCL share
the same pins.
On-chip pull-up resistor specifi-
able bit-wise by mask option.
*
Can drive a LED directly.
19
µ
PD75108,75112F,75116F
5.2
CLOCK GENERATOR
(1) Clock generator configuration
This is the circuit which generates various kinds of clock supplied to the CPU and peripheral hardware to control
the CPU operating mode.
This circuit can also change the instruction execution time.
·
0.95
µ
s/1.91
µ
s/15.3
µ
s (4.19 MHz operation)
Fig. 5-1 Clock Generator Block Diagram
Remarks
1.
f
XX
= Crystal/ceramic oscillator frequency
2.
f
X
= External clock frequency
3.
= CPU Clock
4.
* indicates instruction execution
5.
PCC : Processor clock control register
6.
One
clock cycle (t
CY
) is one machine cycle. See "AC
CHARACTERISTICS" in 12. "ELECTRICAL SPECIFICATIONS" for t
CY
.
X1
f
XX
or f
X
· Basic Interval Timer (BT)
· Clock Output Circuit
· Timer/Event Counter
· Serial Interface
Frequency Divider
1/2
Selector
HALT F/F
Wait Release Signal from BT
RESET Signal
Standby Release Signal from
Interrupt Control Circuit
STOP F/F
S
R
Q
PCC2,
PCC3
Clear
Oscil-
lation
Stop
PCC
4
Internal Bus
System Clock
Oscillation
Circuit
S
R
Q
HALT *
STOP *
Frequency
Divider
1/4
· CPU
· Clock Output Circuit
1/16
X2
1/8 to 1/4096
PCC0
PCC1
PCC2
PCC3
20
µ
PD75108F,75112F,75116F
5.3
CLOCK OUTPUT CIRCUIT
The clock output circuit is a circuit which outputs a clock pulse from P22/PCL and is used to supply clock pulses
to remote control outputs or peripheral LSI's.
·
Clock output (PCL) :
, 524 kHz, 262 kHz (4.19 MHz operation)
Fig. 5-2 Configuration of Clock Output Circuit
CLOM3
CLOM1 CLOM0
4
Internal Bus
CLOM
P22
Output Latch
PORT2.2
Bit 2 of PMGB
Bit Specified
in Port 2
Input/Output
Mode
Output Buffer
P22/PCL
f
XX
/2
3
f
XX
/2
4
Selector
From Clock
Generator
0
21
µ
PD75108,75112F,75116F
5.4
BASIC INTERVAL TIMER
The basic interval timer includes the following functions.
·
It operates as an interval timer which generates reference time interrupts.
·
It can be applied as a watchdog timer which detects when a program is out of control.
·
Selects and counts wait times when the standby mode is released.
·
It reads count contents.
Fig. 5-3 Basic Interval Timer Configuration
Remarks
* indicates instruction execution.
Internal Bus
f
XX
/2
5
f
XX
/2
7
f
XX
/2
12
From Clock
Generator
4
BTM3
BTM2
BTM1
BTM0
BTM
MPX
BT
IRQBT
Set
BT Interrupt
Request Flag
Clear
Clear
Basic Interval Timer
(8-Bit Frequency Divider)
Wait Release
Signal during
Standby Release
8
3
Vector
Interrupt
Request
Signal
f
XX
/2
9
*SET1
5.5
TIMER/EVENT COUNTER
The
µ
PD75116F incorporates two internal timer/event counter channels.
Timer/event counter channel 0 and channel 1 differ only in selectable count pulse (CP) and clock supply function
to serial interface and are the same in other configurations and functions.
The functions of the timer/event counter are as follows.
·
Operates as a programmable interval timer.
·
Outputs square waves in the desired frequency to the PTOn pin.
·
Operates as an event counter.
·
Use of TIn pin as an external interrupt input pin.
·
Divides the TIn pin input into N divisions and outputs it to the PTOn pin (frequency divider operation).
·
Supplies a serial shift clock to the serial interface circuit. (channel 0 only)
·
Count status read function.
22
µ
PD75108F
,75112F
,75116F
Fig. 5-4 Timer/Event Counter Block Diagram (n = 0, 1)
*
1. SET1 : Instruction execution.
2. For details, see Fig. 5-1.
3. The serial interface signal is output only from timer/event counter channel 0.
From Clock
Generator
Input Buffer
*2
MPX
TMn6
SET1
*1
TMn
Timer Operation Start
CP
Count Register (8)
Clear
8
Comparator (8)
8
8
Modulo Register (8)
8
8
Internal Bus
TMODn
Match
TOUT
F/F
TOEn
TO
Enable
Flag
P2n
Output
Latch
PORT2.n
Bit 2 of PGMB
Port 2
Input/
Output
Mode
To Serial
Interface*3
P2n/PTOn
Output
Buffer
INTTn
(IRQTn Set Signal)
IRQTn
Clear Signal
Tn
TIn
TIn
TMn7
TMn5 TMn4 TMn3 TMn2 TMn1 TMn0
TOn
TO
Selector
Edge
Detector
TMn0
RESET
TMn1
TOFn
23
µ
PD75108,75112F,75116F
5.6
SERIAL INTERFACE
The
µ
PD75116F incorporates the clocked 8-bit serial interface. There are the following two modes of serial
interface.
· 3-wire serial I/O mode (MSB-first/LSB-first switchable)
· Operation stop mode
In the 3-wire serial I/O mode, the
µ
PD75116F can be connected with the 75X series, 78K series and various kinds
of I/O devices.
24
µ
PD75108F
,75112F
,75116F
*
SET1 : instruction execution
Fig. 5-5 Serial Interface Block Diagram
Shift Registor (8)
Serial Clock
Counter (3)
Clear
Overflow
Serial Start
SIOM7 SIOM6 SIOM5 SIOM4 SIOM3 SIOM2 SIOM1 SIOM0
SIOM
SET1 *
8
8
8
P03/SI
P02/SO
P01/SCK
SIO7
SIO
SIO0
IRQSIO
Clear Signal
TOF0
(from Timer Channel 0)
f
xx
/2
10
f
xx
/2
4
MPX
R
S
Q
Internal Bus
INTSIO
IRQSIO
Set Signal
25
µ
PD75108,75112F,75116F
5.7
PROGRAMMABLE THRESHOLD PORT (ANALOG INPUT PORT)
The
µ
PD75116F is provided with 4-bit analog input pins (PTH00 to PTH03) for which the threshold voltage can
be changed. These pins have a configuration as shown in Fig. 5-6.
The threshold voltage (V
REF
) can be selected in 16 ways (V
DD
×
------ -- V
DD
×
------) and analog signals can be
directly input.
This port can also be used as a digital signal input port by selecting V
DD
×
7.5/16 as V
REF
.
Fig. 5-6 Programmable Threshold Port Block Diagram
16
16
0.5
15.5
PTHM7
PTHM6
PTHM5
PTHM4
PTHM3
PTHM2
PTHM1
PTHM0
PTHM
4
MPX
V
REF
V
DD
PTH00
PTH01
PTH02
PTH03
+
-
+
-
+
-
+
-
Operation
Stopped
PTH0
Input Buffer
Programmable Threshold
Port Input Latch (4)
Internal Bus
8
2
1
R
2
1
R
R
R
26
µ
PD75108F,75112F,75116F
5.8
BIT SEQUENTIAL BUFFER ······ 16 BITS
Bit manipulation of the bit sequential buffer is the bit manipulation special data memory. Since, in particular,
the bit manipulation can easily be performed by changing sequentially address and bit specification, it is convenient
when processing data comprising a large number of bits bit-wise.
Fig. 5-7 Bit Sequential Buffer Format
Remarks
In pmem. @L addressing, the specified bit moves according to the L register.
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
L = 0
L = 3
L = 4
DECS L
L = 7
L = 8
INCS L
L = B
L = C
L = F
FC3H
FC2H
FC1H
FC0H
Symbol
Address
L Register
BSB3
BSB2
BSB1
BSB0
Bit
27
µ
PD75108F,75112F,75116F
6.
INTERRUPT FUNCTION
The
µ
PD75116F has 7 interrupt sources. Multiple interrupts with priority is are also possible.
Two test sources are also provided. The test sources are edge detection testable inputs.
Table 6-1 Interrupt Sources
INTBT (standard time interval signal from
basic interval timer)
INT4
(both rising edge and falling edge
detection)
INT0
INT1
INTT0
(match signal from timer/event
counter# 0 or TI0 input edge detection)
INTT1
(match signal from timer/event
counter# 1 or TI1 input edge detection)
INT2*2 (rising edge detection)
INT3*2 (rising edge detection)
Vector Interrupt Request
Signal
(Vector Table Address)
(rising edge and falling edge
detection selection)
Internal
External
1
2
Interrupt Order*1
Internal/External
Interrupt Source
External
External
VRQ1
(0002H)
VRQ3
(0006H)
INTSIO (serial data transfer end signal)
Internal
Internal/external
Internal/external
3
4
5
VRQ4
(0008H)
VRQ5
(000AH)
VRQ2
(0004H)
External
Testable input signal
(Set IRQ2 and IRQ3)
*
1. The interrupt order is the priority order when multiple interrupt requests are generated simultaneously.
2. INT2 and INT3 are of test sources . These are affected by interrupt enable flags in the same way as interrupt
sources, but do not generate vector interrupts.
The
µ
PD75116F interrupt control circuit has the following functions:
·
Hardware control vector interrupt function that can control interrupt acceptance by interrupt enable flag (IE
×××
)
and interrupt master enable flag (IME).
·
Arbitrary setting of interrupt start address.
·
Multiple interruption function by which priority can be specified using the interrupt priority selection register
(IPS).
·
Interrupt request flag (IRQ
×××
) test function (interrupt generation confirmation by software possible).
·
Standby mode release (selection of interrupt that releases the standby mode by interrupt enable flag possible).
28
µ
PD75108F
,75112F
,75116F
Fig. 6-1 Interrupt Control Circuit Block Diagram
2
2
IM1
IM0
IRQBT
INT4
/P00
INT0
/P10
INT1
/P11
INT2
/P12
IRQ4
IRQ0
IRQ1
IRQSIO
IRQT0
IRQT1
IRQ2
INT
BT
INTSIO
INTT0
INTT1
(IME)
IST
Internal Bus
Vector
Table
Address
Generator
Priority Control
Circuit
Standby Release
Signal
Interrupt Enable Flag (IE
XXX
)
Edge
Detection
Circuit
Edge
Detection
Circuit
Decoder
IPS
4
2
INT3
/P13
Edge
Detection
Circuit
Edge
Detection
Circuit
Interrupt
Request
Flag
9
IRQ3
Edge
Detection
Circuit
29
µ
PD75108F,75112F,75116F
7.
STANDBY FUNCTION
To reduce the power consumption during program wait, the
µ
PD75116F has two standby modes (STOP mode
and HALT mode).
Table 7-1 Standby Mode Setting and Operation Status
Interrupt request signal from operable hardware enabled by interrupt enable flag, or
RESET input
STOP Mode
STOP instruction
System clock oscillation stopped
Operation possible only when the
external SCK input and TO0 output
(when timer/event counter 0 is external
TI0 input) are selected as a serial clock
Operable only when TIn pin input
specified as count clock
Operation stopped
Operation of INT0 to INT4 possible
Operation stopped
Setting instruction
Clock generator circuit
Basic interval timer
O
peration Status
HALT Mode
HALT instruction
Only CPU clock
stopped
Operable
(IRQBT set at reference time intervals)
Operation possible if a clock other than
is specified as a serial clock
Except CPU clock
, output possible.
Operation stopped
Serial interface
Timer/event counter
Clock output circuit
External interrupt
CPU
Operation possible
Release signal
Operation stopped
30
µ
PD75108F,75112F,75116F
8.
RESET FUNCTION
The reset operation timing is shown in Fig. 8-1.
Fig. 8-1 Reset Operation by RESET Input
The state of hardware after reset operation is as shown in Table 8-1.
Wait
(Approx. 31.3 ms: 4.19 MHz)
HALT Mode
Operating Mode
Internal Reset Operation
Operating Mode or Standby
Mode
RESET Input
31
µ
PD75108F,75112F,75116F
RESET Input in Standby
Mode
Table 8-1 Status of Each Hardware after Resetting
Hardware
Low-order 5 bits of program
memory address 0000H are set
in PC
12
to PC
8
and the contents
of address 0001H are set in PC
7
to PC
0
.
Low-order 6 bits of program
memory address 0000H are set
in PC
13
to PC
8
and the contents
of address 0001H are set in PC
7
to PC
0
.
Held
0
0
Sets program memory address
0000H bit 6 and bit 7 to RBE and
MBE, respectively.
Undefined
Held*
Held
0, 0
Undefined
0
0
FFH
0
0, 0
Held
0
0
0
Reset (0)
0
0
0, 0
OFF
Clear (0)
0
Undefined
0
0
RESET Input during
Operation
Undefined
0
0
Same as left
Undefined
Undefined
Undefined
0, 0
Undefined
0
0
FFH
0
0, 0
Undefined
0
0
0
Reset (0)
0
0
0, 0
OFF
Clear (0)
0
Undefined
0
0
Carry flag (CY)
Skip flag (SK0 to SK2)
Interrupt status flag (IST0, IST1)
Bank enable flag (MBE, RBE)
Stack pointer (SP)
Data memory (RAM)
General register (X, A, H, L, D, E, B, C)
Bank selection register (MBS, RBS)
PSW
Counter (BT)
Mode register (BTM)
Counter (Tn)
Modulo register (TMODn)
Mode register (TMn)
TOEn, TOFn
Shift register (SIO)
Mode register (SIOM)
Processor clock control register (PCC)
Clock output mode register (CLOM)
Interrupt request flag (IRQ
×××
)
Interrupt enable flag (IE
×××
)
Priority selection register (IPS)
INT0, 1 mode registers (IM0, IM1)
Output buffer
Output latch
I/O mode register (PMGA, B, C)
PTH00 to 03 input latch
Mode register (PTHM)
Bit sequential buffer (BSB0 to BSB3)
Basic interval
timer
Timer/event
counter
(n = 0, 1)
Serial interface
Clock generator,
clock output
circuit
Interrupt
Digital port
Analog port
µ
PD75108F
µ
PD75112F
µ
PD75116F
*
Data of data memory addresses 0F8H to 0FDH becomes undefined by RESET input.
Same as left
Program counter (PC)
32
µ
PD75108F,75112F,75116F
Identifier
Description
reg
X, A, B, C, D, E, H, L
reg1
X, B, C, D, E, H, L
rp
XA, BC, DE, HL
rp1
BC, DE, HL
rp2
BC, DE
rp'
XA, BC, DE, HL, XA', BC', DE', HL'
rp'1
BC, DE, HL, XA', BC', DE', HL'
rpa
HL, HL+, HL-, DE, DL
rpa1
DE, DL
n4
4-bit immediate data or label
n8
8-bit immediate data or label
mem
8-bit immediate data or label*
bit
2-bit immediate data or label
fmem
FB0H to FBFH, FF0H to FFFH immediate data or label
pmem
FC0H to FFFH immediate data or label
µ
PD75108F
0000H to 1F7FH immediate data or label
addr
µ
PD75112F
0000H to 2F7FH immediate data or label
µ
PD75116F
0000H to 3F7FH immediate data or lebel
caddr
12-bit immediate data or label
faddr
11-bit immediate data or label
taddr
20H to 7FH immediate data (however, bit0 = 0) or label
PORTn
PORT 0 to PORT 9, PORT12 to PORT14
IE
×××
IEBT, IESIO, IET0, IET1, IE0 to IE4
RBn
RB0 to RB3
MBn
MB0, MB1, MB15
9.
INSTRUCTION SET
(1) Operand identifier and description
The operand is described in the operand field of each instruction in accordance with the description for the
operand identifier of the instruction. (For details, refer to RA75X Assembler Package User's Manual Language
Volume (EEU-730).) When there are multiple elements in the description, one of the elements is selected. Upper
case letters and symbols (+,­) are keywords and are described unchanged.
Various register or flag symbols can be used as a label instead of mem, fmem, pmem, bit, etc. (For details, refer
to
µ
PD75116 User's Manual (IEM-922).) However, there are restrictions on the labels for which fmem and pmem
can be used.
*
In the case of the 8-bit data processing, an even address only can be described for mem.
33
µ
PD75108F,75112F,75116F
(2) Operation description legend
A
: A register; 4-bit accumulator
B
: B register
C
: C register
D
: D register
E
: E register
H
: H register
L
: L register
X
: X register
XA
: Register pair (XA); 8-bit accumulator
BC
: Register pair (BC)
DE
: Register pair (DE)
HL
: Register pair (HL)
XA'
: Extension register pair (XA')
BC'
: Extension register pair (BC')
DE'
: Extension register pair (DE')
HL'
: Extension register pair (HL')
PC
: Program counter
SP
: Stack pointer
CY
: Carry flag; bit accumulator
PSW
: Program status word
MBE
: Memory bank enable flag
RBE
: Register bank enable flag
PORTn
: Portn (n = 0 to 9, 12 to 14)
IME
: Interrupt master enable flag
IPS
: Interrupt priority selection register
IE
×××
: Interrupt enable flag
RBS
: Register bank selection register
MBS
: Memory bank selection register
PCC
: Processor clock control register
.
: Address, bit delimiter
(
××
)
: Contents addressed by
××
××
H
: Hexadecimal data
34
µ
PD75108F,75112F,75116F
(3) Description of addressing area field symbols
*1
*2
Data memory
addressing
*3
*4
*5
*6
MB = MBE · MBS (MBS = 0, 1, 15)
MB = 0
MBE = 0 : MB = 0 (00H to 7FH)
MB = 15 (80H to FFH)
MBE = 1 : MB = MBS (MBS = 0, 1, 15)
MB = 15, fmem = FB0H to FBFH,
FF0H to FFFH
MB = 15, pmem = FC0H to FFFH
µ
PD75108F : addr = 0000H to 1F7FH
µ
PD75112F : addr = 0000H to 2F7FH
µ
PD75116F : addr = 0000H to 3F7FH
addr = (Current PC) ­15 to
(Current PC) + 16
µ
PD75108F : caddr = 0000H to 0FFFH (PC
12
= 0) or
= 1000H to 1F7FH (PC
12
= 1)
µ
PD75112F : caddr = 0000H to 0FFFH (PC
13
, PC
12
= 00B) or
= 1000H to 1FFFH (PC
13
, PC
12
= 01B) or
= 2000H to 2F7FH (PC
13
, PC
12
= 10B)
µ
PD75116F : caddr = 0000H to 0FFFH (PC
13
, PC
12
= 00B) or
= 1000H to 1FFFH (PC
13
, PC
12
= 01B) or
= 2000H to 2FFFH (PC
13
, PC
12
= 10B) or
= 3000H to 3F7FH (PC
13
, PC
12
= 11B)
faddr = 0000H to 07FFH
taddr = 0020H to 007FH
*7
*8
*9
*10
Program memory
addressing
Remarks
1.
MB indicates the accessible memory bank.
2.
For *2, MB = 0 without regard to MBE and MBS.
3.
For *4 and *5, MB = 15 without regard to MBE and MBS.
4.
*6 to *10 indicate the addressable area.
(4) Explanation of machine cycle field
S shows the number of machine cycles required when skip is performed by an instruction with skip. The value
of S changes as follows:
· No skip ....................................................................................................................................................................... S = 0
· When instruction to be skipped is 1-byte or 2-byte instruction ......................................................................... S = 1
· When instruction to be skipped is 3-byte instruction (BR !addr, CALL !addr instructions) ........................... S = 2
Note
One machine cycle is required to skip a GETI instruction.
One machine cycle is equivalent to one cycle (= t
CY
) of the CPU clock
. Three times can be selected by PCC setting.
35
µ
PD75108F,75112F,75116F
A, #n4
reg1, #n4
XA, #n8
HL, #n8
rp2, #n8
A, @HL
A, @HL+
A, @HL-
A, @rpa1
XA, @HL
@HL, A
@HL, XA
A, mem
XA, mem
mem, A
mem, XA
A, reg
XA, rp'
reg1, A
rp'1, XA
A, @HL
A, @HL+
A, @HL-
A, @rpa1
XA, @HL
A, mem
XA, mem
A,reg1
XA, rp'
XA, @PCDE
XA, @PCXA
1
2
2
2
2
1
1
1
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
2
2
2
1
2
1
1
1
2
2
2
2
1
2 + S
2 + S
1
2
1
2
2
2
2
2
2
2
2
2
1
2 + S
2 + S
1
2
2
2
1
2
3
3
A
n4
reg1
n4
XA
n8
HL
n8
rp2
n8
A
(HL)
A
(HL), then L
L + 1
A
(HL), then L
L ­ 1
A
(rpa1)
XA
(HL)
(HL)
A
(HL)
XA
A
(mem)
XA
(mem)
(mem)
A
(mem)
XA
A
reg
XA
rp'
reg1
A
rp'1
XA
A
(HL)
A
(HL), then L
L + 1
A
(HL), then L
L ­ 1
A
(rpa1)
XA
(HL)
A
(mem)
XA
(mem)
A
reg1
XA
rp'
·
µ
PD75108F
XA
(PC
12-8
+ DE)
ROM
·
µ
PD75112F, 75116F
XA
(PC
13-8
+ DE)
ROM
·
µ
PD75108F
XA
(PC
12-8
+ XA)
ROM
·
µ
PD75112F, 75116F
XA
(PC
13-8
+ XA)
ROM
Skip
Condition
Stack A
Stack A
Stack B
L = 0
L = FH
L = 0
L = FH
*1
*1
*1
*2
*1
*1
*1
*3
*3
*3
*3
*1
*1
*1
*2
*1
*3
*3
Transfer
Table Reference
Mnemonic
Operands
Bytes Machine
Cycles
Operation
Instruction Group
MOVT
Addressing
Area
XCH
MOV
36
µ
PD75108F,75112F,75116F
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
fmem.bit, CY
pmem.@L, CY
@H+mem.bit, CY
A, #n4
XA, #n8
A, @HL
XA, rp'
rp'1, XA
A, @HL
XA, rp'
rp'1, XA
A, @HL
XA, rp'
rp'1, XA
A, @HL
XA, rp'
rp'1, XA
A, #n4
A, @HL
XA, rp'
rp'1, XA
A, #n4
A, @HL
XA, rp'
rp'1, XA
A, #n4
A, @HL
XA, rp'
rp'1, XA
CY
(fmem.bit)
CY
(pmem
7 ­ 2
+ L
3 ­ 2
.bit(L
1­0
))
CY
(H + mem
3 ­ 0
.bit)
(fmem.bit)
CY
(pmem
7 ­ 2
+ L
3 ­ 2
.bit(L
1­0
))
CY
(H + mem
3 ­ 0
.bit)
CY
A
A + n4
XA
XA + n8
A
A + (HL)
XA
XA + rp'
rp'1
rp'1 + XA
A, CY
A + (HL) + CY
XA, CY
XA + rp' + CY
rp'1, CY
rp'1 + XA + CY
A
A ­ (HL)
XA
XA ­ rp'
rp'1
rp'1 ­ XA
A, CY
A ­ (HL) ­ CY
XA, CY
XA ­ rp' ­ CY
rp'1, CY
rp'1 ­ XA ­ CY
A
A
n4
A
A
(HL)
XA
XA
rp'
rp'1
rp'1
XA
A
A
n4
A
A
(HL)
XA
XA
rp'
rp'1
rp'1
XA
A
A
n4
A
A
(HL)
XA
XA
rp'
rp'1
rp'1
XA
Skip
Condition
Operands
Bytes
Machine
Cycles
Operation
Addressing
Area
*4
*5
*1
*4
*5
*1
*1
*1
*1
*1
*1
*1
*1
carry
carry
carry
carry
carry
borrow
borrow
borrow
Instruction
Group
Mnemonic
MOV1
Bit
transfer
ADDS
2
2
2
2
2
2
1
2
1
2
2
1
2
2
1
2
2
1
2
2
2
1
2
2
2
1
2
2
2
1
2
2
ADDC
SUBC
AND
Operations
2
2
2
2
2
2
1 + S
2 + S
1 + S
2 + S
2 + S
1
2
2
1 + S
2 + S
2 + S
1
2
2
2
1
2
2
2
1
2
2
2
1
2
2
SUBS
OR
XOR
37
µ
PD75108F,75112F,75116F
A
A
reg
rp1
@HL
mem
reg
rp'
reg, #n4
@HL, #n4
A, @HL
XA, @HL
A, reg
XA, rp'
CY
CY
CY
CY
mem.bit
fmem.bit
pmem.@L
@H + mem.bit
mem.bit
fmem.bit
pmem.@L
@H + mem.bit
mem.bit
fmem.bit
pmem.@L
@H + mem.bit
mem.bit
fmem.bit
pmem.@L
@H + mem.bit
fmem.bit
pmem.@L
@H + mem.bit
Operands
Operation
Instruction
Group
Mne-
monic
Bytes
1
2
1
1
2
2
1
2
2
2
1
2
2
2
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Machine
Cycles
CY
A
0
, A
3
CY, A
n­1
A
n
A
A
reg
reg + 1
rp1
rp1 + 1
(HL)
(HL) + 1
(mem)
(mem) + 1
reg
reg ­ 1
rp'
rp' ­ 1
Skip if reg = n4
Skip if (HL) = n4
Skip if A = (HL)
Skip if XA = (HL)
Skip if A = reg
Skip if XA = rp'
CY
1
CY
0
Skip if CY = 1
CY
CY
(mem.bit)
1
(fmem.bit)
1
(pmem
7­2
+ L
3­2
.bit (L
1­0
))
1
(H + mem
3­0
.bit)
1
(mem.bit)
0
(fmem.bit)
0
(pmem
7­2
+ L
3­2
.bit (L
1­0
))
0
(H + mem
3­0
.bit)
0
Skip if (mem.bit) = 1
Skip if (fmem.bit) = 1
Skip if (pmem
7­2
+ L
3­2
.bit (L
1­0
)) = 1
Skip if (H + mem
3­0
.bit) = 1
Skip if (mem.bit) = 0
Skip if (fmem.bit) = 0
Skip if (pmem
7­2
+ L
3­2
.bit (L
1­0
)) = 0
Skip if (H + mem
3­0
.bit) = 0
Skip if (fmem.bit) = 1 and clear
Skip if (pmem
7­2
+ L
3­2
.bit (L
1­0
))
= 1 and clear
Skip if (H + mem
3­0
.bit)
= 1 and clear
Addressing
Area
Skip Condition
reg = 0
rp1 = 00H
(HL) = 0
(mem) = 0
reg = FH
rp' = FFH
reg = n4
(HL) = n4
A = (HL)
XA = (HL)
A = reg
XA = rp'
CY = 1
(mem.bit) = 1
(fmem.bit) = 1
(pmem.@L) = 1
(@H + mem.bit) = 1
(mem.bit) = 0
(fmem.bit) = 0
(pmem.@L) = 0
(@H + mem.bit) = 0
(fmem.bit) = 1
(pmem.@L) = 1
(@H + mem.bit) = 1
1
2
1 + S
1 + S
2 + S
2 + S
1 + S
2 + S
2 + S
2 + S
1 + S
2 + S
2 + S
2 + S
1
1
1 + S
1
2
2
2
2
2
2
2
2
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
RORC
*1
*3
*1
*1
*1
*3
*4
*5
*1
*3
*4
*5
*1
*3
*4
*5
*1
*3
*4
*5
*1
*4
*5
*1
Accumulator
manipulation
NOT
INCS
Increment
/decrement
DECS
SKE
Comparison
SET1
CLR1
SKT
NOT1
Carry flag
manipulation
SET1
Memory bit
manipulation
CLR1
SKT
SKF
SKTCLR
38
µ
PD75108F,75112F,75116F
CY
CY
(fmem.bit)
CY
CY
(pmem
7­2
+ L
3­2
.bit (L
1­0
))
CY
CY
(H + mem
3­0
.bit)
CY
CY
(fmem.bit)
CY
CY
(pmem
7­2
+ L
3­2
.bit (L
1­0
))
CY
CY
(H + mem
3­0
.bit)
CY
CY
(fmem.bit)
CY
CY
(pmem
7­2
+ L
3­2
.bit (L
1­0
))
CY
CY
(H + mem
3­0
.bit)
·
µ
PD75108F
PC
12­0
addr
(The assembler selects the optimum in-
struction from among the BR !addr, BRCB
!caddr, and BR $addr instructions.)
·
µ
PD75112F, 75116F
PC
13­0
addr
(The assembler selects the optimum in-
struction from among the BR !addr, BRCB
!caddr, and BR $addr instructions.)
·
µ
PD75108F
PC
12-0
addr
·
µ
PD75112F, 75116F
PC
13-0
addr
·
µ
PD75108F
PC
12-0
addr
·
µ
PD75112F, 75116F
PC
13-0
addr
·
µ
PD75108F
PC
12-0
PC
12
+ caddr
11-0
·
µ
PD75112F, 75116F
PC
13-0
PC
13
, PC
12
+ caddr
11-0
·
µ
PD75108F
PC
12-0
PC
12-8
+ DE
·
µ
PD75112F, 75116F
PC
13-0
PC
13-8
+ DE
·
µ
PD75108F
PC
12-0
PC
12-8
+ XA
·
µ
PD75112F, 75116F
PC
13-0
PC
13-8
+ XA
·
µ
PD75108F
(SP-4) (SP-1) (SP-2)
PC
11-0
(SP-3)
MBE, RBE, 0, PC
12
PC
12-0
addr, SP
SP­4
·
µ
PD75112F, 75116F
(SP-4) (SP-1) (SP-2)
PC
11-0
(SP-3)
MBE, RBE, PC
13
, PC
12
PC
13-0
addr, SP
SP­4
Instruction
Group
Mne-
monic
Branch
CY, fmem.bit
CY, pmem.@L
CY, @H + mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H + mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H + mem.bit
addr
!addr
$addr
!caddr
PCDE
PCXA
!addr
Bytes Machine
Cycles
Addressing
Area
Skip
Condition
Operation
Operands
*4
*5
*1
*4
*5
*1
*4
*5
*1
*6
*6
*7
*8
*6
AND1
Memory bit
manipulation
XOR1
2
2
2
2
2
2
2
2
2
--
3
2
2
3
3
3
2
2
2
2
2
2
2
2
2
--
3
1
2
2
2
3
Subroutine
stack control
OR1
BR
BRCB
BR
CALL
39
µ
PD75108F,75112F,75116F
·
µ
PD75108F
(SP ­ 4) (SP ­ 1) (SP ­ 2)
PC
11­0
(SP ­ 3)
MBE, RBE, 0, PC
12
PC
12­0
00, faddr, SP
SP ­ 4
·
µ
PD75112F, 75116F
(SP ­ 4) (SP ­ 1) (SP ­ 2)
PC
11­0
(SP ­ 3)
MBE, RBE, PC
13
, PC
12
PC
13­0
000, faddr, SP
SP ­ 4
·
µ
PD75108F
MBE, RBE,
×
, PC
12
(SP + 1)
PC
11­0
(SP) (SP + 3) (SP + 2)
SP
SP + 4
·
µ
PD75112F, 75116F
MBE, RBE, PC
13
, PC
12
(SP + 1)
PC
11­0
(SP) (SP + 3) (SP + 2)
SP
SP + 4
·
µ
PD75108F
MBE, RBE,
×
, PC
12
(SP + 1)
PC
11­0
(SP) (SP + 3) (SP + 2)
SP
SP + 4, then skip unconditionally
·
µ
PD75112F, 75116F
MBE, RBE, PC
13
, PC
12
(SP + 1)
PC
11­0
(SP) (SP + 3) (SP + 2)
SP
SP + 4, then skip unconditionally
·
µ
PD75108F
MBE, RBE,
×
, PC
12
(SP + 1)
PC
11­0
(SP) (SP + 3) (SP + 2)
PSW
(SP + 4) (SP + 5 ), SP
SP + 6
·
µ
PD75112F, 75116F
MBE, RBE, PC
13
, PC
12
(SP + 1)
PC
11­0
(SP) (SP + 3) (SP + 2)
PSW
(SP + 4) (SP + 5 ), SP
SP + 6
(SP ­ 1) (SP ­ 2)
rp, SP
SP ­ 2
(SP ­ 1)
MBS, (SP ­ 2)
RBS, SP
SP ­ 2
rp
(SP + 1) (SP), SP
SP + 2
MBS
(SP + 1), RBS
(SP), SP
SP + 2
IME (IPS.3)
1
IE
×××
1
IME (IPS.3)
0
IE
×××
0
Operation
Instruction
Group
Mne-
monic
Skip Condition
Operands Bytes Machine
Cycles
Addressing
Area
*9
2
2
!faddr
3
1
CALLF
RET
3 + S
1
RETS
Subroutine
stack control
RETI
3
1
PUSH
POP
EI
DI
rp
BS
rp
BS
IE
×××
IE
×××
1
2
1
2
2
2
2
2
1
2
1
2
2
2
2
2
Unconditional
Interrupt
control
40
µ
PD75108F,75112F,75116F
Operation
Instruction
Group
Mne-
monic
Skip Condition
Operands
Addressing
Area
------------------------
Bytes Machine
Cycles
2
2
2
2
2
2
1
2
2
2
2
2
2
2
2
1
2
2
A
PORTn
(n = 0 to 9, 12 to 14)
XA
PORTn
+ 1
, PORTn (n = 4, 6, 8, 12)
PORTn
A
(n = 2 to 9, 12 to 14)
PORTn
+ 1
, PORTn
XA (n = 4, 6, 8, 12)
Set HALT Mode (PCC.2
1)
Set STOP Mode (PCC.3
1)
No Operation
RBS
n
(n = 0 to 3)
MBS
n (n = 0, 1, 15)
·
µ
PD75108F
TBR Instruction
PC
12­0
(taddr)
4­0
(taddr + 1)
TCALL Instruction
(SP ­ 4) (SP ­ 1) (SP ­ 2)
PC
11­0
(SP ­ 3)
MBE, RBE, 0, PC
12
PC
12­0
(taddr)
4­0
(taddr + 1)
SP
SP ­ 4
Other than TBR and TCALL Instruction
Execution of an instruction addressed
at (taddr) and (taddr + 1)
·
µ
PD75112F, 75116F
TBR Instruction
PC
13­0
(taddr)
5­0
(taddr + 1)
TCALL Instruction
(SP ­ 4) (SP ­ 1) (SP ­ 2)
PC
11­0
(SP ­ 3)
MBE, RBE, 0, PC
13
, PC
12
PC
13­0
(taddr)
5­0
(taddr + 1)
SP
SP ­ 4
Other than TBR and TCALL Instruction
Execution of an instruction addressed
at (taddr) and (taddr + 1)
A, PORTn
XA, PORTn
PORTn, A
PORTn, XA
RBn
MBn
*1
HALT
STOP
NOP
IN
*1
OUT
Input/output
CPU control
SELL
----------------------------------------------------------
----------------------------------------------------------
*10
----------------------------------------------------------
3
1
taddr
*2
GETI
Special
----------------------------------------------------------
-----------------------
Conforms to
referenced
instruction.
Conforms to
referenced
instruction.
*
1. When executing the IN/OUT instruction, <MBE = 0> or <MBE = 1, MBS = 15> must be set.
2. The TBR or TCALL instruction is a GETI instruction table definition assembler pseudo-instruction.
41
µ
PD75108F
,75112F
,75116F
Power Amp
IDC
Amp
Compres-
sion
Transmitter/
Receiver
Extension
MPX
MSK
Modem
Speaker
Speaker
Amp
LED Display
Key Matrix
LED
Display
LCD
Controller/
Driver
Console
Detection
ID ROM
SIO
Radio Wave
Detection
Extra-Area
Detection
TCXO
PLL
VCO
Prescaler
PLL
VCO
Prescaler
MPX
Mixer
2SC4226
1SS281
3SK177
Filter
Amp
2SC2757
2SC4182
10.
APPLICATION EXAMPLE
10.1
CORDLESS TELEPHONE (SUBSET)
Legend
IDC
:
Immediate Deviation Controller,
ID ROM
:
ID (Identification) Code ROM, LCD
:
Liquid Crystal Display,
LED
:
Light Emitting Diode,
MPX
:
Multiplexer,
MSK
:
Minimum Shift Keying,
PLL
:
Phase Locked Loop,
SIO
:
Serial Data Input/Output,
TCXO
:
Temperature Compensation Crystal Oscillator,
VCO
:
Voltage Control Oscillator
µ
PD2840
µ
PD2841
µ
PD6130
µ
PD6131
µ
PD6252
µ
PD7228
µ
PD75116F
42
µ
PD75108F,75112F,75116F
Filter
INT
TO
Code ROM
Piezoelectric
Buzzer
Comparator
Input
High-Current
Output
LED Display
Switch
RAM
PD446
Battery Check
LCD Display
LCD Controller/Driver
PD7228/7229
SIO
PD75116F
µ
µ
µ
10.2 DISPLAY PAGER
43
µ
PD75108F,75112F,75116F
11. MASK OPTION SELECTION
The
µ
PD75116F has the following mask option to select whether or not a pull-up resistor is incorporated.
Pin
Mask Option
P120 to P123
P130 to P133
Pull-up resistor can be incorporated bit-wise.
P140 to P143
44
µ
PD75108F,75112F,75116F
12. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25
°
C)
PARAMETER
SYMBOL
TEST CONDITIONS
RATING
UNIT
Except ports 12, 13 and 14
­0.3 to V
DD
+0.3
V
Input voltage
Internal pull-up resistor
­0.3 to V
DD
+0.3
V
Ports 12 to 14
Open­drain
­0.3 to +11
V
Output voltage
­0.3 to V
DD
+0.3
V
One pin
­15
mA
All pins
­30
mA
Peak value
30
mA
One pin
Effective value
15
mA
Peak value
100
mA
Output current low
Effective value
60
mA
Peak value
100
mA
Total of ports 5 to 9
Effective value
60
mA
Operating
temperature
Storage
temperature
*
1. When a voltage exceeding 10V is applied to ports 12, 13 and 14, the power supply impedance (pull-up resistor)
should be 50K
or more.
2. Effective value should be calculated: [Effective value] = [Peak value]
×
duty
Note
Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even
momentarily.
The absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the product must be used under conditions which ensure that the absolute
maximum ratings are not exceeded.
Supply voltage
­0.3 to +5.5
V
V
I1
V
I2
*1
V
O
I
OH
I
OL
*2
T
opt
T
stg
V
DD
­40 to +60
°
C
­65 to +150
°
C
Output current
high
Total of ports 0, 2 to 4, 12 to
14
45
µ
PD75108F,75112F,75116F
12.1 WHEN Ta = ­40 to +50
°
C, V
DD
= 2.7 to 5.0 V
OPERATING VOLTAGE (Ta = ­40 to +50
°
C)
CPU*1
Programmable threshold port
(comparator input)
Other hardware*1
*2
5.0
V
4.5
5.0
V
2.7
5.0
V
PARAMETER
TEST CONDITIONS
MIN.
MAX.
UNIT
*
1. Except system clock oscillation circuit, programmable threshold port.
2. The operable supply voltage range depends on the cycle time. See "AC CHARACTERISTICS".
OSCILLATION CIRCUIT CHARACTERISTICS (Ta = ­40 to +50
°
C, V
DD
= 2.7 to 5.0 V)
RECOMMENDED
TEST
RESONATOR
PARAMETER
MIN.
TYP.
MAX.
UNIT
CONSTANT
CONDITIONS
Ceramic
resonator
After V
DD
reaches
MIN. of oscillation
voltage range
Crystal
resonator
External
clock
2.0
5.0*3
MHz
4
ms
2.0
4.19
5.0*3
MHz
V
DD
= 4.5 to 5.0 V
10
ms
30
ms
2.0
5.0*3
MHz
100
250
ns
Oscillator
frequency (f
XX
)*1
Oscillation
stabilization time*2
Oscillator
frequency (f
XX
)*1
Oscillation
stabilization time*2
X1 input
frequency (f
X
)*1
X1 input
high-/low-level width
(t
XH
, t
XL
)
X1
X2
µ
PD74HCU04
V
DD
= Oscillation
voltage range
X1
X2
C1
C2
X1
X2
C1
C2
*
1. Oscillator frequency and X1 input frequency indicate oscillation circuit characteristics only. See AC
CHARACTERISTICS for instruction execution time.
2. The oscillation stabilization time is the time required for oscillation to stabilize after V
DD
reaches MIN. of
oscillation voltage range or the STOP mode is released.
3. When the oscillator frequency is 4.19 MHz < f
XX
5.0 MHz, PCC = 0011 should not be selected as the instruction
execution time. If PCC = 0011 is selected, one machine cycle is less than 0.95
µ
s and the rated MIN. value
of 0.95
µ
s is not observed.
Note
When the clock oscillator is used, the following should be noted concerning wiring in the area in the figure
enclosed by a dotted line to prevent the influence of wiring capacitance, etc.
·
The wiring should be kept as short as possible.
·
No other signal lines should be crossed.
·
Keep away from lines carrying a high fluctuating current.
·
The oscillator capacitor grounding point should always be at the same potential as V
SS
. Do not connect
to a ground pattern carrying a high current.
·
A signal should be not taken from the oscillator.
5
46
µ
PD75108F,75112F,75116F
RECOMMENDED OSCILLATION CIRCUIT CONSTANT
RECOMMENDED CERAMIC RESONATOR (Ta = ­40 to +50
°
C)
PRODUCT NAME
CSA 2.00MG
CSA 4.19MG
CSA 4.19MGU
CST 4.19T
KBR­2.0MS
KBR­4.0MS
KBR­4.19MS
KBR­4.9152M
C1
30
30
30
­­
100
33
33
33
C2
30
30
30
­­
100
33
33
33
MANUFACTURER
Murata Mfg.
Kyocera
EXTERNAL CAPACITANCE [pF]
MIN.
2.7
3.0
2.7
3.0
3.0
3.0
3.0
3.0
MAX.
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
OSCILLATION VOLTAGE RANGE [V]
RECOMMENDED CRYSTAL RESONATOR (Ta = ­20 to +50
°
C)
PRODUCT NAME
HC-49/U
C1
22
C2
22
MANUFACTURER
EXTERNAL CAPACITANCE [pF]
MIN.
2.7
MAX.
5.0
OSCILLATION VOLTAGE RANGE [V]
Kinseki
47
µ
PD75108F,75112F,75116F
Other than below
Ports 0,1,TI0, 1, RESET
Internal pull-up resistor
Ports 12 and 14
Open­drain
X1, X2
Other than below
Ports 0,1,TI0, 1, RESET
X1, X2
V
DD
= 4.5 to 5.0 V, I
OH
= ­1 mA
I
OH
= ­100
µ
A
Ports 0, 2 to 9, I
OL
= 15 mA
V
DD
= 4.5 to 5.0 V
Ports 12 to 14, I
OL
= 10 mA
V
DD
= 4.5 to 5.0 V, I
OL
= 1.6 mA
I
OL
= 400
µ
A
Other than below
V
IN
= V
DD
X1, X2
V
IV
= 10 V
Ports 12 to 14 (open-drain)
Except X1, X2
V
IN
= 0 V
X1, X2
V
OUT
= V
DD
Other than below
V
OUT
= 10 V
Ports 12 to 14 (open-drain)
V
DD
= 4.5 to 5.0 V
Ports 12 to 14
V
DD
= 4.5 to 5.0 V*2
V
DD
= 3 V
±
10 %*3
V
DD
= 4.5 to 5.0 V
V
DD
= 3 V
±
10 %
STOP mode, V
DD
= 3 V
±
10 %
DC CHARACTERISTICS (Ta = ­40 to +50
°
C, V
DD
= 2.7 to 5.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
IH1
V
IH2
V
IH3
V
IH4
Input voltage high
V
IL1
V
IL2
V
IL3
Input voltage low
V
OH
Output voltage high
V
OL
Output voltage low
I
LIH1
I
LIH2
I
LIH3
Input leakage
current high
Input leakage
current low
I
LIL1
I
LIL2
I
LOH1
I
LOH2
Output leakage
current high
Output leakage
current low
V
OUT
= 0 V
I
LOL
Internal pull-up
resistor
(mask option)
R
L
I
DD1
4.19 MHz
Crystal oscillation
C1 = C2 = 22 pF
HALT
mode
I
DD2
I
DD3
Supply current*1
­3
µ
A
*
1. Excluding current flowing in the internal pull-up resistors and comparator circuit.
2. When the processor clock control register (PCC) is set to 0011 for operation in the high-speed mode.
3. When the PCC register is set to 0000 for operation in the low-speed mode.
0.7 V
DD
V
DD
V
0.8 V
DD
V
DD
V
0.7 V
DD
V
DD
V
0.7 V
DD
12
V
V
DD
­ 0.5
V
DD
V
0
0.3 V
DD
V
0
0.2 V
DD
V
0
0.4
V
V
DD
­ 1.0
V
V
DD
­ 0.5
V
0.35
2.0
V
0.35
2.0
V
0.4
V
0.5
V
3
µ
A
20
µ
A
20
µ
A
­3
µ
A
­20
µ
A
3
µ
A
20
µ
A
15
40
70
k
10
80
k
3
9
mA
0.55
1.5
mA
600
1800
µ
A
200
600
µ
A
0.1
10
µ
A
48
µ
PD75108F,75112F,75116F
±
100
mV
0
V
DD
V
0
V
DD
V
CAPACITANCE (Ta = 25
°
C, V
DD
= 0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
C
IN
C
OUT
15
pF
15
pF
Input capacitance
Output capacitance
Input/output
capacitance
C
IO
f = 1 MHz
Unmeasured pins returned to 0 V
15
pF
COMPARATOR CHARACTERISTICS (Ta = ­40 to +50
°
C, V
DD
= 4.5 to 5.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
ACOMP
V
TH
V
IPTH
Compare accuracy
Threshold voltage
PTH input voltage
Comparator circuit
current consump-
tion
PTHM7 set to "1"
1
mA
49
µ
PD75108F,75112F,75116F
0.95
32
µ
s
1.91
32
µ
s
0
1
MHz
0
275
kHz
0.48
µ
s
1.8
µ
s
0.8
µ
s
0.95
µ
s
3.2
µ
s
3.8
µ
s
0.4
µ
s
t
KCY
/2 ­ 50
ns
1.6
µ
s
t
KCY
/2 ­ 150
ns
300
ns
1000
ns
V
DD
= 4.5 to 5.0 V
V
DD
= 4.5 to 5.0 V
V
DD
= 4.5 to 5.0 V
Input
V
DD
= 4.5 to 5.0 V
Output
Input
Output
Input
V
DD
= 4.5 to 5.0 V
Output
Input
Output
V
DD
= 4.5 to 5.0 V
AC CHARACTERISTICS (Ta = ­40 to +50
°
C, V
DD
= 2.7 to 5.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
f
TI
t
TIH
,
t
TIL
t
CY
t
KSI
t
SIK
t
KSO
100
ns
400
ns
TI0, TI1 input
frequency
TI0, TI1 input high/
low-level width
t
KCY
SCK cycle time
SCK high/low-level
width
t
KH
,
t
KL
SI setup time
(to SCK
)
SI hold time
(from SCK
)
SO output delay
time from SCK
INT0 to INT4
High/low-level width
RESET low-level
width
t
INTH
,
t
INTL
t
RSL
5
µ
s
5
µ
s
CPU clock cycle time*
(Minimum instruction
execution time = 1
machine cycle)
50
µ
PD75108F,75112F,75116F
t
CY
vs. V
DD
t
CY
[
s]
V
DD
[V]
0
1
2
3
4
5
6
0.5
1
2
3
4
5
7
32
40
6
µ
Operating
Guarantee
Range
*
The CPU clock
cycle time is determined by the
oscillation frequency of the connected resonator
and the setting of the processor clock control
register (PCC). The graph on the right shows the
characteristic for cycle time t
CY
supply current V
DD
during system clock operation.
51
µ
PD75108F,75112F,75116F
AC Timing Test Point (Except ports 0, 1, TI0, TI1, X1, X2, RESET)
Clock Timing
TI0,TI1 Input Timing
X1 Input
1/f
X
t
XL
t
XH
V
DD
­ 0.5 V
0.4 V
TI0, TI1
1/f
TI
t
TIL
t
TIH
0.8 V
DD
0.2 V
DD
0.7 V
DD
0.3 V
DD
0.7 V
DD
0.3 V
DD
Test Points
52
µ
PD75108F,75112F,75116F
Serial Transfer Timing
Interrupt Input Timing
t
INTL
t
INTH
INT0­INT4
0.8 V
DD
0.2 V
DD
RESET Input Timing
t
RSL
RESET
0.2 V
DD
SCK
Input Data
Output Data
t
KSO
SI
SO
0.8 V
DD
0.2 V
DD
0.8 V
DD
0.2 V
DD
t
KCY
t
KH
t
KL
t
SIK
t
KSI
53
µ
PD75108F,75112F,75116F
WAIT TIME
BTM3
BTM2
BTM1
BTM0
(Figures in parentheses are for operation at f
XX
= 4.19 MHz)
--
0
0
0
2
20
/f
XX
(approx. 250 ms)
--
0
1
1
2
17
/f
XX
(approx. 31.3 ms)
--
1
0
1
2
15
/f
XX
(approx. 7.82 ms)
--
1
1
1
2
13
/f
XX
(approx. 1.95 ms)
Data Retention Timing (STOP mode release by RESET)
*
1. Excluding current flowing in the internal pull-up resistors and comparator circuit.
2. The oscillation stabilization wait time is the time during which CPU operation is stopped to prevent unstable
operation when oscillation is started.
3. Depends on the basic interval timer mode register (BTM) setting (see table below).
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = ­40 to +50
°
C)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Data retention supply voltage
V
DDDR
2.0
5.0
V
Data retention supply current*1
I
DDDR
V
DDDR
= 2.0 V
0.1
10
µ
A
Release signal set time
t
SREL
0
µ
s
Release by RESET
2
17
/f
XX
ms
Oscillation stabilization time*2
t
WAIT
Release by interrupt request
*3
ms
STOP Mode
Data Retention Mode
STOP Instruction Execution
RESET
V
DD
Internal Reset Operation
HALT Mode
Operating
Mode
V
DDDR
t
SREL
t
WAIT
54
µ
PD75108F,75112F,75116F
Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)
STOP Mode
Data Retention Mode
STOP Instruction Execution
V
DD
HALT Mode
Operating
Mode
V
DDDR
t
SREL
t
WAIT
Standby Release Signal
(Interrupt Request)
55
µ
PD75108F,75112F,75116F
12.2 WHEN Ta = ­40 to +60
°
C, V
DD
= 2.8 to 5.0 V
OPERATING VOLTAGE (Ta = ­40 to +60
°
C)
CPU*1
Programmable threshold port
(comparator input)
Other hardware*1
*2
5.0
V
4.5
5.0
V
2.8
5.0
V
PARAMETER
TEST CONDITIONS
MIN.
MAX.
UNIT
*
1. Except system clock oscillation circuit, programmable threshold port.
2. The operable supply voltage range depends on the cycle time. See "AC CHARACTERISTICS".
OSCILLATION CIRCUIT CHARACTERISTICS (Ta = ­40 to +60
°
C, V
DD
= 2.8 to 5.0 V)
RECOMMENDED
TEST
RESONATOR
PARAMETER
MIN.
TYP.
MAX.
UNIT
CONSTANT
CONDITIONS
Ceramic
resonator
After V
DD
reaches
MIN. of oscillation
voltage range
Crystal
resonator
External
clock
2.0
5.0*3
MHz
4
ms
2.0
4.19
5.0*3
MHz
V
DD
= 4.5 to 5.0 V
10
ms
30
ms
2.0
5.0*3
MHz
100
250
ns
Oscillator
frequency (f
XX
)*1
Oscillation
stabilization time*2
Oscillator
frequency (f
XX
)*1
Oscillation
stabilization time*2
X1 input
frequency (f
X
)*1
X1 input
high-/low-level width
(t
XH
, t
XL
)
X1
X2
µ
PD74HCU04
V
DD
= Oscillation
voltage range
X1
X2
C1
C2
X1
X2
C1
C2
*
1. Oscillator frequency and X1 input frequency indicate oscillation circuit characteristics only. See AC
CHARACTERISTICS for instruction execution time.
2. The oscillation stabilization time is the time required for oscillation to stabilize after V
DD
reaches MIN. of
oscillation voltage range, or the STOP mode is released.
3. When the oscillator frequency is 4.19 MHz < f
XX
5.0 MHz, PCC = 0011 should not be selected as the instruction
execution time. If PCC = 0011 is selected, one machine cycle is less than 0.95
µ
s and the rated MIN. value
of 0.95
µ
s is not observed.
Note
When the clock oscillator is used, the following should be noted concerning wiring in the area in the figure
enclosed by a dotted line to prevent the influence of wiring capacitance, etc.
·
The wiring should be kept as short as possible.
·
No other signal lines should be crossed.
·
Keep away from lines carrying a high fluctuating current.
·
The oscillator capacitor grounding point should always be at the same potential as V
SS
. Do not connect
to a ground pattern carrying a high current.
·
A signal should be not taken from the oscillator.
5
56
µ
PD75108F,75112F,75116F
RECOMMENDED OSCILLATION CIRCUIT CONSTANT
RECOMMENDED CERAMIC RESONATOR (Ta = ­40 to +60
°
C)
PRODUCT NAME
CSA 2.00MG
CSA 4.19MG
CSA 4.19MGU
CST 4.19T
KBR­2.0MS
KBR­4.0MS
KBR­4.19MS
KBR­4.9152M
C1
30
30
30
­­
100
33
33
33
C2
30
30
30
­­
100
33
33
33
MANUFACTURER
Murata Mfg.
Kyocera
EXTERNAL CAPACITANCE [pF]
MIN.
2.7
3.0
2.7
3.0
3.0
3.0
3.0
3.0
MAX.
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
OSCILLATION VOLTAGE RANGE [V]
RECOMMENDED CRYSTAL RESONATOR (Ta = ­20 to +60
°
C)
PRODUCT NAME
HC-49/U
C1
22
C2
22
MANUFACTURER
EXTERNAL CAPACITANCE [pF]
MIN.
2.7
MAX.
5.0
OSCILLATION VOLTAGE RANGE [V]
Kinseki
57
µ
PD75108F,75112F,75116F
Other than below
Ports 0,1,TI0, 1, RESET
Internal pull-up resistor
Ports 12 to 14
Open­drain
X1, X2
Other than below
Ports 0,1,TI0, 1, RESET
X1, X2
V
DD
= 4.5 to 5.0 V, I
OH
= ­1 mA
I
OH
= ­100
µ
A
Ports 0, 2 to 9, I
OL
= 15 mA
V
DD
= 4.5 to 5.0 V
Ports 12 to 14, I
OL
= 10 mA
V
DD
= 4.5 to 5.0 V, I
OL
= 1.6 mA
I
OL
= 400
µ
A
Other than below
V
IN
= V
DD
X1, X2
V
IV
= 10 V
Ports 12 to 14 (open-drain)
Except X1, X2
V
IN
= 0 V
X1, X2
V
OUT
= V
DD
Other than below
V
OUT
= 10 V
Ports 12 to 14 (open-drain)
V
DD
= 4.5 to 5.0 V
Ports 12 to 14
V
DD
= 4.5 to 5.0 V*2
V
DD
= 2.8 to 3.3 V*3
V
DD
= 4.5 to 5.0 V
V
DD
= 2.8 to 3.3 V
STOP mode, V
DD
= 2.8 to 3.3 V
DC CHARACTERISTICS (Ta = ­40 to +60
°
C, V
DD
= 2.8 to 5.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
IH1
V
IH2
V
IH3
V
IH4
Input voltage high
V
IL1
V
IL2
V
IL3
Input voltage low
V
OH
Output voltage high
V
OL
Output voltage low
I
LIH1
I
LIH2
I
LIH3
Input leakage
current high
Input leakage
current low
I
LIL1
I
LIL2
I
LOH1
I
LOH2
Output leakage
current high
Output leakage
current low
V
OUT
= 0 V
I
LOL
Internal pull-up
resistor
(mask option)
R
L
I
DD1
4.19 MHz
Crystal oscillation
C1 = C2 = 22 pF
HALT
mode
I
DD2
I
DD3
Supply current*1
­3
µ
A
*
1. Excluding current flowing in the internal pull-up resistors and comparator circuit.
2. When the processor clock control register (PCC) is set to 0011 for operation in the high-speed mode.
3. When the PCC register is set to 0000 for operation in the low-speed mode.
0.7 V
DD
V
DD
V
0.8 V
DD
V
DD
V
0.7 V
DD
V
DD
V
0.7 V
DD
10
V
V
DD
­ 0.5
V
DD
V
0
0.3 V
DD
V
0
0.2 V
DD
V
0
0.4
V
V
DD
­ 1.0
V
V
DD
­ 0.5
V
0.35
2.0
V
0.35
2.0
V
0.4
V
0.5
V
3
µ
A
20
µ
A
20
µ
A
­3
µ
A
­20
µ
A
3
µ
A
20
µ
A
15
40
70
k
10
80
k
3
9
mA
0.55
1.5
mA
600
1800
µ
A
200
600
µ
A
0.1
10
µ
A
58
µ
PD75108F,75112F,75116F
±
100
mV
0
V
DD
V
0
V
DD
V
CAPACITANCE (Ta = 25
°
C, V
DD
= 0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
C
IN
C
OUT
15
pF
15
pF
Input capacitance
Output capacitance
Input/output
capacitance
C
IO
f = 1 MHz
Unmeasured pins returned to 0 V
15
pF
COMPARATOR CHARACTERISTICS (Ta = ­40 to +60
°
C, V
DD
= 4.5 to 5.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
ACOMP
V
TH
V
IPTH
Compare accuracy
Threshold voltage
PTH input voltage
Comparator circuit
current consump-
tion
PTHM7 set to "1"
1
mA
59
µ
PD75108F,75112F,75116F
0.95
32
µ
s
1.91
32
µ
s
0
1
MHz
0
275
kHz
0.48
µ
s
1.8
µ
s
0.8
µ
s
0.95
µ
s
3.2
µ
s
3.8
µ
s
0.4
µ
s
t
KCY
/2 ­ 50
ns
1.6
µ
s
t
KCY
/2 ­ 150
ns
300
ns
1000
ns
V
DD
= 4.5 to 5.0 V
V
DD
= 4.5 to 5.0 V
V
DD
= 4.5 to 5.0 V
Input
V
DD
= 4.5 to 5.0 V
Output
Input
Output
Input
V
DD
= 4.5 to 5.0 V
Output
Input
Output
V
DD
= 4.5 to 5.0 V
AC CHARACTERISTICS (Ta = ­40 to +60
°
C, V
DD
= 2.8 to 5.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
f
TI
t
TIH
,
t
TIL
t
CY
t
KSI
t
SIK
t
KSO
100
ns
400
ns
TI0, TI1 input
frequency
TI0, TI1 input high/
low-level width
t
KCY
SCK cycle time
SCK high/low-level
width
t
KH
,
t
KL
SI setup time
(to SCK
)
SI hold time
(from SCK
)
SO output delay
time from SCK
INT0 to INT4
High/low-level width
RESET low-level
width
t
INTH
,
t
INTL
t
RSL
5
µ
s
5
µ
s
CPU clock cycle time*
(Minimum instruction
execution time = 1
machine cycle)
60
µ
PD75108F,75112F,75116F
t
CY
vs. V
DD
t
CY
[
s]
V
DD
[V]
0
1
2
3
4
5
6
0.5
1
2
3
4
5
7
32
40
6
µ
Operating
Guarantee
Range
*
The CPU clock
cycle time is determined by the
oscillation frequency of the connected resonator
and the setting of the processor clock control
register (PCC). The graph on the right shows the
characteristic for cycle time t
CY
supply current V
DD
during system clock operation.
61
µ
PD75108F,75112F,75116F
AC Timing Test Point (Except ports 0, 1, TI0, TI1, X1, X2, RESET)
Clock Timing
TI0, TI1 Input Timing
X1 Input
1/f
X
t
XL
t
XH
V
DD
­ 0.5 V
0.4 V
TI0, TI1
1/f
TI
t
TIL
t
TIH
0.8 V
DD
0.2 V
DD
0.7 V
DD
0.3 V
DD
0.7 V
DD
0.3 V
DD
Test Points
62
µ
PD75108F,75112F,75116F
Serial Transfer Timing
SCK
Input Data
Output Data
t
KSO
SI
SO
0.8 V
DD
0.2 V
DD
0.8 V
DD
0.2 V
DD
t
KCY
t
KH
t
KL
t
SIK
t
KSI
Interrupt Input Timing
t
INTL
t
INTH
INT0­INT4
0.8 V
DD
0.2 V
DD
RESET Input Timing
t
RSL
RESET
0.2 V
DD
63
µ
PD75108F,75112F,75116F
WAIT TIME
BTM3
BTM2
BTM1
BTM0
(Figures in parentheses are for operation at f
XX
= 4.19 MHz)
--
0
0
0
2
20
/f
XX
(approx. 250 ms)
--
0
1
1
2
17
/f
XX
(approx. 31.3 ms)
--
1
0
1
2
15
/f
XX
(approx. 7.82 ms)
--
1
1
1
2
13
/f
XX
(approx. 1.95 ms)
Data Retention Timing (STOP mode release by RESET)
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = ­40 to +60
°
C)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Data retention supply voltage
V
DDDR
2.0
5.0
V
Data retention supply current*1
I
DDDR
V
DDDR
= 2.0 V
0.1
10
µ
A
Release signal set time
t
SREL
0
µ
s
Release by RESET
2
17
/f
XX
ms
Oscillation stabilization time*2
t
WAIT
Release by interrupt request
*3
ms
*
1. Excluding current flowing in the internal pull-up resistors and comparator circuit.
2. The oscillation stabilization wait time is the time during which CPU operation is stopped to prevent unstable
operation when oscillation is started.
3. Depends on the basic interval timer mode register (BTM) setting (see table below).
STOP Mode
Data Retention Mode
STOP Instruction Execution
RESET
V
DD
Internal Reset Operation
HALT Mode
Operating
Mode
V
DDDR
t
SREL
t
WAIT
64
µ
PD75108F,75112F,75116F
Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)
STOP Mode
Data Retention Mode
STOP Instruction Execution
V
DD
HALT Mode
Operating
Mode
V
DDDR
t
SREL
t
WAIT
Standby Release Signal
(Interrupt Request)
65
µ
PD75108F,75112F,75116F
13. CHARACTERISTIC CURVES (REFERENCE)
Supply Current I
DD
[
µ
A]
I
DD
vs. V
DD
(Crystal Oscillator : 4.19 MHz)
(Ta = 25 °C)
Supply Voltage V
DD
[V]
1000
100
10
0
1
2
3
4
5
6
X1
X2
22pF
22pF
Crystal
4.19 MHz
HALT Mode
High-Speed Mode
Medium-Speed Mode
Low-Speed Mode
66
µ
PD75108F,75112F,75116F
Supply Current I
DD
[mA]
Supply Current I
DD
[mA]
0
1
2
3
4
5
0
0.5
1.0
1.5
2.0
2.5
3.0
Values in parentheses indicate PCC set values.
I
DD
vs. f
XX
Characteristic Examples (Crystal Oscillation)
(V
DD
= 5.0 V, Ta = 25 °C)
f
XX
[MHz]
C
1
X1
X2
C
2
High-Speed Mode [0011]
Medium-Speed Mode
[0010]
Low-Speed Mode [0000]
HALT Mode [0100]
0
1
2
3
4
5
0
0.5
1.0
1.5
2.0
2.5
3.0
Values in parentheses indicate PCC set values.
I
DD
vs. f
XX
Characteristic Examples (Ceramic Oscillation)
(V
DD
= 5.0 V, Ta = 25 °C)
f
XX
[MHz]
C
1
X1
X2
C
2
High-Speed Mode [0011]
Medium-Speed Mode
[0010]
Low-Speed Mode [0000]
HALT Mode [0100]
67
µ
PD75108F,75112F,75116F
Supply Current I
DD
[mA]
µ
PD74HCU04
0
1
2
3
4
5
0
0.5
1.0
1.5
2.0
2.5
3.0
Values in parentheses indicate PCC set values.
I
DD
vs. f
X
Characteristic Examples (External Clock)
(V
DD
= 5.0 V, Ta = 25 °C)
f
X
[MHz]
X1
X2
High-Speed Mode [0011]
Medium-Speed Mode
[0010]
Low-Speed Mode [0000]
HALT Mode [0100]
68
µ
PD75108F,75112F,75116F
TIn Input Frequency f
TI
[kHz]
TIn Input Frequency f
TI
[kHz]
0
0
f
TI
vs. V
DD
Characteristic
(Ta = ­40 to +50 °C)
V
DD
[V]
1
2
3
4
5
6
7
100
50
1000
500
Operating
Guarantee
Range
0
0
f
TI
vs. V
DD
Characteristic
(Ta = ­40 to +60 °C)
V
DD
[V]
1
2
3
4
5
6
7
100
50
1000
500
Operating
Guarantee
Range
69
µ
PD75108F,75112F,75116F
Ports 0, 2 to 9 Output Current Low I
OL
[mA]
Ports 12 to 14 Output Current Low I
OL
[mA]
0
0
V
OL
vs. I
OL
(Ports 0, 2 to 9) Characteristic Examples
V
OL
[V]
V
DD
= 5 V
V
DD
= 4 V
V
DD
= 3 V
1
2
3
4
10
20
30
0
0
V
OL
vs. I
OL
(Ports 12 to 14) Characteristic Examples
V
OL
[V]
V
DD
= 5 V
V
DD
= 4 V
V
DD
= 3 V
1
2
3
4
10
20
30
70
µ
PD75108F,75112F,75116F
Ports 0, 2 to 9 Output Current High I
OH
[mA]
Remarks
Characteristic curves not marked "Guarantee Range" indicate reference values.
0
0
V
OH
vs. I
OH
(Ports 0, 2 to 9) Characteristic Examples
V
DD
­ V
OH
[V]
V
DD
= 5 V
V
DD
= 4 V
V
DD
= 3 V
1
2
3
4
-5
-10
-15
71
µ
PD75108F,75112F,75116F
N
A
M
F
B
51
52
32
K
L
64 PIN PLASTIC QFP (14
×
20)
64
1
20
19
33
P
D
C
detail of lead end
S
Q
5°±5°
G
M
I
H
J
P64GF-100-3B8,3BE,3BR-1
ITEM
MILLIMETERS
INCHES
A
B
C
D
F
G
H
I
J
K
L
23.6±0.4
14.0±0.2
1.0
0.40±0.10
0.20
20.0±0.2
0.929±0.016
0.039
0.039
0.008
0.039 (T.P.)
0.795
NOTE
M
N
0.12
0.15
1.8±0.2
1.0 (T.P.)
0.005
0.006
+0.004
­0.003
Each lead centerline is located within 0.20
mm (0.008 inch) of its true position (T.P.) at
maximum material condition.
0.071
0.016
0.551
0.8±0.2
0.031
P
2.7
0.106
0.693±0.016
17.6±0.4
1.0
+0.009
­0.008
Q
0.1±0.1
0.004±0.004
S
3.0 MAX.
0.119 MAX.
+0.10
­0.05
+0.009
­0.008
+0.004
­0.005
+0.009
­0.008
+0.008
­0.009
14. PACKAGE INFORMATION
64-Pin Plastic QFP (14
×
20)
72
µ
PD75108F,75112F,75116F
64-Pin Ceramic QFP for ES (Reference Diagram)
Caution
1.
Note that the metal cap is
connected to pin 26, and is
at the V
SS
(GND) level.
2.
Note that the leads on the
underside are formed at an
angle.
3.
Cutting of the lead tips is
not process-controlled, and
therefore there is no stan-
dard lead length.
14.2
12.0
64
52
1
51
32
20
19
33
0.4
1.0
2.25
18.0
0.15
Bottom
View
20
73
µ
PD75108F,75112F,75116F
15. RECOMMENDED SOLDERING CONDITIONS
The
µ
PD75116F should be soldered and mounted under the conditions recommended in the table below.
For details of recommended conditions, refer to the information document "Semiconductor Device Mount
Technology Manual" (IEI-1207).
For soldering methods and conditions other than those recommended below, contact our salesman.
Table 15-1 Surface Mount Type Soldering Conditions
µ
PD75108FGF-
×××
-3BE : 64-Pin Plastic QFP (14
×
20 mm)
µ
PD75112FGF-
×××
-3BE : 64-Pin Plastic QFP (14
×
20 mm)
µ
PD75116FGF-
×××
-3BE : 64-Pin Plastic QFP (14
×
20 mm)
Recommended
Condition Symbol
Soldering Method
Soldering Conditions
Infrared reflow
VPS
Package peak temperature : 230
°
C, Duration : 30 sec. max. (at 210
°
C or
avove), Number of times : once
Package peak temperature : 215
°
C, Duration : 40 sec. max. (at 200
°
C or
above), Number of times : once
Solder bath temperature : 260
°
C max., Duration : 10 sec. max., Number of
times : once, Preheating temperature : 120
°
C max. (package surface
temperature)
Pin part temperature : 300
°
C max., Duration : 3 sec. max. (per device side)
IR30-00-1
VP15-00-1
Pin part heating
Pin part heating
Wave soldering
WS60-00-1
Note
Use of more than one soldering method should be avoided (except in the case of pin part heating).
Notice
A version of this product with improved recommended soldering conditions is
available. For details (improvements such as infrared reflow peak temperature
extension (235
°
C), number of times: twice, relaxation of time limit, etc.), contact
NEC sales personnel.
74
µ
PD75108F,75112F,75116F
Item
4K/6K/8K/12K/16K
4K/8K
8K/12K/16K
(Mask ROM)
(Mask ROM)
(Mask ROM)
320/320/512/512/512
320/512
512
ROM (byte)
RAM (
×
4 bits)
µ
PD75104/106/108/112/116
µ
PD75104A/108A
µ
PD75108F/112F/116F
Product Name
APPENDIX A. FUNCTIONAL DIFFERENCES AMONG
µ
PD751
××
SERIES PRODUCTS
10 (Pull-up resistor mask option : 4)
32 (Pull-up resistor mask option : 24,
LED direct drive capability)
10
32 (LED direct drive capability)
32 (LED direct drive capability)
10
Withstand voltage
CMOS
input/output
N-ch open-drain
input/output
CMOS input
Total
12 (LED direct drive capability)
+12 V
+10 V
Instruction set
75X High-End
58
Analog input
Power-on reset circuit
Power-on flag
On-chip (Mask option)
None
2.7 to 6.0 V
­40 to +85
°
C
­40 to +60
°
C
Pull-up resistor
Can be incorporated by mask option
4 (4-bit precision)
Operating temperature
range
2.7 to 5.0 V (Ta = ­40 to +50
°
C)
2.8 to 5.0 V
Minimum instruction
execution time
0.95
µ
s (operating at 4.5 to 6.0 V)
0.95
µ
s (operating at 4.5 to 5.0 V)
3.8
µ
s (operating at 2.7 V)
1.91
µ
s (operating at 2.7V)
I/O
port
Package *2
*
1. 75X High-End can also be used by means of the 16K-byte mode/24K-byte mode switching function.
2. The following five types of plastic QFP are available.
· G-1B ........ 14
×
20
×
2.05 mm, 1.0 mm pitch
· GC-AB8 ... 14
×
14
×
2.55 mm, 0.8 mm pitch
· GF-3BE .... 14
×
20
×
2.7 mm, 1.0 mm pitch
· G-22 ........ 14
×
14
×
1.5 mm, 0.8 mm pitch
· GK-7ET ... 12
×
12
×
1.45 mm, 0.65 mm pitch
3. Under development.
Operating voltage
· 64-pin plastic shrink DIP
· 64-pin plastic QFP(GF-3BE)
· 64-pin plastic QFP (G-1B)
:
µ
PD75104/106/108 only
· 64-pin plastic QFP(GC-AB8)
· 64-pin plastic QFP (G-22)
:
µ
PD75108A only
· 64-pin plastic QFP(GF-3BE)
5
75
µ
PD75108F,75112F,75116F
16K/24K
8K
24K
(Mask ROM)
(One-time PROM)
(One-time PROM)
768
512
768
75X High-End/Extended
75X High-End
75X Extended
High-End
High-End*1
58
10
µ
PD75116H/117H
µ
PD75P108B
µ
PD75P116
µ
PD75P117H
32 (LED direct drive
capability : 8)
32 (LED direct drive capability)
32 (LED direct drive
capability : 8)
12
12 (LED direct drive capability)
12
+6 V
+12 V
+6 V
Can be incorporated by
mask option
None
4 (4-bit precision)
None
None
1.8 to 5.0 V
­40 to +60
°
C
­40 to +85
°
C
2.7 to 6.0 V
5 V
±
10 %
1.8 to 5.0 V
­40 to +60
°
C
0.95
µ
s (operating at 2.7 V)
1.91
µ
s (operating at 1.8 V)
0.95
µ
s (operating at 4.5 to 6.0 V)
3.8
µ
s (operating at 2.7 V)
0.95
µ
s
(operating at 4.75 to 5.5 V)
0.95
µ
s (operating at 2.7 V)
1.91
µ
s (operating at 1.8 V)
· 64-pin plastic QFP (GC-AB8)
· 64-pin plastic QFP (GK-7ET)
· 64-pin plastic shrink DIP
· 64-pin plastic QFP (GF-3BE)
· 64-pin plastic shrink DIP
· 64-pin plastic QFP (GF-3BE)
· 64-pin ceramic shrink DIP
with window
· 64-pin plastic QFP (GC-AB8)
· 64-pin plastic QFP
(GK-7ET)*3
76
µ
PD75108F,75112F,75116F
APPENDIX B. DEVELOPMENT TOOLS
The following development tools are available for system development using the
µ
PD75116F.
*
1. Maintenance product
2. Not incorporated in the IE-75001-R.
3. A task swapping function is provided in Ver. 5.00/5.00A, but this function cannot be used with this software.
Remarks
Please refer to the 75X Series Selection Guide (IF-151) for third party development tools.
5
IE-75000-R*1
IE-75001-R
IE-75000-R-EM*2
EP-75108GF-R
PG-1500
PA-75P116GF
IE Control Program
PG-1500 Controller
RA75X Relocatable
Assembler
75X series in-circuit emulator
Emulation board for the IE-75000-R or IE-75001-R
Emulation probe for the
µ
PD75116FGF. A 64-pin conversion socket (EV-9200G-64) is also
provided.
PROM programmer
PROM programmer adapter for the
µ
PD75P116GF, connected to the PG-1500.
Host machines
· PC-9800 series (MS-DOSTM Ver. 3.30 to Ver. 5.00A*3)
· IBM PC/ATTM (PC-DOSTM Ver.3.1)
EV-9200G-64
Hardware
Software
77
µ
PD75108F,75112F,75116F
Document Name
Document Number
IE-75000-R/IE-75001-R User's Manual
EEU­1455
IE-75000-R-EM User's Manual
EEU­1294
EP-75108GF-R User's Manual
EEU­1318
PG-1500 User's Manual
EEU­1335
Operation Volume
EEU­1346
Language Volume
EEU­1343
PG-1500 Controller User's Manual
EEU­1291
APPENDIX C. RELATED DOCUMENTS
Device Related Documents
Document Name
Document Number
User's Manual
IEM­1260
Instruction Application Table
Not Available
(I)
Introductory Volume
IEM­1139
(II)
Remote Control Reception
Volume
IEM­1281
(III) Barcode Reader Volume
IEM­1265
(IV) MSK Transmission/Reception
IC Control Volume
IEM­1278
75X Series Selection Guide
IF­1027
Application Note
Development Tools Documents
Other Documents
Document Name
Document Number
Package Manual
IEI­1213
Surface Mount Technology Manual
IEI­1207
Quality grade on NEC Semiconductor Devices
IEI­1209
NEC Semiconductor Device Reliability & Quality Control
Not Available
Electrostatic Discharge (ESD) Test
Not Available
Semiconductor Devices Quality Guide Guarantee Guide
MEI­1202
Microcomputer Related Products Guide Other Manufacturers Volume
Not Available
Note
The information in these related documents is subject to change without notice. For design purpose, etc.,
be sure to use the latest ones.
5
RA75X Assembler Package User's Manual
Hardware
Software
[MEMO]
µ
PD75108F,75112F,75116F
MS-DOS is a trademark of Microsoft Corporation.
PC/AT and PC DOS are trademarks of IBM Corporation.
M4 92.6
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights
or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear
reactor control systems and life support systems. If customers intend to use NEC devices for above applications
or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact
our sales people in advance.
Application examples recommended by NEC Corporation
Standard :
Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special
:
Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,
Anticrime systems, etc.