Document Outline

Cover
FEATURES
ORDERING INFORMATION
CONTENTS
1. PIN CONFIGURATION (TOP VIEW)
2. BLOCK DIAGRAM
3. PIN FUNCTIONS
- 3.1 Port Pins
- 3.2 Non-Port Pins
- 3.3 Pin Input/Output Circuits
- 3.4 Connection of Unused Pins
4. Mk I MODE/Mk II MODE SWITCH FUNCTION
- 4.1 Differences between Mk I Mode and Mk II Mode
- 4.2 Setting of the Stack Bank Selection Register (SBS)
5. MEMORY CONFIGURATION
6. PERIPHERAL HARDWARE FUNCTIONS
- 6.1 Digital I/O Ports
- 6.2 Clock Generator
- 6.3 Control Functions of Subsystem Clock Oscillator
- 6.4 Clock Output Circuit
- 6.5 Basic Interval Timer/Watchdog Timer
- 6.6 Clock Timer
- 6.7 Timer/Event Counter
- 6.8 Serial Interface
- 6.9 Bit Sequential Buffer
7. INTERRUPT FUNCTIONS AND TEST FUNCTIONS
8. STANDBY FUNCTION
9. RESET FUNCTION
10. MASK OPTION
11. INSTRUCTION SET
12. ELECTRICAL CHARACTERISTICS
13. CHARACTERISTIC CURVE (REFERENCE VALUES)
14. EXAMPLES OF RC OSCILLATOR FREQUENCY CHARACTERISTICS (REFERENCE VALUES)
15. PACKAGE DRAWINGS
16. RECOMMENDED SOLDERING CONDITIONS
APPENDIX A FUNCTIONS OF THE uPD750008, uPD750108, AND uPD75P0116
APPENDIX B DEVELOPMENT TOOLS
APPENDIX C RELATED DOCUMENTS

DATA SHEET

MOS INTEGRATED CIRCUIT

1990

1997

4 BIT SINGLE-CHIP MICROCONTROLLER

The

PD750108 is one of the 75XL series 4-bit single-chip microcontrollers, which provide data processing

capability equal to that of an 8-bit microcontroller.

The

PD750108 is produced by replacing the main system clock oscillator of the

PD750008 with an RC oscillator,

enabling operation at a relatively low voltage of 1.8 V. In addition, it is best suited to applications using batteries.

The

PD750108(A) has a higher reliability than the

PD750108.

A built-in one-time PROM product,

PD75P0116, is also available. It is suitable for small-scale production and

evaluation of application systems.

The following user's manual describes the details of the functions of the

PD750108. Be sure to read it

before designing application systems.

PD750108 User's Manual: U11330E

FEATURES

З Built-in RC oscillator

З Enables the immediate start of processing after the

release of standby mode

З Capable of low-voltage operation: V

= 1.8 to 5.5 V

З Internal memory

Program memory (ROM)

: 4,096

8 bits (

PD750104 and

PD750104(A))

: 6,144

8 bits (

PD750106 and

PD750106(A))

: 8,192

8 bits (

PD750108 and

PD750108(A))

Data memory (RAM)

: 512

4 bits

APPLICATIONS

PD750104,

PD750106, and

PD750108

Cameras, meters, and pagers

PD750104(A),

PD750106(A), and

PD750108(A)

Electrical equipment for automobiles

The

PD750104,

PD750106,

PD750108,

PD750104(A),

PD750106(A), and

PD750108(A) differ only in

quality grade. In this manual, the

PD750108 is described unless otherwise specified. Users of other than the

PD750108 should read

PD750108 as referring to the pertinent product.

When the description differs among

PD750104,

PD750106, and

PD750108, they also refer to the pertinent

(A) products.

PD750104

PD750104(A),

PD750106

PD750106(A),

PD750108

PD750108(A)

The information in this document is subject to change without notice.

Document No.

U12301EJ1V0DS00 (1st edition)

Date Published July 1997 J
Printed in Japan

PD750104,750106,750108,750104(A),750106(A),750108(A)

З Function for specifying the instruction execution time

(useful for saving power)

s, 8

s, 16

s, 64

s (when operating at 1.0 MHz)

s, 4

s, 8

s, 32

s (when operating at 2.0 MHz)

122

s (when operating at 32.768 kHz)

З Enhanced timer function (4 channels)

З Can be easily substituted for the

PD750008 because

this product succeeds to the functions and instructions

of the

PD750008.

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

ORDERING INFORMATION

Part number

Package

Quality grade

PD750104CU-

ззз

42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

Standard

PD750104GB-

ззз

-3BS-MTX

44-pin plastic QFP (10

10 mm, 0.8-mm pitch)

Standard

PD750106CU-

ззз

42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

Standard

PD750106GB-

ззз

-3BS-MTX

44-pin plastic QFP (10

10 mm, 0.8-mm pitch)

Standard

PD750108CU-

ззз

42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

Standard

PD750108GB-

ззз

-3BS-MTX

44-pin plastic QFP (10

10 mm, 0.8-mm pitch)

Standard

PD750104CU(A)-

ззз

42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

Special

PD750104GB(A)-

ззз

-3BS-MTX

44-pin plastic QFP (10

10 mm, 0.8-mm-pitch)

Special

PD750106CU(A)-

ззз

42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

Special

PD750106GB(A)-

ззз

-3BS-MTX

44-pin plastic QFP (10

10 mm, 0.8-mm pitch)

Special

PD750108CU(A)-

ззз

42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

Special

PD750108GB(A)-

ззз

-3BS-MTX

44-pin plastic QFP (10

10 mm, 0.8-mm pitch)

Special

Remark

ззз

is a mask ROM code number.

DIFFERENCES BETWEEN

PD75010

AND

PD75010

(A)

Product number

Item

Quality grade

Standard

Special

PD750104

PD750106

PD750108

PD750104(A)

PD750106(A)

PD750108(A)

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

ROM

RAM

FUNCTIONS

CMOS input

CMOS I/O

N-ch open

drain I/O

Total

Can incorporate 7 pull-up resistors that are specified with the software.

Can directly drive the LED.

Can incorporate 18 pull-up resistors that are specified with the software.

Can directly drive the LED.

Can withstand 13 V.

Can incorporate pull-up resistors that are specified with the mask option.

Serial interface

Clock output (PCL)

Buzzer output (BUZ)

Vectored interrupt

Test input

System clock oscillator

Standby

Operating ambient

temperature range

Supply voltage

Package

Item

Command execution

time

Internal memory

General-purpose

I/O port

Timer

Bit sequential buffer (BSB)

4 channels

8-bit timer/event counter: 1 channel

8-bit timer counter: 1 channel

Basic interval timer/watchdog timer: 1 channel

lock timer: 1 channel

Three-wire serial I/O mode ... switchable between the start LSB and the start MSB

Two-wire serial I/O mode

SBI mode

16 bits

, 125, 62.5, or 15.6 kHz (when the main system clock operates at 1.0 MHz)

, 250, 125, or 31.3 kHz (when the main system clock operates at 2.0 MHz)

2, 4, or 32 kHz (when the subsystem clock operates at 32.768 kHz)

0.488, 0.977, or 7.813 kHz (when the main system clock operates at 1.0 MHz)

0.977, 1.953, or 15.625 kHz (when the main system clock operates at 2.0 MHz)

External :

Internal :

External :

Internal :

RC oscillator for main system clock (with external resistor and capacitor)

Crystal oscillator for subsystem clock

STOP/HALT mode

= -40 to +85

= 1.8 to 5.5 V

42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

44-pin plastic QFP (10

10 mm, 0.8-mm pitch)

Function

З 4, 8, 16, or 64

s (when the main system clock operates at 1.0 MHz)

З 2, 4, 8, or 32

s (when the main system clock operates at 2.0 MHz)

З 122

s (when the subsystem clock operates at 32.768 kHz)

4,096

8 bits (

PD750104)

6,144

8 bits (

PD750106)

8,192

8 bits (

PD750108)

512

4 bits

З When operating in 4 bits: 8

4 banks

З When operating in 8 bits: 4

4 banks

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

CONTENTS

PIN CONFIGURATION (TOP VIEW) .........................................................................................

BLOCK DIAGRAM .....................................................................................................................

PIN FUNCTIONS ........................................................................................................................

3.1

Port Pins .........................................................................................................................................

3.2

Non-Port Pins .................................................................................................................................

3.3

Pin Input/Output Circuits ..............................................................................................................

3.4

Connection of Unused Pins .........................................................................................................

MODE/Mk

MODE SWITCH FUNCTION ........................................................................

4.1

Differences between Mk

Mode and Mk

Mode ......................................................................

4.2

Setting of the Stack Bank Selection Register (SBS) ................................................................

MEMORY CONFIGURATION ....................................................................................................

PERIPHERAL HARDWARE FUNCTIONS ................................................................................

6.1

Digital I/O Ports ..............................................................................................................................

6.2

Clock Generator .............................................................................................................................

6.3

Control Functions of Subsystem Clock Oscillator ...................................................................

6.4

Clock Output Circuit ......................................................................................................................

6.5

Basic Interval Timer/Watchdog Timer ........................................................................................

6.6

Clock Timer .....................................................................................................................................

6.7

Timer/Event Counter .....................................................................................................................

6.8

Serial Interface ...............................................................................................................................

6.9

Bit Sequential Buffer .....................................................................................................................

INTERRUPT FUNCTIONS AND TEST FUNCTIONS ...............................................................

STANDBY FUNCTION ...............................................................................................................

RESET FUNCTION .....................................................................................................................

10. MASK OPTION ...........................................................................................................................

11. INSTRUCTION SET ....................................................................................................................

12. ELECTRICAL CHARACTERISTICS .........................................................................................

13. CHARACTERISTIC CURVE (REFERENCE VALUES) ............................................................

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

14. EXAMPLES OF RC OSCILLATOR FREQUENCY CHARACTERISTICS (REFERENCE

VALUES) .....................................................................................................................................

15. PACKAGE DRAWINGS .............................................................................................................

16. RECOMMENDED SOLDERING CONDITIONS ........................................................................

APPENDIX A

FUNCTIONS OF THE

PD750008,

PD750108, AND

PD75P0116 ..................

APPENDIX B

DEVELOPMENT TOOLS ........................................................................................

APPENDIX C

RELATED DOCUMENTS ........................................................................................

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

1. PIN CONFIGURATION (TOP VIEW)

42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

PD750104CU-

ззз

PD750104CU(A)-

ззз

PD750106CU-

ззз

PD750106CU(A)-

ззз

PD750108CU-

ззз

PD750108CU(A)-

ззз

IC : Internally connected (Connect directly to V

P40

P41

P42

P43

P50

P51

P52

P53

P60/KR0

P61/KR1

P62/KR2

P63/KR3

P70/KR4

P71/KR5

P72/KR6

P73/KR7

P20/PTO0

P21/PTO1

P22/PCL

P23/BUZ

XT1

XT2

RESET

CL1

CL2

P33

P32

P31

P30

P81

P80

P03/SI/SB1

P02/SO/SB0

P01/SCK

P00/INT4

P13/TI0

P12/INT2

P11/INT1

P10/INT0

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

44-pin plastic QFP (10

10 mm, 0.8-mm pitch)

PD750104GB-

ззз

-3BS-MTX,

PD750104GB(A)-

ззз

-3BS-MTX

PD750106GB-

ззз

-3BS-MTX,

PD750106GB(A)-

ззз

-3BS-MTX

PD750108GB-

ззз

-3BS-MTX,

PD750108GB(A)-

ззз

-3BS-MTX

IC : Internally connected (Connect directly to V

PIN NAMES

BUZ

Buzzer Clock

P70-P73

: Port 7

CL1, CL2

Main System Clock (RC)

P80, P81

: Port 8

Internally Connected

PCL

: Programmable Clock

INT0, 1, 4 :

External Vectored Interrupt 0, 1, 4

PTO0, PTO1 : Programmable Timer Output 0, 1

INT2

External Test Input 2

RESET

: Reset

KR0-KR7

Key Return 0-7

SB0, SB1

: Serial Bus 0, 1

No connection

SCK

: Serial Clock

P00-P03

Port 0

: Serial Input

P10-P13

Port 1

: Serial Output

P20-P23

Port 2

TI0

: Timer Input 0

P30-P33

Port 3

: Positive Power Supply

P40-P43

Port 4

: Ground

P50-P53

Port 5

XT1, XT2

: Subsystem Clock (Crystal)

P60-P63

Port 6

P72/KR6

P71/KR5

P70/KR4

P63/KR3

P62/KR2

P61/KR1

P60/KR0

P53

P52

P51

P50

P13/TI0

P00/INT4

P01/SCK

P02/SO/SB0

P03/SI/SB1

P80

P81

P30

P31

P32

P33

P43

P42

P41

P40

XT1

XT2

RESET

CL1

CL2

P73/KR7

P20/PTO0

P21/PTO1

P22/PCL

P23/BUZ

P10/INT0

P11/INT1

P12/INT2

12 13 14 15 16 17 18 19 20 21 22

44 43 42 41 40 39 38 37 36 35 34

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

2. BLOCK DIAGRAM

Note The ROM capacity depends on the product.

BIT SEQ.

BUFFER (16)

PORT 0

P00 - P03

PORT 1

PORT 2

PORT 3

P30 - P33

PORT 4

P40 - P43

PORT 5

P50 - P53

PORT 6

P60 - P63

RESET

CPU CLOCK

STAND BY

CONTROL

CL2

CL1

XT2

XT1

SYSTEM CLOCK
GENERATOR

MAIN

SUB

CLOCK

DIVIDER

CLOCK
OUTPUT
CONTROL

fx/2

PCL/P22

GENERAL
REGISTER

DATA

MEMORY

(RAM)

512

4 BITS

BANK

SBS

SP (8)

ALU

PROGRAM

COUNTER

PROGRAM

MEMORY

Note

(ROM)

DECODE

AND

CONTROL

BASIC INTERVAL
TIMER/
WATCHDOG
TIMER

TI0/P13

INTBT

RESET

8-BIT
TIMER/EVENT
COUNTER #0

PTO0/P20

INTT0

TOUT0

8-BIT TIMER
COUNTER #1

INTT1

TOUT0

CLOCKED
SERIAL
INTERFACE

SI/SB1/P03

INTERRUPT

CONTROL

INT0/P10

SO/SB0/P02

SCK/P01

INT1/P11

INT2/P12

INT4/P00

KR0/P60-

KR7/P73

WATCH

TIMER

PORT 7

P70 - P73

PORT 8

P80, P81

P10 - P13

P20 - P23

PTO1/P21

INTCSI

INTW

BUZ/P23

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

3. PIN FUNCTIONS

3.1 Port Pins

Notes 1. The circle (

) indicates the Schmitt trigger input.

2. When pull-up resistors that can be specified with the mask option are not incorporated (when pins are

used as N-ch open-drain input ports), the input leak low current increases when an input instruction or

bit operation instruction is executed.

I/O circuit

type

Note 1

-A

-B

-C

E-B

M-D

-A

E-B

When reset

Input

High level (when

pull-up resistors

are provided) or

high impedance

High level (when

pull-up resistors

are provided) or

high impedance

Input

8-bit

I/O

Function

4-bit input port (PORT0).

For P01 - P03, built-in pull-up resistors

can be connected by software in units

of 3 bits.

4-bit input port (PORT1).

Built-in pull-up resistors can be

connected by software in units of 4 bits.

A noise eliminator can be selected only

when the P10/INT0 pin is used.

4-bit I/O port (PORT2).

Built-in pull-up resistors can be

connected by software in units of 4 bits.

Programmable 4-bit I/O port (PORT3).

I/O can be specified bit by bit. Built-in

pull-up resistors can be connected by

software in units of 4 bits.

N-ch open-drain 4-bit I/O port (PORT4).

A pull-up resistor can be provided bit by

bit (mask option). Withstand voltage is

13 V in open-drain mode.

N-ch open-drain 4-bit I/O port (PORT5).

A pull-up resistor can be provided bit by

bit (mask option). Withstand voltage is

13 V in open-drain mode.

Programmable 4-bit I/O port (PORT6).

I/O can be specified bit by bit. Built-in

pull-up resistors can be connected by

software in units of 4 bits.

4-bit I/O port (PORT7).

Built-in pull-up resistors can be

connected by software in units of 4 bits.

2-bit I/O port (PORT8).

Built-in pull-up resistors can be

connected by software in units of 2

bits.

Pin name

P00

P01

P02

P03

P10

P11

P12

P13

P20

P21

P22

P23

P30 - P33

P40 - P43

Note 2

P50 - P53

Note 2

P60

P61

P62

P63

P70

P71

P72

P73

P80

P81

Input/

output

Input

I/O

Input

I/O

Shared

INT4

SCK

SO/SB0

SI/SB1

INT0

INT1

INT2

TI0

PTO0

PTO1

PCL

BUZ

KR0

KR1

KR2

KR3

KR4

KR5

KR6

KR7

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

3.2 Non-Port Pins

Notes 1. The circle (

) indicates the Schmitt trigger input.

2. With a noise eliminator/asynchronously selectable

3. Asynchronous

Function

Inputs external event pulse to the timer/event

counter

Timer/event counter output

Timer counter output

Clock output

Arbitrary frequency output (for buzzer output or

system clock trimming)

Serial clock I/O

Serial data output

Serial data bus I/O

Serial data input

Serial data bus I/O

Edge detection vectored interrupt input (both

rising and falling edges are detected)

Rising edge detection testable input

Falling edge detection testable input

Pin for connecting a resistor (R) or capacitor (C)

for main system clock oscillation. An external

clock cannot be input.

Crystal connection pin for subsystem clock

generation. When external clock signal is used, it

is applied to XT1, and it reverse phase signal is

applied to XT2.

XT1 can be used as a 1-bit input (test).

System reset input (active low)

Internally connected. (To be connected directly to

)

Positive power supply

Ground potential

Input/

output

Input

Output

I/O

Input

When reset

Input

Edge detection vectored interrupt input

(detection edge selectable). A noise eliminator

can be selected when INT0/P10 is used.

Shared

P13

P20

P21

P22

P23

P01

P02

P03

P00

P10

P11

P12

P60 - P63

P70 - P73

Note 3

Note 2

Note 3

I/O circuit

type

Note 1

-C

E-B

-A

-B

-C

-A

Pin name

TI0

PTO0

PTO1

PCL

BUZ

SCK

SO/SB0

SI/SB1

INT4

INT0

INT1

INT2

KR0 - KR3

KR4 - KR7

CL1

CL2

XT1

XT2

RESET

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Input state

: To be connected to V

or V

through a separate resistor

Output state : To be left open

Input state

: To be connected to V

or V

through a separate resistor

Output state : To be left open

Input state

: To be connected to V

Output state : To be connected to V

(Do not connect to a pull-up
resistor specified with a mask
option.)

3.4 Connection of Unused Pins

Table 3-1. Connection of Unused Pins

Note When the subsystem clock is not used, set SOS.0 to 1 (not to use the built-

in feedback resistor).

Pin name

Recommended connection

P00/INT4

To be connected to V

or V

P01/SCK

P02/SO/SB0

P03/SI/SB1

To be connected to V

P10/INT0 - P12/INT2

To be connected to V

or V

P13/TI0

P20/PTO0

P21/PTO1

P22/PCL

P23/BUZ

P30 - P33

P40 - P43

P50 - P53

P60/KR0 - P63/KR3

P70/KR4 - P73/KR7

P80, P81

XT1

Note

To be connected to V

or V

XT2

Note

To be left open

To be connected directly to V

To be connected to V

or V

through a

separate resistor

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

MODE/Mk

MODE SWITCH FUNCTION

4.1 Differences between Mk

Mode and Mk

Mode

The CPU of the

PD750108 has two modes (Mk

mode and Mk

mode) and which mode is used is selectable.

Bit 3 of the stack bank selection register (SBS) determines the mode.

З Mk

mode:

This mode has the upward compatibility with the 75X series.

It can be used in the 75XL CPUs having a ROM of up to 16 KB.

З Mk

mode:

This mode is not compatible with the 75X series.

It can be used in all 75XL CPUs, including those having a ROM of 16 KB or more.

Table 4-1 shows the differences between Mk

mode and Mk

mode.

Table 4-1. Differences between Mk

Mode and Mk

Mode

Caution Mk

mode can be used to support a program area larger than 16K bytes in the 75X series or 75XL

series. This mode enhances a software compatibility with products whose program area is larger

than 16K bytes. If Mk

mode is selected, when the subroutine call instruction is executed, the

number of stack bytes (use area) will be increased by one byte for each stack, compared to Mk

mode. When a CALL !addr or CALLF !faddr instruction is executed, it takes one more machine

cycle. Therefore, Mk

mode should be used for applications for which RAM efficiency or

processing capabilities is more critical than a software compatibility.

Number of stack bytes in a

subroutine instruction

BRA !addr1 instruction

CALLA !addr1 instruction

CALL !addr instruction

CALLF !faddr instruction

2 bytes

None

3 machine cycles

2 machine cycles

3 bytes

Available

4 machine cycles

3 machine cycles

mode

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

4.2 Setting of the Stack Bank Selection Register (SBS)

The Mk

mode and Mk

mode are switched by stack bank selection register. Figure 4-1 shows the register

configuration.

The stack bank selection register is set with a 4-bit memory operation instruction. To use the CPU in Mk

mode,

initialize the register to 100

Note

at the beginning of the program. To use the CPU in Mk

mode, initialize it to

000

Note

Specify the desired value in

Figure 4-1. Stack Bank Selection Register Format

Caution The CPU operates in Mk

mode after the RESET signal is issued, because bit 3 of SBS is set to

1. Set bit 3 of SBS to 0 (Mk

mode) to use the CPU in Mk

mode.

SBS0

SBS1

SBS2

SBS3

F84H

Address

SBS

Symbol

Memory bank 0

Memory bank 1

Other settings are inhibited.

mode

Mode switching designation

Bit 2 must be set to 0.

Stack area designation

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

5. MEMORY CONFIGURATION

З Program memory (ROM) : 4,096

8 bits (0000H-0FFFH):

PD750104

6,144

8 bits (0000H-17FFH):

PD750106

8,192

8 bits (0000H-1FFFH):

PD750108

0000H to 0001H

Vector address table for holding the RBE and MBE values and program start address when a RESET signal is

issued (allowing a reset start at an arbitrary address)

0002H to 000DH

Vector address table for holding the RBE and MBE values and program start address for each vectored interrupt

(allowing interrupt processing to be started at an arbitrary address)

0020H to 007FH

Table area referenced by the GETI instruction

Note

The GETI instruction requires only one byte to represent an arbitrary two-byte or three-byte instruction or

two one-byte instructions, reducing the number of program bytes.

З Data memory (RAM)

Data area

: 512

4 bits (000H to 1FFH)

Peripheral hardware area: 128

4 bits (F80H to FFFH)

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Figure 5-1. Program Memory Map (in

PD750104)

Note

Can be used only in the Mk

mode.

Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address

with only the 8 low-order bits of the PC changed.

0 0 0 H

Address

MBE RBE

Internal reset start address

(high-order 4 bits)

0 0 2 H MBE RBE

INTBT/INT4

(high-order 4 bits)

start address

0 0 4 H MBE RBE

INT0

(high-order 4 bits)

start address

0 0 6 H MBE RBE

INT1

(high-order 4 bits)

start address

0 0 8 H MBE RBE

INTCSI

(high-order 4 bits)

start address

0 0 A H MBE RBE

INTT0

(high-order 4 bits)

start address

0 0 C H MBE RBE

INTT1

(high-order 4 bits)

start address

0 2 0 H

0 7 F H

0 8 0 H

7 F F H

8 0 0 H

F F F H

GETI instruction reference table

(low-order 8 bits)

CALLF
! faddr
instruction
entry
address

Branch address
of BR BCXA, BR
BCDE, BR !addr,
BRA !addr1

Note

CALLA !addr1

Note

instruction

CALL !addr
instruction
subroutine entry
address

BR $addr
instruction relative
branch address

BRCB
!caddr
instruction
branch
address

-15 to -1,
+2 to +16

Branch destination
address and
subroutine entry
address when
GETI instruction
is executed

Internal reset start address

INTBT/INT4

start address

INT0

start address

INT1

start address

INTCSI

start address

INTT0

start address

INTT1

start address

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Figure 5-2. Program Memory Map (in

PD750106)

Note

Can be used only in the Mk

mode.

Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address

with only the 8 low-order bits of the PC changed.

0 0 0 0 H

Address

0 0 0 2 H MBE RBE

INTBT/INT4

(high-order 5 bits)

start address

0 0 0 4 H MBE RBE

INT0

(high-order 5 bits)

start address

0 0 0 6 H MBE RBE

INT1

(high-order 5 bits)

start address

0 0 0 8 H MBE RBE

INTCSI

(high-order 5 bits)

start address

0 0 0 A H MBE RBE

INTT0

(high-order 5 bits)

start address

0 0 2 0 H

0 0 7 F H

0 0 8 0 H

0 7 F F H

0 8 0 0 H

MBE RBE

Internal reset start address

(high-order 5 bits)

0 F F F H

1 0 0 0 H

1 7 F F H

GETI instruction reference table

0 0 0 C H MBE RBE

INTT1

(high-order 5 bits)

start address

(low-order 8 bits)

CALLF
!faddr
instruction
entry
address

BRCB !caddr
instruction
branch
address

Branch address
of BR BCXA, BR
BCDE, BR !addr,
BRA !addr1

Note

CALLA !addr1

Note

instruction

CALL !addr
instruction
subroutine entry
address

BR $addr
instruction relative
branch address

-15 to -1,
+2 to +16

Branch destination
address and
subroutine entry
address when GETI
instruction is executed

BRCB !caddr
instruction
branch
address

Internal reset start address

INTBT/INT4

INT0

INT1

INTCSI

INTT0

INTT1

start address

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Figure 5-3. Program Memory Map (in

PD750108)

Note

Can be used only in the Mk

mode.

Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address

with only the 8 low-order bits of the PC changed.

0 0 0 0 H

Address

0 0 0 2 H MBE RBE

INTBT/INT4

(high-order 5 bits)

start address

0 0 0 4 H MBE RBE

INT0

(high-order 5 bits)

start address

0 0 0 6 H MBE RBE

INT1

(high-order 5 bits)

start address

0 0 0 8 H MBE RBE

INTCSI

(high-order 5 bits)

start address

0 0 0 A H MBE RBE

INTT0

(high-order 5 bits)

start address

0 0 2 0 H

0 0 7 F H

0 0 8 0 H

0 7 F F H

0 8 0 0 H

MBE RBE

Internal reset start address

(high-order 5 bits)

0 F F F H

1 0 0 0 H

1 F F F H

GETI instruction reference table

0 0 0 C H MBE RBE

INTT1

(high-order 5 bits)

start address

(low-order 8 bits)

CALLF
!faddr
instruction
entry
address

BRCB !caddr
instruction
branch
address

Branch address
of BR BCXA, BR
BCDE, BR !addr,
BRA !addr1

Note

CALLA !addr1

Note

instruction

CALL !addr
instruction
subroutine entry
address

BR $addr
instruction relative
branch address

-15 to -1,
+2 to +16

Branch destination
address and
subroutine entry
address when GETI
instruction is executed

BRCB !caddr
instruction
branch
address

Internal reset start address

INTBT/INT4

INT0

INT1

INTCSI

INTT0

INTT1

start address

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

When the serial interface function is used, dual-function pins

function as output pins in some operation modes.

4-bit input port

Allows input or output mode setting in units of 4 bits.

Allows input or output mode setting in units of 1 bit.

Operation and feature

Port name

PORT0

PORT1

PORT2

PORT3

PORT4

PORT5

PORT6

PORT7

PORT8

6. PERIPHERAL HARDWARE FUNCTIONS

6.1 Digital I/O Ports

The

PD750108 has the following three types of I/O port:

З 8 CMOS input pins (PORT0 and PORT1)

З 18 CMOS I/O pins (PORT2, PORT3, and PORT6 to PORT8)

З 8 N-ch open-drain I/O pins (PORT4 and PORT5)

Total: 34 pins

Table 6-1. Digital Ports and Their Features

6.2 Clock Generator

The clock generator generates clocks which are supplied to the peripheral hardware in the CPU. Figure 6-1 shows

the configuration of the clock generator.

Operation of the clock generator is specified by the processor clock control register (PCC) and system clock control

The main system clock and subsystem clock are used.

The instruction execution time can be made variable.

З 4, 8, 16, or 64

s (when the main system clock is at 1.0 MHz)

З 2, 4, 8, or 32

s (when the main system clock is at 2.0 MHz)

З 122

s (when the subsystem clock is at 32.768 kHz)

Allows input or output mode setting in

units of 4 bits. Whether to use pull-up

resistors can be specified bit by bit with

the mask option.

Allows input or output mode setting in

units of 1 bit.

Allows input or output mode setting in

units of 4 bits.

Ports 4 and 5 can be

paired, allowing data

I/O in units of 8 bits.

Ports 6 and 7 can be

paired, allowing data

I/O in units of 8 bits.

4-bit input

4-bit I/O

4-bit I/O (N-ch

open-drain can

withstand 13 V)

4-bit I/O

2-bit I/O

Also used as INT4, SCK,

SO/SB0, or SI/SB1.

Also used as INT0, INTI,

INT2 or TI0.

Also used as PTO0,

PTO1, PCL, or BUZ.

Also used as one of KR0

to KR3.

Also used as one of KR4

to KR7.

Allows input or output mode setting in units of 2 bits.

Function

Remarks

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Figure 6-1. Clock Generator Block Diagram

Note

Instruction execution

Remarks 1. f

= Main system clock frequency

2. f

= Subsystem clock frequency

= CPU clock

4. PCC: Processor clock control register

5. SCC: System clock control register

6. One clock cycle (t

) of the CPU clock (

) is equal to one machine cycle of an instruction.

Subsystem
clock generator

Main system
clock generator
RC oscillation

Clock timer

Basic interval timer (BT)

Timer/event counter

Timer counter

Serial interface

Clock timer

INT0 noise eliminator

Clock output circuit

1/1 to 1/4096

Frequency divider

Selec-
tor

Frequency
divider

Oscillator
disable
signal

Internal bus

HALT

Note

STOP

Note

PCC2, PCC3
clear signal

Wait release signal from BT

Standby release signal from
interrupt control circuit

RESET signal

XT1

XT2

CL1

CL2

SCC

SCC3

SCC0

PCC

PCC0

PCC1

PCC2

PCC3

STOP flip-flop

HALT flip-flop

1/2

1/16

1/4

WM.3

CPU

INT0 noise

eliminator

Clock

output
circuit

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

6.3 Control Functions of Subsystem Clock Oscillator

The subsystem clock oscillator of the

PD750108 has two control functions to decrease the supply current.

З The function to select with the software whether to use the built-in feedback resistor

Note

З The function to suppress the supply current by reducing the drive current of the built-in inverter when the supply

voltage is high (V

2.7 V)

Note

When the subsystem clock is not used, set SOS.0 to 1 (not to use the built-in feedback resistor), connect

XT1 to V

or V

, and open XT2. This makes it possible to reduce the supply current required by the

subsystem clock oscillator.

Each function can be used by switching bits 0 and 1 in the sub-oscillator control register (SOS). (See Figure 6-

2.)

Figure 6-2. Subsystem Clock Oscillator

SOS.0

SOS.1

XT1

XT2

Inverter

Feedback resistor

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

6.5 Basic Interval Timer/Watchdog Timer

The basic interval timer/watchdog timer has these functions:

З Interval timer operation which generates a reference timer interrupt

З Operation as a watchdog timer for detecting program crashes and resetting the CPU

З Selection of wait time for releasing the standby mode and counting the wait time

З Reading out the count value

Figure 6-4. Block Diagram of the Basic Interval Timer/Watchdog Timer

Note

Instruction execution

From the clock
generator

Internal bus

MPX

Basic interval timer

(8-bit frequency divider)

Clear signal

BT interrupt
request flag

Vectored
interrupt
request
signal

IRQBT

Wait release
signal for standby
release

Set
signal

BTM3

BTM2

BTM1

BTM0

BTM

SET1

Note

WDTM

Internal
reset signal

SET1

Note

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

6.6 Clock Timer

The

PD750108 contains one channel for a clock timer. The clock timer provides the following functions:

З Sets the test flag (IRQW) with a 0.5 sec interval (when WM0 = 1).

З The standby mode can be released by IRQW.

З The 0.5 second interval can be generated from the subsystem clock (32.768 kHz).

З The time interval can be made 128 times faster by selecting the fast mode. This is convenient for program

debugging, testing, etc.

З Any of the frequencies (f

, f

, or f

can be output to the P23/BUZ pin. This can be used for beep and

system clock frequency trimming.

З The clock can be started from zero seconds by clearing the frequency divider.

Figure 6-5. Clock Timer Block Diagram

Note

When a frequency-divided main system clock is used, 32.768 kHz cannot be selected as the source clock

frequency.

Remark The values in parentheses in the figure above are for f

= 1.0 MHz, f

= 32.768 kHz.

P23/BUZ

Internal bus

Selector

From the
clock
generator

128

(7.8125 kHz)

(32.768 kHz)

Selector

Frequency divider

Selector

INTW
IRQW
set signal

WM7

WM5

WM4

WM3

WM2

WM1

WM0

P23 output
latch

Bit 2 of PMGB

PORT2.3

Output buffer

Clear

32.768 kHz

7.8125 kHz

Bit test instruction

Port 2 input/
output mode

Note

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

6.9 Bit Sequential Buffer: 16 Bits

The bit sequential buffer (BSB) is a data memory specifically provided for bit manipulation. With this buffer,

addresses and bit specifications can be sequentially updated by bit manipulation operation. Therefore, this buffer

is very useful for processing long data in bit units.

Figure 6-9. Bit Sequential Buffer Format

Remarks 1. In pmem.@L addressing, bit specification is shifted according to the L register.

2. In pmem.@L addressing, the bit sequential buffer can be manipulated at any time regardless of MBE/

MBS specification.

BSB3

BSB2

BSB1

BSB0

FC3H

FC2H

FC1H

FC0H

L = FH

L = CH L = BH

L = 8H L = 7H

L = 4H L = 3H

L = 0H

DECS L

INCS L

Address

Bit

L register

Symbol

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

7. INTERRUPT FUNCTIONS AND TEST FUNCTIONS

The

PD750108 has seven interrupt sources and two test sources. One test source, INT2, has two types of edge

detection testable input pins.

The interrupt control circuit of the

PD750108 has the following functions.

(1) Interrupt functions

З Hardware controlled vectored interrupt function which can control whether or not to accept an interrupt using

the interrupt flag (IE

ззз

) and interrupt master enable flag (IME).

З The interrupt start address can be set arbitrarily.

З Multiple interrupt function which can specify the priority by the interrupt priority specification register (IPS)

З Test function of an interrupt request flag (IRQ

ззз

)

(The software can confirm that an interrupt occurred.)

З Release of the standby mode (Interrupts released by an interrupt enable flag can be selected.)

(2) Test functions

Whether test request flags (IRQ

ззз

) are issued can be checked with software.

Release of the standby mode (A test source to be released can be selected with test enable flags.)

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

8. STANDBY FUNCTION

The

PD750108 has two different standby modes (STOP mode and HALT mode) to reduce power dissipation while

waiting for program execution.

Table 8-1. Standby Mode Statuses

Notes 1. Operation is possible only when the main system clock operates.

2. Operation is possible only when the noise eliminator is not selected by bit 2 of the edge detection mode

Instruction for setting

System clock for setting

Clock oscillator

Basic interval

timer/watchdog

timer

Serial interface

Timer/event

counter

Timer counter

Clock timer

External interrupt

CPU

Release signal

STOP mode

STOP instruction

Can be set only when operating on the

main system clock.

The main system clock stops its operation.

Does not operate.

Can operate only when the external SCK

input is selected for the serial clock.

Can operate only when the TI0 pin input is

selected for the count clock.

Does not operate.

Can operate when f

is selected as the

count clock.

INT1, INT2, and INT4 can operate.

Only INT0 cannot operate.

Note 2

Does not operate.

Opera-

tion

status

Item

Mode

An interrupt request signal from hardware whose operation is enabled by the interrupt

enable flag or the generation of a RESET signal

HALT mode

HALT instruction

Can be set either with the main system

clock or the subsystem clock.

Only the CPU clock

stops its operation

(oscillation continues).

Can operate only at main system clock

oscillation.

BT mode : IRQBT is set at the reference

interval.

WT mode : A reset signal is generated

when the BT overflows.

Can operate only when external SCK input

is selected as the serial clock or at main

system clock oscillation.

Can operate only when TI0 pin input is

specified as the count clock or at main

system clock oscillation.

Can operate.

Note 1

Can operate.

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

9. RESET FUNCTION

The

PD750108 is reset with the external reset signal (RESET) or the reset signal received from the basic interval

timer/watchdog timer. When either reset signal is input, the internal reset signal is generated. Figure 9-1 shows the

configuration of the reset circuit.

Figure 9-1. Configuration of Reset Functions

When the RESET signal is generated, all hardware is initialized as indicated in Table 9-1. Figure 9-2 shows the

reset operation timing.

Figure 9-2. Reset Operation by Generation of RESET Signal

Note

56/f

(28

s at 2.0 MHz, 56

s at 1.0 MHz)

WDTM

RESET

Internal reset signal

Reset signal from basic
interval timer/watchdog timer

Internal bus

RESET signal is generated

Operating mode or
standby mode

HALT mode

Operating mode

Internal reset operation

Wait

Note

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Table 9-1. Status of the Hardware after a Reset (1/2)

Program counter (PC)

PSW

Stack pointer (SP)

Stack bank selection register (SBS)

Data memory (RAM)

General-purpose registers (X, A, H, L, D, E, B, C)

Bank selection register (MBS, RBS)

Timer/event

counter

Timer counter

Clock timer

Serial interface

4 low-order bits at address 0000H

in program memory are set in PC

bits 11 to 8, and the data at address

0001H are set in PC bits 7 to 0.

5 low-order bits at address 0000H

in program memory are set in PC

bits 12 to 8, and the data at address

0001H are set in PC bits 7 to 0.

Held

Bit 6 at address 0000H in

program memory is set in RBE,

and bit 7 is set in MBE.

Undefined

1000B

Held

0, 0

Undefined

FFH

0, 0

FFH

0, 0

Held

4 low-order bits at address 0000H

in program memory are set in PC

bits 11 to 8, and the data at address

0001H are set in PC bits 7 to 0.

5 low-order bits at address 0000H

in program memory are set in PC

bits 12 to 8, and the data at address

0001H are set in PC bits 7 to 0.

Undefined

Bit 6 at address 0000H in program

memory is set in RBE, and bit 7 is

set in MBE.

Undefined

1000B

Undefined

0, 0

Undefined

FFH

0, 0

FFH

0, 0

Undefined

Generation of a RESET signal

during operation

Generation of a RESET signal in

a standby mode

Hardware

Carry flag (CY)

Skip flags (SK0 to SK2)

Interrupt status flags (IST0, IST1)

Bank enable flags (MBE, RBE)

PD750104

PD750106, 750108

Counter (BT)

Mode register (BTM)

Watchdog timer enable flag

(WDTM)

Counter (T0)

Modulo register (TMOD0)

Mode register (TM0)

TOE0, TOUT flip-flop

Counter (T1)

Modulo register (TMOD1)

Mode register (TM1)

TOE1, TOUT flip-flop

Mode register (WM)

Shift register (SIO)

Operation mode register (CSIM)

SBI control register (SBIC)

Slave address register (SVA)

Basic interval

timer/ watchdog

timer

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Table 9-1. Status of the Hardware after a Reset (2/2)

Reset (0)

0, 0, 0

Off

Clear (0)

Undefined

Generation of a RESET signal

during operation

Clock generator,

clock output cir-

cuit

Interrupt

Digital ports

Processor clock control register (PCC)

System clock control register (SCC)

Clock output mode register (CLOM)

Interrupt request flag (IRQ

ззз

)

Interrupt enable flag (IE

ззз

)

Priority selection register (IPS)

INT0, INT1, and INT2 mode registers

(IM0, IM1, IM2)

Output buffer

Output latch

I/O mode registers (PMGA, PMGB,

PMGC)

Pull-up resistor specification registers

(POGA, POGB)

Generation of a RESET signal in

a standby mode

Hardware

Sub-oscillator control register (SOS)

Reset (0)

0, 0, 0

Off

Clear (0)

Held

Bit sequential buffers (BSB0 to BSB3)

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Description

Representation

format

11. INSTRUCTION SET

(1) Operand identifier and its descriptive method

The operands are described in the operand column of each instruction according to the descriptive method for

the operand format of the appropriate instructions. (For details, refer to the RA75X Assembler Package User's

Manual: Language (EEU-1363).) For descriptions in which alternatives exist, one element should be selected.

Capital letters and plus and minus signs are keywords; therefore, they should be described as they are.

For immediate data, the appropriate numerical values or labels should be described.

The symbols of register flags can be used as a label instead of mem, fmem, pmem, and bit. (For details, refer

to the

PD750108 User's Manual (U11330E).) However, there are some restrictions on usable labels for fmem

and pmem.

Note Only even address can be specified for 8-bit data processing.

X, A, B, C, D, E, H, L

X, B, C, D, E, H, L

XA, BC, DE, HL

BC, DE, HL

BC, DE

XA, BC, DE, HL, XA', BC', DE', HL'

BC, DE, HL, XA', BC', DE', HL'

HL, HL+, HL-, DE, DL

DE, DL

4-bit immediate data or label

8-bit immediate data or label

Note

2-bit immediate data or label

FB0H - FBFH, FF0H - FFFH immediate data or label

FC0H - FFFH immediate data or label

0000H - 0FFFH immediate data or label (

PD750104)

0000H - 17FFH immediate data or label (

PD750106)

0000H - 1FFFH immediate data or label (

PD750108)

0000H - 0FFFH immediate data or label (

PD750104)

0000H - 17FFH immediate data or label (

PD750106)

0000H - 1FFFH immediate data or label (

PD750108)

12-bit immediate data or label

11-bit immediate data or label

20H - 7FH immediate data (however, bit 0 = 0) or label

PORT0 - PORT8

IEBT, IET0, IET1, IE0 - IE2, IE4, IECSI, IEW

RB0 - RB3

MB0, MB1, MB15

reg

reg1

rp1

rp2

rp'

rp'1

rpa

rpa1

mem

bit

fmem

pmem

addr

addr1(for Mk

mode only)

caddr

faddr

taddr

PORTn

ззз

RBn

MBn

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

(2) Symbol definitions in operation description

A register; 4-bit accumulator

B register

C register

D register

E register

H register

L register

X register

XA'

Extended register pair (XA')

BC'

Extended register pair (BC')

DE'

Extended register pair (DE')

HL'

Extended register pair (HL')

Program counter

Stack pointer

Carry flag; Bit accumulator

PSW

Program status word

MBE

Memory bank enable flag

RBE

PORTn :

Port n (n = 0 to 8)

IME

Interrupt master enable flag

IPS

Interrupt priority specification register

ззз

Interrupt enable flag

RBS

MBS

Memory bank selection register

PCC

Processor clock control register

Address bit delimiter

(

зз

)

Contents addressed by

зз

Hexadecimal data

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

(3) Symbols used for the addressing area column

Remarks 1. MB indicates the memory bank that can be accessed.

2. For *2, MB = 0 regardless of MBE and MBS settings.

3. For *4 and *5, MB = 15 regardless of MBE and MBS settings.

4. For *6 to *11, each addressable area is indicated.

(4) Description of machine cycle column

S indicates the number of machine cycles necessary for skipping any skip instruction. The value of S changes

as follows:

When no skip is performed

: S = 0

When a 1-byte or 2-byte instruction is skipped : S = 1

When a 3-byte instruction

Note

is skipped

: S = 2

Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr, and CALLA !addr1 instructions.

Caution The GETI instruction is skipped in one machine cycle.

One machine cycle is equal to one cycle (= t

) of the CPU clock (

), and four types of times are available for

selection according to the PCC setting.

* 1

MB = MBE З MBS (MBS = 0, 1, 15)

* 2

MB = 0

* 3

MBE = 0

MBE = 1

MB = 0 (000H - 07FH), MB = 15 (F80H - FFFH)

MB = MBS (MBS = 0, 1, 15)

* 4

MB = 15, fmem = FB0H - FBFH, FF0H - FFFH

* 5

MB = 15, pmem = FC0H - FFFH

* 6

addr = 0000H - 0FFFH (

PD750104), 0000H - 17FFH (

PD750106)

0000H - 1FFFH (

PD750108)

* 7

addr, addr1 = (Current PC) - 15 to (Current PC) - 1

(Current PC) + 2 to (Current PC) + 16

* 8

caddr = 0000H - 0FFFH ( PD750104)

0000H - 0FFFH (PC

= 0:

PD750106, 750108)

1000H - 17FFH (PC

= 1:

PD750106)

1000H - 1FFFH (PC

= 1:

PD750108)

* 9

faddr = 0000H - 07FFH

* 10

taddr = 0020H - 007FH

Data memory
addressing

Program memory
addressing

mode only

addr1 =

0000H - 0FFFH ( PD750104)

0000H - 17FFH (

PD750106)

0000H - 1FFFH (

PD750108)

* 11

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Group

Transfer

Table

reference

Mne-

monic

MOV

XCH

MOVT

Operand

A, #n4

reg1, #n4

XA, #n8

HL, #n8

rp2, #n8

A, @HL

A, @HL+

A, @HL-

A, @rpa1

XA, @HL

@HL, A

@HL, XA

A, mem

XA, mem

mem, A

mem, XA

A, reg

XA, rp'

reg1, A

rp'1, XA

A, @HL

A, @HL+

A, @HL-

A, @rpa1

XA, @HL

A, mem

XA, mem

A, reg1

XA, rp'

XA, @PCDE

XA, @PCXA

XA, @BCDE

XA, @BCXA

Bytes

Machin-

ing

cycle

2 + S

Skip

condition

String A

String B

L = 0

L = FH

L = 0

L = FH

Address-

ing area

Operation

reg1

rp2

(HL)

(HL), then L

L + 1

(HL), then L

L - 1

(rpa1)

(HL)

(mem)

reg

rp'

reg1

rp'1

(HL)

(HL), then L

L + 1

(HL), then L

L - 1

(rpa1)

(HL)

(mem)

reg1

rp'

PD750104

(PC

11-8

+ DE)

ROM

PD750106, 750108

(PC

12-8

+ DE)

ROM

PD750104

(PC

11-8

+ XA)

ROM

PD750106, 750108

(PC

12-8

+ XA)

ROM

(BCDE)

ROM

Note

(BCXA)

ROM

Note

Set register B to 0 in the

PD750104. Only the LSB is valid in register B in the

PD750106 and

PD750108.

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Group

Bit transfer

Arithme-

tic

Accumulator

manipulation

Increment/

decrement

Mne-

monic

MOV1

ADDS

ADDC

SUBS

SUBC

AND

XOR

RORC

NOT

INCS

DECS

Operand

CY, fmem.bit

CY, pmem.@L

CY, @H+mem.bit

fmem.bit, CY

pmem.@L, CY

@H+mem.bit, CY

A, #n4

XA, #n8

A, @HL

XA, rp'

rp'1, XA

A, @HL

XA, rp'

rp'1, XA

A, @HL

XA, rp'

rp'1, XA

A, @HL

XA, rp'

rp'1, XA

A, #n4

A, @HL

XA, rp'

rp'1, XA

A, #n4

A, @HL

XA, rp'

rp'1, XA

A, #n4

A, @HL

XA, rp'

rp'1, XA

reg

rp1

@HL

mem

reg

rp'

Bytes

Machin-

ing

cycle

1 + S

2 + S

1 + S

2 + S

1 + S

2 + S

1 + S

2 + S

1 + S

2 + S

Skip

condition

carry

borrow

reg = 0

rp1 = 00H

(HL) = 0

(mem) = 0

reg = FH

rp' = FFH

Address-

ing area

Operation

(fmem.bit)

(pmem

7-2

+ L

3-2

.bit(L

1-0

))

(H + mem

3-0

.bit)

(fmem.bit)

(pmem

7-2

+ L

3-2

.bit(L

1-0

))

(H + mem

3-0

.bit)

A + n4

XA + n8

A + (HL)

XA + rp'

rp'1

rp'1 + XA

A, CY

A + (HL) + CY

XA, CY

XA + rp' + CY

rp'1, CY

rp'1 + XA + CY

A - (HL)

XA - rp'

rp'1

rp'1 - XA

A, CY

A - (HL) - CY

XA, CY

XA - rp' - CY

rp'1, CY

rp'1 - XA - CY

(HL)

rp'

rp'1

(HL)

rp'

rp'1

(HL)

rp'

rp'1

, A

CY, A

n-1

reg

reg + 1

rp1

rp1 + 1

(HL)

(HL) + 1

(mem)

(mem) + 1

reg

reg - 1

rp'

rp' - 1

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Group

Compari-

son

Carry flag

manipula-

tion

Memory

bit

manipula-

tion

Mne-

monic

SKE

SET1

CLR1

SKT

NOT1

SET1

CLR1

SKT

SKF

SKTCLR

AND1

OR1

XOR1

Operand

reg, #n4

@HL, #n4

A, @HL

XA, @HL

A, reg

XA, rp'

mem.bit

fmem.bit

pmem. @L

@H+mem.bit

mem.bit

fmem.bit

pmem. @L

@H+mem.bit

mem.bit

fmem.bit

pmem. @L

@H+mem.bit

mem.bit

fmem.bit

pmem. @L

@H+mem.bit

fmem.bit

pmem. @L

@H+mem.bit

CY, fmem.bit

CY, pmem. @L

CY, @H+mem.bit

CY, fmem.bit

CY, pmem. @L

CY, @H+mem.bit

CY, fmem.bit

CY, pmem.@L

CY, @H+mem.bit

Bytes

Machin-

ing

cycle

2 + S

1 + S

2 + S

1 + S

2 + S

Skip

condition

reg = n4

(HL) = n4

A = (HL)

XA = (HL)

A = reg

XA = rp'

CY = 1

(mem.bit) = 1

(fmem.bit) = 1

(pmem.@L) = 1

(@H + mem.bit) = 1

(mem.bit) = 0

(fmem.bit) = 0

(pmem.@L) = 0

(@H + mem.bit) = 0

(fmem.bit) = 1

(pmem.@L) = 1

(@H + mem.bit) = 1

Address-

ing area

Operation

Skip if reg = n4

Skip if (HL) = n4

Skip if A = (HL)

Skip if XA = (HL)

Skip if A = reg

Skip if XA = rp'

Skip if CY = 1

(mem.bit)

(fmem.bit)

(pmem

7-2

+ L

3-2

.bit(L

1-0

))

(H + mem

3-0

.bit)

(mem.bit)

(fmem.bit)

(pmem

7-2

+ L

3-2

.bit(L

1-0

))

(H + mem

3-0

.bit)

Skip if (mem.bit) = 1

Skip if (fmem.bit) = 1

Skip if (pmem

7-2

+ L

3-2

.bit(L

1-0

)) = 1

Skip if (H + mem

3-0

.bit) = 1

Skip if (mem.bit) = 0

Skip if (fmem.bit) = 0

Skip if (pmem

7-2

+ L

3-2

.bit(L

1-0

)) = 0

Skip if (H + mem

3-0

.bit) = 0

Skip if (fmem.bit) = 1 and clear

Skip if (pmem

7-2

+ L

3-2

.bit(L

1-0

)) = 1 and clear

Skip if (H + mem

3-0

.bit) = 1 and clear

(fmem.bit)

(pmem

7-2

+ L

3-2

.bit(L

1-0

))

(H + mem

3-0

.bit)

(fmem.bit)

(pmem

7-2

+ L

3-2

.bit(L

1-0

))

(H + mem

3-0

.bit)

(fmem.bit)

(pmem

7-2

+ L

3-2

.bit(L

1-0

))

(H + mem

3-0

.bit)

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Group

Branch

Mne-

monic

Note

Operand

addr

addr1

!addr

$addr

$addr1

Skip

condition

Address-

ing area

*11

Note

The shaded portion is supported in Mk

mode only. The other portions are supported in Mk

mode only.

Bytes

Machin-

ing

cycle

Operation

PD750104

11-0

addr

The assembler selects the most

adequate instruction from BR !addr,

BRCB !caddr, or BR $addr.

PD750106, 750108

12-0

addr

The assembler selects the most

adequate instruction from BR !addr,

BRCB !caddr, or BR $addr.

PD750104

11-0

addr1

The assembler selects the most

adequate instruction from

instructions below.

З BR !addr

З BRA !addr1

З BRCB !caddr

З BR $addr1

PD750106, 750108

12-0

addr1

The assembler selects the most

adequate instruction from

instructions below.

З BR !addr

З BRA !addr1

З BRCB !caddr

З BR $addr1

PD750104

11-0

addr

PD750106, 750108

12-0

addr

PD750104

11-0

addr

PD750106, 750108

12-0

addr

PD750104

11-0

addr1

PD750106, 750108

12-0

addr1

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Group

Branch

Subrou-
tine stack
control

Mne-

monic

BRA

Note 3

BRCB

CALLA

Note 3

Operand

PCDE

PCXA

BCDE

BCXA

!addr1

!caddr

!addr1

Bytes

Machin-

ing

cycle

Skip

condition

Address-

ing area

*11

Operation

PD750104

11-0

11-8

+ DE

PD750106, 750108

12-0

12-8

+ DE

PD750104

11-0

11-8

+ XA

PD750106, 750108

12-0

12-8

+ XA

PD750104

11-0

BCDE

Note 1

PD750106, 750108

12-0

BCDE

Note 2

PD750104

11-0

BCXA

Note 1

PD750106, 750108

12-0

BCXA

Note 2

PD750104

11-0

addr1

PD750106, 750108

12-0

addr1

PD750104

11-0

caddr

11-0

PD750106, 750108

12-0

+ caddr

11-0

PD750104

(SP - 2)

, MBE, RBE

(SP - 6) (SP - 3) (SP - 4)

11-0

(SP - 5)

0, 0, 0, 0

11-0

addr1, SP

SP - 6

PD750106, 750108

(SP - 2)

, MBE, RBE

(SP - 6) (SP - 3) (SP - 4)

11-0

(SP - 5)

0, 0, 0, PC

12-0

addr1, SP

SP - 6

Notes 1. Set register B to 0.

2. Only the LSB is valid in register B.

3. The shaded portion is supported in Mk

mode only. The other portions are supported in Mk

mode

only.

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Group

Subrou-
tine stack
control

Mne-

monic

CALL

Note

CALLF

Note

Operand

!addr

!faddr

Bytes

Machin-

ing

cycle

Skip

condition

Address-

ing area

Operation

PD750104

(SP - 3)

MBE, RBE, 0, 0

(SP - 4) (SP - 1) (SP - 2)

11-0

addr, SP

SP - 4

PD750106, 750108

(SP - 3)

MBE, RBE, 0, PC

(SP - 4) (SP - 1) (SP - 2)

11-0

12-0

addr, SP

SP - 4

PD750104

(SP - 2)

, MBE, RBE

(SP - 6) (SP - 3) (SP - 4)

11-0

(SP - 5)

0, 0, 0, 0

11-0

addr, SP

SP - 6

PD750106, 750108

(SP - 2)

, MBE, RBE

(SP - 6) (SP - 3) (SP - 4)

11-0

(SP - 5)

0, 0, 0, PC

12-0

addr, SP

SP - 6

PD750104

(SP - 3)

MBE, RBE, 0, 0

(SP - 4) (SP - 1) (SP - 2)

11-0

0 + faddr, SP

SP - 4

PD750106, 750108

(SP - 3)

MBE, RBE, 0, PC

(SP - 4) (SP - 1) (SP - 2)

11-0

12-0

00 + faddr, SP

SP - 4

PD750104

(SP - 2)

, MBE, RBE

(SP - 6) (SP - 3) (SP - 4)

11-0

(SP - 5)

0, 0, 0, 0

11-0

0 + faddr, SP

SP - 6

PD750106, 750108

(SP - 2)

, MBE, RBE

(SP - 6) (SP - 3) (SP - 4)

11-0

(SP - 5)

0, 0, 0, PC

12-0

00 + faddr, SP

SP - 6

Note The shaded portion is supported in Mk

mode only. The other portions are supported in Mk

mode only.

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Group

Subrou-
tine stack
control

Mne-

monic

RET

Note

RETS

Note

Operand

Bytes

Machin-

ing

cycle

3 + S

Skip

condition

Uncondition

Address-

ing area

Operation

PD750104

11-0

(SP) (SP + 3) (SP + 2)

MBE, RBE, 0, 0

(SP + 1), SP

SP + 4

PD750106, 750108

11-0

(SP) (SP + 3) (SP + 2)

MBE, RBE, 0, PC

(SP + 1)

SP + 4

PD750104

, MBE, RBE

(SP + 4)

0, 0, 0, 0

(SP + 1)

11-0

(SP) (SP + 3) (SP + 2)

SP + 6

PD750106, 750108

, MBE, RBE

(SP + 4)

MBE, 0, 0, PC

(SP + 1)

11-0

(SP) (SP + 3) (SP + 2)

SP + 6

PD750104

MBE, RBE, 0, 0

(SP + 1)

11-0

(SP) (SP + 3) (SP + 2)

SP + 4

then skip unconditionally

PD750106, 750108

MBE, RBE, 0

(SP + 1)

11-0

(SP) (SP + 3) (SP + 2)

SP + 4

then skip unconditionally

PD750104

0, 0, 0, 0

(SP + 1)

11-0

(SP) (SP + 3) (SP + 2)

, MBE, RBE

(SP + 4)

SP + 6

then skip unconditionally

PD750106, 750108

0, 0, 0, PC

(SP + 1)

11-0

(SP) (SP + 3) (SP + 2)

, MBE, RBE

(SP + 4)

SP + 4

then skip unconditionally

Note The shaded portion is supported in Mk

mode only. The other portions are supported in Mk

mode only.

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Group

Subrou-
tine stack
control

Interrupt

control

Input/

output

CPU

control

Mne-

monic

RETI

Note 1

PUSH

POP

Note 2

OUT

Note 2

HALT

STOP

NOP

Operand

ззз

A, PORTn

XA, PORTn

PORTn, A

PORTn, XA

Bytes

Machin-

ing

cycle

Skip

condition

Address-

ing area

Operation

PD750104

MBE, RBE, 0, 0

(SP + 1)

11-0

(SP) (SP + 3) (SP + 2)

PSW

(SP + 4) (SP + 5), SP

SP + 6

PD750106, 750108

MBE, RBE, 0, PC

(SP + 1)

11-0

(SP) (SP + 3) (SP + 2)

PSW

(SP + 4) (SP + 5), SP

SP + 6

PD750104

0, 0, 0, 0

(SP + 1)

11-0

(SP) (SP + 3) (SP + 2)

PSW

(SP + 4) (SP + 5), SP

SP + 6

PD750106, 750108

0, 0, 0, PC

(SP + 1)

11-0

(SP) (SP + 3) (SP + 2)

PSW

(SP + 4) (SP + 5), SP

SP + 6

(SP - 1)(SP - 2)

rp, SP

SP - 2

(SP - 1)

MBS, (SP - 2)

RBS,

SP - 2

(SP + 1)(SP), SP

SP + 2

MBS

(SP + 1), RBS

(SP),

SP + 2

IME (IPS.3)

ззз

IME (IPS.3)

ззз

PORTn

(n = 0 - 8)

PORTn

,PORTn

(n = 4, 6)

PORTn

(n = 2 - 8)

PORTn

,PORTn

(n = 4, 6)

Set HALT Mode (PCC.2

Set STOP Mode (PCC.3

No Operation

Notes 1. The shaded portion is supported in Mk

mode only. The other portions are supported in Mk

mode

only.

2. When executing the IN/OUT instruction, MBE must be set to 0 or MBE and MBS must be set to 1 and

15, respectively.

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Group

Special

Mne-

monic

SEL

GETI

Notes 1, 2

Operand

RBn

MBn

taddr

Bytes

Machin-

ing

cycle

Skip

condition

Depends

on the

referenced

instruction.

Depends

on the

referenced

instruction.

Depends

on the

referenced

instruction.

Address-

ing area

*10

Operation

RBS

n (n = 0 - 3)

MBS

n (n = 0, 1, 15)

PD750104

When the TBR instruction is used

11-0

(taddr)

3-0

+ (taddr + 1)

When the TCALL instruction is used

(SP - 4) (SP - 1) (SP - 2)

11-0

(SP - 3)

MBE, RBE, 0, 0

11-0

(taddr)

3-0

+ (taddr + 1)

SP - 4

When an instruction other than the

TBR and TCALL instructions is used

Execution of (taddr)(taddr + 1)

instruction

PD750106, 750108

When the TBR instruction is used

12-0

(taddr)

4-0

+ (taddr + 1)

When the TCALL instruction is used

(SP - 4) (SP - 1) (SP - 2)

11-0

(SP - 3)

MBE, RBE, 0, PC12

12-0

(taddr)

4-0

+ (taddr + 1)

SP - 4

When an instruction other than the

TBR and TCALL instructions is used

Execution of (taddr)(taddr + 1)

instruction

PD750104

When the TBR instruction is used

11-0

(taddr)

3-0

+ (taddr + 1)

When the TCALL instruction is used

(SP - 6) (SP - 3) (SP - 4)

11-0

(SP - 5)

0, 0, 0, 0

(SP - 2)

, MBE, RBE

11-0

(taddr)

3-0

+ (taddr + 1)

SP - 6

When an instruction other than the TBR

and TCALL instructions is used

Execution of (taddr)(taddr + 1)

instruction

Notes 1. The shaded portion is supported in Mk

mode only. The other portions are supported in Mk

mode

only.

2. TBR and TCALL instructions are assembler pseudo instructions to define tables used for GETI

instructions.

........................................................

.....................

.......................................................................

.....................

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Group

Special

Mne-

monic

GETI

Notes 1, 2

Operand

taddr

Bytes

Machin-

ing

cycle

Skip

condition

Depends

on the

referenced

instruction.

Address-

ing area

*10

Operation

PD750106, 750108

When the TBR instruction is used

12-0

(taddr)

4-0

+ (taddr + 1)

When the TCALL instruction is used

(SP - 6) (SP - 3) (SP - 4)

11-0

(SP - 5)

0, 0, 0, PC

(SP - 2)

, MBE, RBE

12-0

(taddr)

4-0

+ (taddr + 1)

SP - 6

When an instruction other than the TBR

and TCALL instructions is used

Execution of (taddr)(taddr + 1)

instruction

Notes 1. The shaded portion is supported in Mk

mode only.

2. TBR and TCALL instructions are assembler pseudo instructions to define tables used for GETI

instructions.

.......................................................................

.....................

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

12. ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS (T

= 25

Caution Absolute maximum ratings are rated values beyond which physical damage will be caused to the

product; if the rated value of any of the parameters in the above table is exceeded, even

momentarily, the quality of the product may deteriorate. Always use the product within its rated

values.

CAPACITANCE (T

= 25

C, V

= 0 V)

Unit

Rated value

-0.3 to +7.0

-0.3 to V

+ 0.3

-0.3 to V

+ 0.3

-0.3 to +14.0

-0.3 to V

+ 0.3

-10

-30

220

-40 to +85

-65 to +150

Conditions

Other than ports 4 and 5

Ports

With a built-in pull-up resistor

4 and 5

With N-ch open drain

Each pin

Total of all pins

Each pin

Total of all pins

Parameter

Supply voltage

Input voltage

Output voltage

High-level output current

Low-level output current

Operating ambient temperature

Storage temperature

Symbol

stg

Parameter

Input capacitance

Output capacitance

I/O capacitance

Symbol

OUT

MAX.

Unit

TYP.

Conditions

f = 1 MHz

0 V for pins other than pins to be

measured

MIN.

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Recommended

constant

CHARACTERISTICS OF THE MAIN SYSTEM CLOCK OSCILLATOR (T

= -40 to +85

C, V

= 1.8 to 5.5 V)

Note

The oscillator frequency indicates only the oscillator characteristics. See AC characteristics for the

instruction execution time and oscillator frequency characteristics.

Caution When the main system clock oscillator is used, conform to the following guidelines when wiring

at the portions surrounded by dotted lines in the figures above to eliminate the influence of the

wiring capacity.

The wiring must be as short as possible.

Other signal lines must not run in these areas.

Any line carrying a high fluctuating current must be kept away as far as possible.

The grounding point of the capacitor of the oscillator must have the same potential as that

of V

It must not be grounded to ground patterns carrying a large current.

No signal must be taken from the oscillator.

TYP.

Parameter

Oscillator frequency (f

)

Note

MIN.

0.4

MAX.

2.0

Unit

MHz

Conditions

Resonator

RC
oscillator

CL1

CL2

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Recommended
constant

Resonator

Parameter

kHz

Unit

100

32.768

1.0

Conditions

Crystal

External
clock

Oscillator frequency (f

)

Note 1

Oscillation settling time

Note 2

XT1 input frequency (f

)

Note 1

XT1 input high/low level width
(t

XTH

, t

XTL

)

CHARACTERISTICS OF THE SUBSYSTEM CLOCK OSCILLATOR (T

= -40 to +85

C, V

= 1.8 to 5.5 V)

Notes 1. The oscillator frequency and input frequency indicate only the oscillator characteristics. See the item

of AC characteristics for the instruction execution time.

2. The oscillation settling time means the time required for the oscillation to settle after V

is applied.

Caution When the subsystem clock oscillator is used, conform to the following guidelines when wiring

at the portions of surrounded by dotted lines in the figures above to eliminate the influence of

the wiring capacity.

З The wiring must be as short as possible.

З Other signal lines must not run in these areas.

З Any line carrying a high fluctuating current must be kept away as far as possible.

З The grounding point of the capacitor of the oscillator must have the same potential as that of

З It must not be grounded to ground patterns carrying a large current.

З No signal must be taken from the oscillator.

When the subsystem clock is used, pay special attention to its wiring; the subsystem clock

oscillator has low amplification to minimize current consumption and is more likely to malfunc-

tion due to noise than the main system clock oscillator.

MIN.

TYP.

MAX.

XT1

XT2

XT1

XT2

= 4.5 to 5.5 V

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

DC CHARACTERISTICS (T

= -40 to +85

C, V

= 1.8 to 5.5 V)

Parameter Symbol

IH1

IH2

IH3

IH4

IL1

IL2

IL3

OL1

OL2

LIH1

LIH2

LIH3

LIL1

LIL2

LIL3

LOH1

LOH2

LOL

0.7V

0.9V

0.8V

0.9V

0.7V

0.9V

0.7V

0.9V

- 0.1

- 0.5

SCK, SO,
and ports
2 to 8

= 5.0 V

= 3.0 V

0.2

-10

-3

100

150

0.3V

0.1V

0.2V

0.1V

0.1

2.0

0.4

0.2V

-3

-20

-3

-30

-27

-8

-3

200

MIN. TYP. MAX. Unit

Low-level output

current

High-level input

voltage

Low-level input

voltage

High-level output voltage

Low-level output

voltage

High-level input

leakage current

Low-level input

leakage current

High-level output

leakage current

Low-level output

leakage current

Built-in pull-up

resistor

Ports 4 and 5 (With N-ch

open drain)

When the input instruction

is executed

With a Built-in pull-up

resistor

With N-ch open drain

Each pin

Total of all pins

Ports 2, 3, and 8

Ports 0, 1, 6, and 7 and RESET

Ports 4 and

XT1

Ports 2 to 5, and 8

Ports 0, 1, 6, and 7 and RESET

XT1

SCK, SO, and ports 2, 3, and 6 to 8 I

= -1.0 mA

SB0, SB1 N-ch open drain Pull-up resistor

1 k

= V

Other than XT1

XT1

= 13 V Ports 4 and 5 (With N-ch open drain)

= 0 V Other than XT1 and ports 4 and 5

XT1

Ports 4 and 5 (With N-ch open drain)

At other than input instruction execution

OUT

= V

SCK, SO/SB0, SB1, and ports 2, 3, and 6

to 8

Ports 4 and 5 (With a built-in pull-up resistor)

OUT

= 13 V Ports 4 and 5 (With N-ch open drain)

OUT

= 0 V

= 0 V Ports 0 to 3 and 6 to 8 (except P00 pin)

Ports 4 and 5 (mask option)

Conditions

2.7 V

5.5 V

1.8 V

< 2.7 V

2.7 V

5.5 V

1.8 V

< 2.7 V

2.7 V

5.5 V

1.8 V

< 2.7 V

2.7 V

5.5 V

1.8 V

< 2.7 V

2.7 V

5.5 V

1.8 V

< 2.7 V

2.7 V

5.5 V

1.8 V

< 2.7 V

= 15 mA, V

= 5.0 V

10%

= 1.6 mA

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Parameter

Power supply

current

Note 1

Conditions

Low-current-

drain

mode

Note 7

DC CHARACTERISTICS (T

= -40 to +85

C, V

= 1.8 to 5.5 V)

Notes 1. This current excludes the current which flows through the built-in pull-up resistors.

2. This value applies also when the subsystem clock oscillates.

3. Value when the processor clock control register (PCC) is set to 0011 and the

PD750108 is operated

in the high-speed mode.

4. Value when the PCC is set to 0000 and the

PD750108 is operated in the low-speed mode.

5. This value applies when the system clock control register (SCC) is set to 1001 to stop the main system

clock pulse and to start the subsystem clock pulse.

6. Mode when the sub-oscillator control register (SOS) is set to 0000.

7. Mode when the SOS is set to 0010.

8. This value applies when the SOS is set to 00

1 and the sub-oscillator feedback resistor is not used (

= don't care).

Symbol

DD1

DD2

DD3

DD4

DD5

Unit

= 5.0 V

10%

Note 3

= 3.0 V

10%

Note 4

HALT mode

Low-voltage

mode

Note 6

HALT mode

Low-vol-

tage

mode

Note 6

= 5.0 V

10%

= 3.0 V

10%

Low-cur-
rent-drain
mode

Note 7

XT1 =
0 V

Note 8

STOP
mode

= 3.0 V

10%

= 3.0 V,

= -40 to +50

= 2.0 V

10%

= 3.0 V, T

= 25

= 3.0 V

10%

= 3.0 V,

= -40 to +50

= 3.0 V, T

= 25

= 5.0 V

10%

= 3.0 V

10%

= 3.0 V

10%

= 2.0 V

10%

= 3.0 V, T

= 25

= 3.0 V

10%

= 3.0 V, T

= 25

1.0
MHz

Note 2

RC
oscillation

R = 22 k

C = 22 pF

32.768
kHz

Note 5

crystal

oscillation

MIN.

TYP.

0.65

180

370

170

11.0

5.5

11.0

8.0

5.0

2.5

5.0

4.0

0.05

0.02

MAX.

1.6

360

920

340

40.0

18.0

24.0

14.0

30.0

12.0

10.0

15.0

8.0

7.0

5.0

2.5

0.2

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

AC CHARACTERISTICS (T

= -40 to +85

C, V

= 1.8 to 5.5 V)

CPU clock cycle

time

Note 1

(minimum

instruction execution time

= 1 machine cycle)

TI0 input frequency

TI0 input high/low level

width

Interrupt input high/low

level width

RESET low level width

RC oscillator frequency

IM02 = 0

IM02 = 1

Notes 1. When the main system clock is used, the

cycle time of the CPU clock (

) (minimum

instruction execution time) depends on the

time constants of connected resistors (R)

and capacitors (C) and the processor clock

control register (PCC).

When the subsystem clock is used, the cycle

time of the CPU clock (

) (minimum instruc-

tion execution time) depends on the fre-

quency of the connected resonator (and ex-

ternal clock), the system clock control regis-

ter (SCC), and the processor clock control

The figure on the right side shows the cycle

time t

characteristics for the supply voltage

during main system clock operation.

2. This value becomes 2t

or 128/f

accord-

ing to the setting of the interrupt mode reg-

ister (IM0).

TIH

TIL

INTH

INTL

RSL

Conditions

MIN.

TYP.

MAX.

Unit

Operated by main system clock pulse

2.0

128

Operated by subsystem clock pulse

114

122

125

= 2.7 to 5.5 V

MHz

275

kHz

= 2.7 to 5.5 V

0.48

1.8

INT0

Note 2

INT1, INT2, and INT4

KR0 to KR7

MHz

Parameter

Symbol

= 2.7 to 5.5 V

1.00

1.30

0.90

0.55

R = 22 k

C = 22 pF

1.8 2

5 5.5 6

0.5

128

vs. V

(Main system clock in operation)

Cycle time t

[ s]

Power supply voltage V

[V]

Operation guaranteed
range

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Unit

Parameter

SCK cycle time

SCK high/low level

width

Note 1

setup time

(referred to SCK

)

Note 1

hold time

(referred to SCK

)

Delay time from SCK

to SO

Note 1

output

SERIAL TRANSFER OPERATION

Two-wire and three-wire serial I/O modes (SCK: Internal clock output): (T

= -40 to +85

C, V

= 1.8 to 5.5 V)

Notes 1. In two-wire serial I/O mode, SO should be read as SB0 or SB1.

2. R

is the resistance of the SO output line load, while C

is the capacitance.

Two-wire and three-wire serial I/O modes (SCK: External clock input): (T

= -40 to +85

C, V

= 1.8 to 5.5 V)

Notes 1. In two-wire serial I/O mode, SO should be read as SB0 or SB1.

2. R

is the resistance of the SO output line load, while C

is the capacitance.

TYP.

MAX.

300

1,000

Unit

MIN.

800

3,200

400

1,600

100

150

400

600

Conditions

= 2.7 to 5.5 V

= 1 k

Note 2

= 2.7 to 5.5 V

= 100 pF

Symbol

KCY2

KL2

KH2

SIK2

KSI2

KSO2

Parameter

SCK cycle time

SCK high/low level

width

Note 1

setup time

(referred to SCK

)

Note 1

hold time

(referred to SCK

)

Delay time from SCK

to SO

Note 1

output

MIN.

1,300

3,800

KCY1

/2 - 50

KCY1

/2 - 150

150

500

400

600

Conditions

= 2.7 to 5.5 V

= 1 k

Note 2

= 2.7 to 5.5 V

= 100 pF

Symbol

KCY1

KL1

KH1

SIK1

KSI1

KSO1

TYP.

MAX.

250

1,000

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

SBI mode (SCK: Internal clock output (master)): (T

= -40 to +85

C, V

= 1.8 to 5.5 V)

Note

is the resistance of the SB0/SB1 output line load, while C

is the capacitance.

SBI mode (SCK: External clock input (slave)): (T

= -40 to +85

C, V

= 1.8 to 5.5 V)

Note

is the resistance of the SB0/SB1 output line load, while C

is the capacitance.

TYP.

MAX.

250

1,000

Unit

MIN.

1,300

3,800

KCY3

/2 - 50

KCY3

/2 - 150

150

500

KCY3

Conditions

= 2.7 to 5.5 V

= 1 k

Note

= 2.7 to 5.5 V

= 100 pF

Symbol

KCY3

KL3

KH3

SIK3

KSI3

KSO3

KSB

SBK

SBL

SBH

Parameter

SCK cycle time

SCK high/low level

width

SB0/SB1 setup time

(referred to SCK

)

SB0/SB1 hold time

(referred to SCK

)

Delay time from SCK

to SB0/SB1 output

From SCK

to SB0/SB1

From SB0/SB1

to SCK

SB0/SB1 low level width

SB0/SB1 high level

width

TYP.

MAX.

300

1,000

Unit

MIN.

800

3,200

400

1,600

100

150

KCY4

Conditions

= 2.7 to 5.5 V

= 1 k

Note

= 2.7 to 5.5 V

= 100 pF

Symbol

KCY4

KL4

KH4

SIK4

KSI4

KSO4

KSB

SBK

SBL

SBH

Parameter

SCK cycle time

SCK high/low level

width

SB0/SB1 setup time

(referred to SCK

)

SB0/SB1 hold time

(referred to SCK

)

Delay time from SCK

to SB0/SB1 output

From SCK

to SB0/SB1

From SB0/SB1

to SCK

SB0/SB1 low level width

SB0/SB1 high level

width

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Parameter

Symbol

Release signal setting time

Oscillation settling time

Note 1

SREL

WAIT

Release by RESET

Release by interrupt request

Conditions

DATA HOLD CHARACTERISTICS BY LOW SUPPLY VOLTAGE IN DATA MEMORY STOP MODE

= -40 to +85

Notes 1. CPU operation stop time for preventing unstable operation at the beginning of oscillation.

2. Select either 512/f

or no wait with the mask option.

Data hold timing (STOP mode release by RESET)

Data hold timing (standby release signal: STOP mode release by interrupt signal)

MIN.

TYP.

MAX.

Unit

56/f

Note 2

RESET

SREL

WAIT

Internal reset operation

HALT mode

Operation
mode

STOP instruction execution

Data hold mode

STOP mode

Standby release signal
(Interrupt request)

SREL

WAIT

HALT mode

Operation
mode

STOP instruction execution

Data hold mode

STOP mode

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

-60

0.5

1.0

Main system clock frequency f

(MHz)

2.0

-40

-20

+20

Operating ambient temperature T

(АC)

+40

+60

+80

+100

CL1

CL2

22 k

22 pF

(Sample A)

vs. T

(RC oscillation, R = 22 k

, C = 22 pF)

= 5.0 V

= 3.0 V

= 2.2 V

= 1.8 V

-60

0.5

1.0

Main system clock frequency f

(MHz)

2.0

-40

-20

+20

Operating ambient temperature T

(АC)

+40

+60

+80

+100

CL1

CL2

22 k

22 pF

(Sample B)

= 5.0 V

= 3.0 V

= 2.2 V

= 1.8 V

-60

0.5

1.0

Main system clock frequency f

(MHz)

2.0

-40

-20

+20

Operating ambient temperature T

(АC)

+40

+60

+80

+100

CL1

CL2

22 k

22 pF

(Sample C)

= 5.0 V

= 3.0 V

= 2.2 V

= 1.8 V

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

15. PACKAGE DRAWINGS

44 PIN PLASTIC QFP ( 10)

S44GB-80-3BS

ITEM

MILLIMETERS

INCHES

0.125

0.075

0.10

2.7

0.004

0.106

0.005

0.003

NOTE

Each lead centerline is located within 0.16 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.

13.2

0.2

0.520+0.008

0.009

10.0

0.2

0.394+0.008

0.009

10.0

0.2

0.394+0.008

0.009

13.2

0.2

0.520+0.008

0.009

1.0

0.37

1.0

0.039

0.015+0.003

0.004

0.8 (T.P.)

1.6

0.2

0.16

0.007

0.031 (T.P.)

0.063

0.008

0.8

0.2

0.031 +0.009

0.008

0.17

0.007 +0.002

0.003

3.0 MAX.

0.119 MAX.

+0.08

0.07

+0.06

0.05

detail of lead end

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

16. RECOMMENDED SOLDERING CONDITIONS

The

PD750104,

PD750106, and

PD750108 should be soldered and mounted under the conditions recom-

mended in the table below.

For detail of recommended soldering conditions, refer to the information document SMD Surface Mount

Technology Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact our sales personnel.

Table 16-1. Surface Mounting Type Soldering Conditions

PD750104GB-

ззз

-3BS-MTX

: 44-pin plastic QFP (10

10 mm, 0.8-mm pitch)

PD750106GB-

ззз

-3BS-MTX

: 44-pin plastic QFP (10

10 mm, 0.8-mm pitch)

PD750108GB-

ззз

-3BS-MTX

: 44-pin plastic QFP (10

10 mm, 0.8-mm pitch)

PD750104GB(A)-

ззз

-3BS-MTX : 44-pin plastic QFP (10

10 mm, 0.8-mm pitch)

PD750106GB(A)-

ззз

-3BS-MTX : 44-pin plastic QFP (10

10 mm, 0.8-mm pitch)

PD750108GB(A)-

ззз

-3BS-MTX : 44-pin plastic QFP (10

10 mm, 0.8-mm pitch)

Caution Use of more than one soldering method should be avoided (except for partial heating method).

Table 16-2. Insertion Type Soldering Conditions

PD750104CU-

ззз

: 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

PD750106CU-

ззз

: 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

PD750108CU-

ззз

: 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

PD750104CU(A)-

ззз

: 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

PD750106CU(A)-

ззз

: 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

PD750108CU(A)-

ззз

: 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

Package peak temperature: 235

Duration: 30 seconds max. (at 210

C or above)

Maximum allowable number of reflow processes: 3

Package peak temperature: 215

Duration: 40 seconds max. (at 200

C or above)

Maximum allowable number of reflow processes: 3

Solder bath temperature: 260

C max.

Duration: 10 seconds max.

Number of times: 1

Preliminary heat temperature: 120

C max. (package surface temperature)

Terminal temperature: 300

C max.

Duration: 3 seconds max. (per device side)

IR35-00-3

VP15-00-3

WS60-00-1

Infrared reflow

VPS

Wave

soldering

Partial heating

method

Soldering

method

Soldering conditions

Soldering method

Soldering conditions

Wave soldering (terminal only)

Partial heating method

Solder bath temperature: 260

C max., Duration: 10 seconds max.

Terminal temperature: 300

C max., Duration: 3 seconds max. (for each pin)

Caution Apply wave soldering to terminals only. See to it that the jet solder does not contact with the

chip directly.

Symbol

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

APPENDIX A FUNCTIONS OF THE

PD750008,

PD750108, AND

PD75P0116

Instruction

execution time

(1/2)

Item

PD750008

PD750108

PD75P0116

Program memory

Masked ROM

One-time PROM

0000H - 1FFFH

0000H - 3FFFH

(8,192

8 bits)

(16,384

8 bits)

Data memory

000H - 1FFH
(512

4 bits)

CPU

75XL CPU

General-purpose register

(4 bits

8 or 8 bits

4 banks

Main system clock oscillator

Crystal/ceramic

RC oscillator (with external resistor and

oscillator

capacitor)

Time required for start after reset

, 2

Fixed to 56/f

(selected using a mask
option)

Wait time applied when STOP

, 2

or no wait

Fixed to 2

mode is released by an interrupt

(selected accord-

(selected using a mask

ing to BTM setting)

option)

Subsystem clock oscillator

Crystal oscillator

When selecting the main

З 0.95, 1.91, 3.81, or 15.3 З 4, 8, 16, or 64

s (when operating at f

= 1.0 MHz)

system clock

s (when operating at

=4.19 MHz)

З 2, 4, 8, or 32

s (when operating at f

= 2.0 MHz)

З 0.67, 1.33, 2.67, or 10.7

s (when operating at

= 6.0 MHz)

When selecting the

122

s (when operating at 32.768 kHz)

subsystem clock

CMOS input

8 (Built-in pull-up resistors that can be connected by software: 7)

CMOS I/O

18 (Built-in pull-up resistors that can be connected by software)

N-ch open-drain I/O

8 (Pull-up resistors that can be incorporated by

8 (No mask option)

mask option)

Withstand voltage of

Withstand voltage of 13 V

13 V

Total

Timer

4 channels

З 8-bit timer counter: 1

З 8-bit timer counter (clock timer output function

З 8-bit timer/event

provided): 1

counter: 1

З 8-bit timer/event counter: 1

З Basic interval timer/

З Basic interval timer/watchdog timer: 1

watchdog timer: 1

З Clock timer: 1

I/O port

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

(2/2)

Item

PD750008

PD750108

PD75P0116

Serial interface

3 modes supported
З Three-wire serial I/O mode: First transferred bit switchable between
LSB and MSB
З Two-wire serial I/O mode
З SBI mode

Clock output (PCL)

, 524, 262, or 65.5 kHz З

, 125, 62.5, or 15.6 kHz (when the main system

(when the main system

clock operates at 1.0 MHz)

clock operates at 4.19
MHz)

, 750, 375, or 93.8 kHz З

, 250, 125, or 31.3 kHz (when the main system

(when the main system

clock operates at 2.0 MHz)

clock operates at 6.0
MHz)

Buzzer output (BUZ)

З 2, 4, or 32 kHz (when the З 2, 4, or 32 kHz (when the subsystem clock

main system clock

operates at 32.768 kHz)

operates at 4.19 MHz

З 0.488, 0.977, or 7.813 kHz (when the main

or the subsystem clock

system clock operates at 1.0 MHz)

operates at 32.768 kHz)

З 0.977, 1.953, or 15.625 kHz (when the main

З 2.93, 5.86, or 46.9 kHz

system clock operates at 2.0 MHz)

(when the main system
clock operates at 6.0
MHz)

Vectored interrupt

External: 3, internal: 4

Test input

External: 1, internal: 1

Supply voltage

= 2.2 to 5.5 V

= 1.8 to 5.5 V

Operating ambient temperature

= -40 to +85

Package

З 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
З 44-pin plastic QFP (10

10 mm, 0.8-mm pitch)

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

APPENDIX B DEVELOPMENT TOOLS

The following development tools are provided for the development of a system which employs the

PD750108.

In the 75XL series, use the common relocatable assembler together with a device file of each model.

Language processors

Note

These software products cannot use the task swap function, which is available in MS-DOS Ver. 5.00 or later.

Remark The operations of the assembler and device file are guaranteed only on the above host machines and

OSs.

MS-DOS

Ver. 3.30

Ver. 6.2

Note

See "OS for IBM PC."

MS-DOS

Ver. 3.30

Ver. 6.2

Note

See "OS for IBM PC."

Part number

S5A13DF750008

S5A10DF750008

S7B13DF750008

S7B10DF750008

Host machine

PC-9800 series

IBM PC/AT

and

compatibles

Host machine

PC-9800 series

IBM PC/AT

and

compatibles

Device file

RA75X relocatable assembler

Part number

S5A13RA75X

S5A10RA75X

S7B13RA75X

S7B10RA75X

Distribution media

3.5-inch 2HD

5.25-inch 2HD

3.5-inch 2HC

5.25-inch 2HC

Distribution media

3.5-inch 2HD

5.25-inch 2HD

3.5-inch 2HC

5.25-inch 2HC

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

PROM programming tools

Note

These software products cannot use the task swap function, which is available in MS-DOS Ver. 5.00 or

later.

Remark Operation of the PG-1500 controller is guaranteed only on the above host machines and OSs.

Hardware

Software

PG-1500

PA-75P008CU

PG-1500 controller

MS-DOS

Ver. 3.30

Ver. 6.2

Note

See "OS for IBM PC."

Host machine

PC-9800 series

IBM PC/AT and

compatibles

Distribution media

3.5-inch 2HD

5.25-inch 2HD

3.5-inch 2HD

5.25-inch 2HC

Part number

S5A13PG1500

S5A10PG1500

S7B13PG1500

S7B10PG1500

The PG-1500 PROM programmer is used together with an accessory board and optional

program adapter. It allows the user to program a single chip microcontroller containing

PROM from a standalone terminal or a host machine. The PG-1500 can be used to

program typical 256K-bit to 4M-bit PROMs.

The PA-75P008CU is a PROM programmer adapter provided for the

PD75P0116CU/GB.

It is used in conjunction with the PG-1500.

This program enables the host machine to control the PG-1500 through the serial and

parallel interfaces.

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Hardware

Part number

S5A13IE75X

S5A10IE75X

S7B13IE75X

S7B10IE75X

Distribution media

3.5-inch 2HD

5.25-inch 2HD

3.5-inch 2HC

5.25-inch 2HC

Debugging tools

The in-circuit emulators (IE-75000-R and IE-75001-R) are provided to debug programs used for the

PD750108.

The system configuration is shown below.

Notes 1. Maintenance service only

2. These software products cannot use the task swap function, which is available in MS DOS Ver. 5.00

or later.

Remarks 1. Operation of the IE control program is guaranteed only on the above host machines and OSs.

2. The

PD750104,

PD750106,

PD750108, and

PD75P0116 are collectively called the

PD750108

subseries.

MS-DOS

Ver. 3.30

Ver. 6.2

Note 2

See "OS for IBM PC."

The IE-75000-R is an in-circuit emulator used to debug hardware and software when

developing an application system using the 75X series and 75XL series. Use this

emulator together with optional emulation board IE-75300-R-EM and emulation probe

EP-75008CU-R or EP-75008GB-R to develop application systems of the

PD750108

subseries.

For efficient debugging, connect the emulator to the host machine and a PROM

programmer.

The IE-75000-R contains emulation board IE-75000-R-EM. The board is connected

to the IE-75000-R.

The IE-75001-R is an in-circuit emulator used to debug hardware and software when

developing an application system using the 75X series and 75XL series. Use this

emulator together with optional emulation board IE-75300-R-EM and emulation probe

EP-75008CU-R or EP-75008GB-R to develop application systems of the

PD750108

subseries.

For efficient debugging, connect the emulator to the host machine and a PROM

programmer.

The IE-75300-R-EM is an emulation board used to evaluate an application system

using the

PD750108 subseries.

Use this board together with the IE-75000-R or IE-75001-R.

The EP-75008CU-R is an emulation probe for the

PD750108CU.

Connect this emulation probe to the IE-75000-R or IE-75001-R, and the IE-75300-R-

EM.

The EP-75008GB-R is an emulation probe for the

PD750108GB.

Connect this emulation probe to the IE-75000-R or IE-75001-R, and the IE-75300-R-

EM.

A 44-pin conversion socket, the EV-9200G-44, supplied with this probe facilitates the

connection of the probe to the target system.

This program enables the host machine to control the IE-75000-R or IE-75001-R

through the RS-232-C and Centronics interface.

IE-75000-R

Note 1

IE-75001-R

IE-75300-R-EM

EP-75008CU-R

EP-75008GB-R

IE control program

Software

EV-9200G-44

Host machine

PC-9800 series

IBM PC/AT

and

compatibles

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Document number

Japanese

English

Document number

Japanese

English

Hardware

Software

IE-75000-R/IE-75001-R User's Manual

IE-75300-R-EM User's Manual

EP-75008CU-R User's Manual

EP-75008GB-R User's Manual

PG-1500 User's Manual

RA75X Assembler Package User's

Manual

PG-1500 Controller

User's Manual

PC-9800 series (MS-DOS) base

IBM PC series (PC DOS) base

Operation

Language

Document number

Japanese

English

C10535E

C11531E

C10983E

MEI-1202

IC Package Manual

Semiconductor Device Mounting Technology Manual

Quality Grade on NEC Semiconductor Devices

Reliability and Quality Control of NEC Semiconductor Devices

Electrostatic Discharge (ESD) Test

Semiconductor Device Quality Guarantee Guide

Microcontroller-Related Products Guide - by third parties

Document name

APPENDIX C RELATED DOCUMENTS

Some documents are preliminary editions, but they are not so specified in the tables below.

Documents related to devices

Documents related to development tools

Other related documents

Caution The above related documents are subject to change without notice. Be sure to use the latest

edition when you design your system.

U12301J

U12603J

U11330J

U11456J

U10453J

EEU-846

U11354J

EEU-699

EEU-698

U11940J

EEU-731

EEU-730

EEU-704

EEU-5008

EEU-1416

U11354E

EEU-1317

EEU-1305

EEU-1335

EEU-1346

EEU-1363

EEU-1291

U10540E

C10943X

C10535J

C11531J

C10983J

MEM-539

C11893J

U11416J

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) Data

Sheet

PD75P0116 Data Sheet

PD750108 User's Manual

PD750008, 750108 Instruction List

75XL Series Selection Guide

U12301E (This manual)

U12603E

U11330E

U10453E

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of

the gate oxide and ultimately degrade the device operation. Steps must be taken

to stop generation of static electricity as much as possible, and quickly dissipate

it once, when it has occurred. Environmental control must be adequate. When

it is dry, humidifier should be used. It is recommended to avoid using insulators

that easily build static electricity. Semiconductor devices must be stored and

transported in an anti-static container, static shielding bag or conductive

material. All test and measurement tools including work bench and floor should

be grounded. The operator should be grounded using wrist strap. Semiconduc-

tor devices must not be touched with bare hands. Similar precautions need to

be taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input level

may be generated due to noise, etc., hence causing malfunction. CMOS device

behave differently than Bipolar or NMOS devices. Input levels of CMOS devices

must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

or GND with a resistor, if it is considered to have

a possibility of being an output pin. All handling related to the unused pins must

be judged device by device and related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production

process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset function

have not yet been initialized. Hence, power-on does not guarantee out-pin

levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after

power-on for devices having reset function.

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290

NEC Electronics Italiana s.r.1.

Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951

NEC do Brasil S.A.

Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

З Device availability

З Ordering information

З Product release schedule

З Availability of related technical literature

З Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

З Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

J96. 8

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

MS-DOS is a registered trademark or trademark of Microsoft Corporation in the United States and/or other countries.

IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.

M4 96. 5

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

Part Number ТЕPD750106

Document Outline