Document Outline
- COVER
- FEATURES
- ORDERING INFORMATION
- PIN CONFIGURATION
- BLOCK DIAGRAM
- ABSOLUTE MAXIMUM RATINGS
- ELECTRICAL CHARACTERISTICS
- SWITCHING CHARACTERISTICS
- PIN FUNCTION
- REGISTER - ADDRESS CORRESPONDENCE TABLE
- LEAP YEAR CONTROL REGISTER (R/W)
- MODE REGISTER (R/W)
- CONTROL REGISTER
- TYPICAL INT CONTROL EXAMPLES (mode register: INT output mode)
- TP OUTPUT (mode register: TP output mode)
- BUSY SIGNAL
- OUTLINE DRAWING
- RECOMMENDED SOLDERING CONDITIONS
©
1995
PRELIMINARY DATA SHEET
The
µ
PD4992 is a CMOS integrated circuit which outputs 8-bit parallel time and calendar data in a system in which
a microprocessor is employed. The
µ
PD4992 operates at 32.768 kHz and provides year, month, day of month, day
of week, hour, minute, and second data to a system. The
µ
PD4992 internally contains a voltage regulator so that
low power consumption operation and high accuracy are realized even if the supply voltage varies. The
µ
PD4992
uses the 8-bit bus to facilitate interfacing with a microprocessor.
FEATURES:
·
Internal counter for time (hour, minute, second), and calendar (leap year, year, month, day of month, day of week)
·
Super low power consumption (I
DD
= 2
µ
A MAX. at V
DD
= 2.4 V)
·
Automatic determination of leap year, manual setting possible
·
12 hour/24 hour mode selectable
·
8-bit parallel input/output in BCD data format
·
12 kinds of interval timer output (can be used as watchdog timer)
·
Internal voltage detection circuit for automatic determination of battery run-down
·
High accuracy
ORDERING INFORMATION:
Order Code
Package
µ
PD4992CX
20-pin plastic DIP (300 mil)
µ
PD4992GS
20-pin plastic SOP (300 mil)
µ
PD4992GS-T1, T2
20-pin plastic SOP (300 mil)
Provided on adhesive tape
µ
PD4992GS-E2
20-pin plastic SOP (300 mil)
Provided on embossed carrier tape
µ
PD4992
MOS INTEGRATED CIRCUIT
8-Bit Parallel I/O Calendar Clock
The information in this document is subject to change without notice.
1992
Document No. ID-3084 (1st edition)
(O.D. No. ID-8222)
Date Published March 1997 P
Printed in Japan
µ
PD4992
2
PIN CONFIGURATION
BLOCK DIAGRAM
OSC
Data Bus
Controller
8
3
Address Bus
Controller
Time Counter
TP
TP Generator
Clock Stop
1 / 2
15
15 Stage Binary Divider
Mode Registor
Control Registor
Address
Decoder
CS
1
X
IN
X
OUT
RD
WR
D
0
to D
7
A
0
to A
2
CS
2
Second
Minute
Time
Day
Month
Year
Day of
the week
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
V
DD
X
IN
X
OUT
CS
2
D
7
D
6
D
5
D
4
D
3
D
2
V
SS
D
1
D
0
RD
A
2
A
1
A
0
WR
CS
1
TP
µ
PD4992
3
ABSOLUTE MAXIMUM RATINGS (V
SS
= 0 V)
Item
Symbol
Ratings
Unit
Supply voltage
V
DD
0.3 to 7.0
V
Input voltage range
V
IN
0.3 to V
DD
+ 0.3
V
Output pin withstand voltage
V
OUT
7.0
V
Low level output current
I
OUT
30
mA
(N ch Open Drain)
Operating temperature range
T
opt
40 to +85
°
C
Storage temperature range
T
stg
65 to +125
°
C
ELECTRICAL CHARACTERISTICS
(V
SS
= 0 V, f = 32.768 kHz, C
G
= C
D
= 20 pF, C
i
= 20k ohms, T
a
= 40 to +85
°
C)
Item
Symbol
Condition
MIN.
TYP.*
MAX.
Unit
Operating voltage range
V
DD
2.4
5.5
V
High level input voltage
V
IH
0.7 V
DD
V
DD
V
Low level input voltage
V
IL
V
SS
0.3 V
DD
V
Supply current
I
DD
V
DD
= 5.5 V, V
IN
= V
SS
2
6
µ
A
Supply current
I
DD
V
DD
= 2.4 V, V
IN
= V
SS
0.6
2
µ
A
Input leakage current
I
LI
V
DD
= 5.5 V, V
IN
= V
DD
or V
SS
±
1
×
10
5
±
1.0
µ
A
High level output voltage
V
OH
I
OH
= 1.0 mA
2.4
4.3
V
Low level output voltage
V
OL1
I
OL
= 2.0 mA
0.1
0.4
V
Low level output voltage
V
OL2
I
OL
= 1.0 mA (N ch Open Drain)
0.4
V
High level leakage current
I
LOH
TP
out
= V
DD
(N ch Open Drain)
4
×
10
5
1.0
µ
A
*: Ta = +25
°
C
SWITCHING CHARACTERISTICS
WRITE CYCLE (unless otherwise specified V
DD
= 5 V
±
10 %, T
a
= 40 to +85
°
C)
Item
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Cycle time
t
WC
150
CS-WR reset time
t
CW
120
Address - WR reset time
t
AW
120
Address - WR set up time
t
AS
0
Write pulse width
t
WP
90
ns
Address hold time
t
WR
20
Input data set up time
t
DW
50
Input data hold time
t
DH
0
WR - output floating time
t
WHZ
50
µ
PD4992
4
WRITE CYCLE TIMING WAVEFORMS 1
t
DW
t
DH
t
WR
t
WP
t
CW
t
AW
t
AS
t
OHZ
t
WC
ADDRESS
RD
CS
WR
D
IN
D
OUT
WRITE CYCLE TIMING WAVEFORMS 2 (RD = V
IL
)
t
WC
ADDRESS
t
DW
t
DH
t
WR
t
WP
t
AW
t
AS
t
WHZ
CS
WR
D
IN
D
OUT
t
OW
t
CW
µ
PD4992
5
READ CYCLE (unless otherwise specified V
DD
= 5 V
±
10 %, T
a
= 40 to +85
°
C)
Item
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Cycle time
t
RC
150
Address access time
t
AA
150
CS - access time
t
ACS
150
RD - output delay time
t
OE
75
RD - output delay time
t
OLZ
5
ns
RD - output delay time
t
OHZ
50
Output hold time
t
OH
15
CS - output set time
t
CLZ
10
CS - output floating time
t
CHZ
5
READ CYCLE TIMING WAVEFORMS 1
t
RC
ADDRESS
t
ACS
t
CLZ
RD
D
OUT
Data output
t
OHZ
t
CHZ
CS
t
RC
ADDRESS
t
AA
t
OE
CS
RD
D
OUT
t
OLZ
Data output
t
OH
READ CYCLE TIMING WAVEFORMS 2
µ
PD4992
6
PIN FUNCTION
Pin symbol
Pin name
Pin number
Function
CS
1
Chip select input
2
Internal register can be accessed when CS
1
= L
CS
2
Chip select input
17
and CS
2
= H
WR
Write signal input
3
Writes the contents of data bus to the register
selected by address input at the rising edge
RD
Read signal input
7
Outputs the contents of the register selected by
address input to the data bus at the rising edge
D
0
to D
7
Data input/output
8, 9, 11 to 16
Data input/output bus
A
0
to A
2
Address input
4 to 6
Address input to select internal register
TP
Timing pulse output
1
Interval signal and timing pulse output (N ch open
drain output)
X
IN
Crystal resonator connection pin
19
Crystal resonator and capacitor are connected to
X
OUT
Crystal resonator connection pin
18
these pins.
V
DD
Power supply pin
20
2.4 V to 5.5 V
V
SS
GND
10
Connect to GND
External components (crystal resonator, capacitors) must be located as close as the IC, and separated as far as
from high speed clock wiring.
X
V
DD
X
IN
X
OUT
C
2
C
1
X: 32.768 kHz
C
1
, C
2
: 10 to 30 pF
5 V or 0 V
µ
PD4992
7
REGISTER ADDRESS CORRESPONDENCE TABLE
ADDRESS
Register contents
HEX
BIN
b7
b6
b5
b4
b3
b2
b1
b0
0H
000B
10s second digit
1s second digit
1H
001B
10s minute digit
1s minute digit
2H
010B
12/24H
AM/PM
10s hour digit
1s hour digit
3H
011B
Leap year control
Leap year counter
Day of week digit
4H
100B
10s day digit
1s day of month digit
5H
101B
10s month digit
1s month digit
6H
110B
10s year digit
1s year digit
7H
111B
Mode register
Control register
AM/PM flag (R/W) : In 12 hour mode, 0 indicates AM, and 1 indicates PM.
Always 0 in 24 hour mode.
12/24H flag (R/W) : 0 indicates 24 hour mode, and 1 indicates 12 hour mode.
LEAP YEAR CONTROL REGISTER (R/W)
b7
b6
Mode
0
0
Leap year effective
Writing to leap year counter disabled
0
1
Leap year effective
Writing to leap year counter enabled
1
0
Leap year invalid
Writing to leap year counter disabled
1
1
Leap year invalid
Writing to leap year counter enabled
·
When the leap year control register is "0X" and the leap year counter is "00"
Leap year (Feb. has 29 days).
·
To disable leap year mode, write "10" to the leap year control register (Feb. 28 is followed by Mar. 1).
µ
PD4992
8
MODE REGISTER (R/W)
HEX
BIN
Mode
0H
0000B
Outputs TP2048 Hz
1H
0001B
Outputs TP1024 Hz
2H
0010B
Outputs TP256 Hz
3H
0011B
Outputs TP64 Hz
4H
0100B
Outputs INT1/2048s
5H
0101B
Outputs INT1/1024s
6H
0110B
Outputs INT1/256s
7H
0111B
Outputs INT1/64s
8H
1000B
Outputs INT1s
9H
1001B
Outputs INT10s
AH
1010B
Outputs INT60s
BH
1011B
Outputs BUSY signal
CH
1100B
Test mode 1
DH
1101B
Test mode 2
EH
1110B
Test mode 3
FH
1111B
Test mode 4
CONTROL REGISTER
Access mode
b3
b2
b1
b0
CLK adjust
Reset
CLK stop
0
0: NOP
0: NOP
0: CLK start
When writing
1: CLK adjust
1: Reset
1: CLK stop
TP enable
*1
INT reset
INT stop
1
0: TP = ENABLE
0: NOP
0: INT start
1: TP = DISABLE
1: Reset
1: INT stop
*
TP flag
OSC flag
*2
BUSY flag
*3
When reading
(Don't care)
0: TP = Z
0: No oscillation
0: OFF
1: TP = L
1: Oscillation
1: ON
*1 : When TP enable is 1 (TP = DISABLE), the TP pin becomes high impedance (actually a high level because
a pull up resistor is connected to the TP pin).
But TP flag is not DISABLE in this case.
*2 : If the OSC flag becomes 0 by oscillation stop, the OSC flag remains to be 0 when oscillation is resumed.
To set OSC flag to 1 again, execute CLK reset (if the OSC flag still remains to be 0, oscillation has not been
started again).
Upon initial power application of the
µ
PD4992, 0 is set to the OSC flag.
*3 : The BUSY flag is "1" when the time counter of the
µ
PD4992 is operating (when read is disabled).
µ
PD4992
9
Table 1 Time Counter Data
TIME COUNTER
DATA
TIME COUNTER
DATA
1s second digit
0-9
1s day of month digit
0-9
10s seocnd digit
0-5
10s day of month digit
0-3
1s minute digit
0-9
1s month digit
0-9
10s minute digit
0-5
10s month digit
0-1
1s hour digit
0-9
1s year digit
0-9
10s hour digit
0-5
10s year digit
0-9
Day of week digit
0-6
Table 2 Hour Counter Data
Hour
24 hour mode
12 hour mode
Hour
24 hour mode
12 hour mode
AM 1 o'clock
01H
81H
PM 1 o'clock
13H
C1H
AM 2 o'clock
02H
82H
PM 2 o'clock
14H
C2H
AM 3 o'clock
03H
83H
PM 3 o'clock
15H
C3H
AM 4 o'clock
04H
84H
PM 4 o'clock
16H
C4H
AM 5 o'clock
05H
85H
PM 5 o'clock
17H
C5H
AM 6 o'clock
06H
86H
PM 6 o'clock
18H
C6H
AM 7 o'clock
07H
87H
PM 7 o'clock
19H
C7H
AM 8 o'clock
08H
88H
PM 8 o'clock
20H
C8H
AM 9 o'clock
09H
89H
PM 9 o'clock
21H
C9H
AM 10 o'clock
10H
90H
PM 10 o'clock
22H
D0H
AM 11 o'clock
11H
91H
PM 11 o'clock
23H
D1H
PM 12 o'clock
12H
D2H
AM 12 o'clock
00H
92H
µ
PD4992
10
TYPICAL INT CONTROL EXAMPLES (mode register: INT output mode)
(1) Use of INT reset (example 1)
INT
output
Clear
INT stop
INT
stop
T
30.5 s
µ
(4) Use of INT stop (example 2)
t
2
t
1
T = t
1
+ t
2
Clear
INT stop
INT
stop
INT
output
(3) Use of INT stop (example 1)
INT reset
INT reset
T
T
INT
output
(2) Use of INT reset (example 2)
T
T
30.5 s
INT reset
µ
µ
PD4992
11
(5) Use of INT reset, INT stop
T
INT
output
INT
reset
Clear
INT stop
INT
stop
t
1
(6) Use of TP enable
TP
DISABLE
T
INT
output
T
TP
ENABLE
µ
PD4992
12
TP OUTPUT (mode register: TP output mode)
BUSY SIGNAL
TP output
DISABLE set
1s carry over
Internal counter
1 Hz
457.7 s
BUSY flag
ON
BUSY flag
OFF
BUSY flag
ON
Busy
signal output
1s carry over
µ
µ
30.5 s
The time and calendar data read out when BUSY signal is being output may not be correct. This is because, the
internal time counter is operating. Therefore, accessing must be disabled during this period or the data must be read
out twice and checked by the software. (Reading data during BUSY period has not effect on the contents of the internal
counter.)
1 / f
50 % duty continuous output
µ
PD4992
13
OUTLINE DRAWING
20PIN PLASTIC DIP (300 mil)
ITEM MILLIMETERS
INCHES
NOTES
1) Each lead centerline is located within 0.25 mm (0.01 inch) of
its true position (T.P.) at maximum material condition.
P20C-100-300A,C-1
N
0.25
0.01
R
0~15
°
0~15
°
A
25.40 MAX.
1.000 MAX.
B
1.27 MAX.
0.050 MAX.
F
1.1 MIN.
0.043 MIN.
G
3.5±0.3
0.138±0.012
J
5.08 MAX.
0.200 MAX.
K
7.62 (T.P.)
0.300 (T.P.)
C
2.54 (T.P.)
0.100 (T.P.)
D
0.50±0.10
0.020 +0.004
0.005
H
0.51 MIN.
0.020 MIN.
I
4.31 MAX.
0.170 MAX.
L
6.4
0.252
M
0.25
0.010 +0.004
0.003
+0.10
0.05
2) ltem "K" to center of leads when formed parallel.
M
R
M
I
H
G
F
D
N
C
B
K
P
0.9 MIN.
0.035 MIN.
1
10
20
11
P
L
A
J
µ
PD4992
14
20 PIN PLASTIC SOP (300 mil)
ITEM MILLIMETERS
INCHES
A
B
C
E
F
G
H
I
J
13.00 MAX.
1.27 (T.P.)
1.8 MAX.
1.55
7.7±0.3
0.78 MAX.
0.12
1.1
5.6
M
0.1±0.1
N
0.512 MAX.
0.031 MAX.
0.004±0.004
0.071 MAX.
0.061
0.303±0.012
0.220
0.043
0.005
0.050 (T.P.)
P20GM-50-300B, C-4
P
3
°
3
°
+7
°
NOTE
Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
D
0.40
0.016
+0.10
0.05
K
0.20
0.008
+0.10
0.05
L
0.6±0.2
0.024
0.10
3
°
+7
°
3
°
0.004
+0.008
0.009
+0.004
0.002
+0.004
0.003
A
C
D
G
P
detail of lead end
F
E
B
H
I
L
K
M
J
N
M
1
10
11
20
µ
PD4992
15
RECOMMENDED SOLDERING CONDITIONS
The following conditions (see table below) must be met when soldering this product.
Please consult with our sales offices in case other soldering process is used, or in case soldering is done under
different conditions.
TYPES OF SURFACE MOUNT DEVICE
µ
PD4992GS
Soldering process
Soldering condition
Symbol
Peak package's surface temperature: 235
°
C or below,
Infrared ray reflow
Reflow time: 30 seconds or below (210
°
C or higher),
IR35-00-2
Number of reflow process: 2,
Exposure limit*: None
Peak package's surface temperature: 215
°
C or below,
VPS
Reflow time: 40 seconds or below (200
°
C or higher),
VP15-00-2
Number of reflow process: 2,
Exposure limit*: None
Solder temperature: 260
°
C or below,
Wave soldering
Flow time: 10 seconds or below,
WS60-00-1
Number of flow process: 1,
Exposure limit*: None
Terminal temperature: 300
°
C or below,
Partial heating method
Flow time: 10 seconds or below,
Exposure limit*: None
*:
Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25
°
C and relative humidity at 65 % or less.
Note:
Do not apply more than a single process at once, except for "Partial heating method".
TYPE OF THROUGH HOLE MOUNT DEVICE
µ
PD4992CX
Soldering process
Soldering conditions
Wave soldering
Solder temperature: 260
°
C or below,
Flow time: 10 seconds or below.
µ
PD4992
16
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special:
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific:
Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
[MEMO]
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