(TOP VIEW)
positive logic: Low input to clear resets Q low and
positive logic:
Q high regardless of dc levels at A
positive logic:
or B inputs.
14
13
12
11
10
9
1
2
3
4
5
6
7
16
15
8
VCC
1A
1 Rext/
Cext
1
Cext 1Q
2Q
2B
2
CLR
2A
1B
1
CLR
1Q
2Q
2
Cext
2 Rext/
Cext
GND
Q
Q
CLR
Q
Q
CLR
+
VCC
Rext
R/C
Cext
*See operational notes -- Pulse Trigger Modes
5-380
FAST AND LS TTL DATA
DUAL MONOSTABLE
MULTIVIBRATORS
WITH SCHMITT-TRIGGER INPUTS
Each multivibrator of the LS221 features a negative-transition-triggered
input and a positive-transition-triggered input either of which can be used as
an inhibit input.
Pulse triggering occurs at a voltage level and is not related to the transition
time of the input pulse. Schmitt-trigger input circuitry for B input allows
jitter-free triggering for inputs as slow as 1 volt/ second, providing the circuit
with excellent noise immunity. A high immunity to VCC noise is also provided
by internal latching circuitry.
Once triggered, the outputs are independent of further transitions of the
inputs and are a function of the timing components. The output pulses can be
terminated by the overriding clear. Input pulse width may be of any duration
relative to the output pulse width. Output pulse width may be varied from 35
nanoseconds to a maximum of 70 s by choosing appropriate timing
components. With Rext = 2.0 k
and Cext = 0, a typical output pulse of 30
nanoseconds is achieved. Output rise and fall times are independent of pulse
length.
Pulse width stability is achieved through internal compensation and is
virtually independent of VCC and temperature. In most applications, pulse
stability will only be limited by the accuracy of external timing components.
Jitter-free operation is maintained over the full temperature and VCC ranges
for greater than six decades of timing capacitance (10 pF to 10
µ
F), and
greater than one decade of timing resistance (2.0 to 70 k
for the
SN54LS221, and 2.0 to 100 k
for the SN74LS221). Pulse width is defined
by the relationship: tw(out) = CextRext ln 2.0
0.7 Cext Rext; where tW is in ns
if Cext is in pF and Rext is in k
. If pulse cutoff is not critical, capacitance up
to 1000
µ
F and resistance as low as 1.4 k
may be used. The range of
jitter-free pulse widths is extended if VCC is 5.0 V and 25
°
C temperature.
·
SN54LS221 and SN74LS221 is a Dual Highly Stable One-Shot
·
Overriding Clear Terminates Output Pulse
·
Pin Out is Identical to SN54 / 74LS123
FUNCTION TABLE
(EACH MONOSTABLE)
INPUTS
OUTPUTS
CLEAR
A
B
Q
Q
L
X
X
L
H
X
H
X
L
H
X
X
L
L
H
H
L
°
H
±
H
*
°
L
H
TYPE
TYPICAL
POWER
MAXIMUM
OUTPUT PULSE
DISSIPATION
LENGTH
SN54LS221
23 mW
49 s
SN74LS221
23 mW
70 s
SN54/74LS221
DUAL MONOSTABLE
MULTIVIBRATORS
WITH SCHMITT-TRIGGER INPUTS
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN
Plastic
SN74LSXXXD
SOIC
16
1
D SUFFIX
SOIC
CASE 751B-03
5-381
FAST AND LS TTL DATA
SN54/74LS221
OPERATIONAL NOTES
Once in the pulse trigger mode, the output pulse width is
determined by tW = RextCextIn2, as long as Rext and Cext are
within their minimum and maximum valves and the duty cycle
is less than 50%. This pulse width is essentially independent
of VCC and temperature variations. Output pulse widths varies
typically no more than
±
0.5% from device to device.
tW
T
If the duty cycle, defined as being 100
·
where T is the
input
period of the input pulse, rises above 50%, the output pulse
width will become shorter. If the duty cycle varies between
low and high valves, this causes the output pulse width to
vary in length, or jitter. To reduce jitter to a minimum, Rext
should be as large as possible. (Jitter is independent of Cext).
With Rext = 100K, jitter is not appreciable until the duty cycle
approaches 90%.
Although the LS221 is pin-for-pin compatible with the
LS123, it should be remembered that they are not functionally
identical. The LS123 is retriggerable so that the output is
dependent upon the input transitions once it is high. This is not
the case for the LS221. Also note that it is recommended to
externally ground the LS123 Cext pin. However, this cannot be
done on the LS221.
The SN54LS/74LS221 is a dual, monolithic, non-retrigger-
able, high-stability one shot. The output pulse width, tW can be
varied over 9 decades of timing by proper selection of the
external timing components, Rext and Cext.
Pulse triggering occurs at a voltage level and is, therefore,
independent of the input slew rate. Although all three inputs
have this Schmitt-trigger effect, only the B input should be
used for very long transition triggers (
1.0
µ
V/s). High
immunity to VCC noise (typically 1.5 V) is achieved by internal
latching circuitry. However, standard VCC bypassing is
strongly recommended.
The LS221 has four basic modes of operation.
Clear Mode:
If the clear input is held low, irregardless of
the previous output state and other input
states, the Q output is low.
Inhibit Mode:
If either the A input is high or the B input is
low, once the Q output goes low, it cannot be
retriggered by other inputs.
Pulse Trigger
Mode:
A transition of the A or B inputs as indicated
in the functional truth table will trigger the Q
output to go high for a duration determined
by the tW equation described above; Q will
go low for a corresponding length of time.
The Clear input may also be used to trigger
an output pulse, but special logic precondi-
tioning on the A or B inputs must be done as
follows:
Following any output triggering action
using the A or B inputs, the A input must
be set high OR the B input must be set
low to allow Clear to be used as a trigger.
Inputs should then be set up per the truth
table (without triggering the output) to
allow Clear to be used a trigger for the
output pulse.
If the Clear pin is routinely being used to
trigger the output pulse, the A or B inputs
must be toggled as described above
before and between each Clear trigger
event.
Once triggered, as long as the output
remains high, all input transitions (except
overriding Clear) are ignored.
Overriding
Clear Mode:
If the Q output is high, it may be forced low
by bringing the clear input low.
5-382
FAST AND LS TTL DATA
SN54/74LS221
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
55
0
25
25
125
70
°
C
IOH
Output Current -- High
54, 74
0.4
mA
IOL
Output Current -- Low
54
74
4.0
8.0
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VT+
Positive-Going Threshold
Voltage at C Input
1.0
2.0
V
VCC = MIN
VT
Negative-Going Threshold
Voltage at C Input
54
0.7
0.8
V
VCC = MIN
VT
Negative-Going Threshold
Voltage at C Input
74
0.7
0.8
V
VCC = MIN
VT+
Positive-Going Threshold
Voltage at B Input
1.0
2.0
V
VCC = MIN
VT
Negative-Going Threshold
Voltage at B Input
54
0.7
0.9
V
VCC = MIN
VT
Negative-Going Threshold
Voltage at B Input
74
0.8
0.9
V
VCC = MIN
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
A Input
VIL
Input LOW Voltage
54
0.7
V
Guaranteed Input LOW Voltage for
A Input
VIL
Input LOW Voltage
74
0.8
V
Guaranteed Input LOW Voltage for
A Input
VIK
Input Clamp Voltage
1.5
V
VCC = MIN, IIN = 18 mA
VOH
Output HIGH Voltage
54
2.5
3.4
V
VCC = MIN, IOH = MAX
VOH
Output HIGH Voltage
74
2.7
3.4
V
VCC = MIN, IOH = MAX
VOL
Output LOW Voltage
54
0.25
0.4
V
IOL = 4.0 mA
VCC = MIN
VOL
Output LOW Voltage
74
0.35
0.5
V
IOL = 8.0 mA
VCC = MIN
IIH
Input HIGH Current
20
µ
A
VCC = MAX, VIN = 2.7 V
IIH
Input HIGH Current
0.1
mA
VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
Input A
Input B
Clear
0.4
0.8
0.8
mA
VCC = MAX, VIN = 0.4 V
IOS
Short Circuit Current (Note 1)
20
100
mA
VCC = MAX
ICC
Power Supply Current
Quiescent
4.7
11
mA
VCC = MAX
ICC
Triggered
19
27
mA
VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
5-383
FAST AND LS TTL DATA
SN54/74LS221
AC CHARACTERISTICS
(VCC = 5.0 V, TA = 25
°
C)
Symbol
From
(Input)
To
(Output)
Limits
Unit
Test Conditions
Symbol
From
(Input)
To
(Output)
Min
Typ
Max
Unit
Test Conditions
tPLH
A
Q
45
70
ns
CL = 15 pF,
See Figure 1
Cext = 80 pF, Rext = 2.0
tPLH
B
Q
35
55
ns
CL = 15 pF,
See Figure 1
Cext = 80 pF, Rext = 2.0
tPHL
A
Q
50
80
ns
CL = 15 pF,
See Figure 1
Cext = 80 pF, Rext = 2.0
tPHL
B
Q
40
65
ns
CL = 15 pF,
See Figure 1
Cext = 80 pF, Rext = 2.0
tPHL
Clear
Q
35
55
ns
CL = 15 pF,
See Figure 1
tPLH
Clear
Q
44
65
ns
CL = 15 pF,
See Figure 1
tW(out)
A or B
Q or Q
70
120
150
ns
Cext = 80 pF, Rext = 2.0
tW(out)
A or B
Q or Q
20
47
70
ns
Cext = 0, Rext = 2.0 k
tW(out)
A or B
Q or Q
600
670
750
Cext = 100 pF, Rext = 10 k
6.0
6.9
7.5
ms
Cext = 1.0
µ
F, Rext = 10 k
AC SETUP REQUIREMENTS
(VCC = 5.0 V, TA = 25
°
C)
Symbol
Parameter
Limits
Unit
Symbol
Parameter
Min
Typ
Max
Unit
dv/dt
Rate of Rise or Fall of Input Pulse
dv/dt
Schmitt, B
1.0
V/s
dv/dt
Logic Input, A
1.0
V/
µ
s
tW
Input Pulse Width
tW
A or B, tW(in)
40
ns
tW
Clear, tW (clear)
40
ts
Clear-Inactive-State Setup Time
15
ns
Rext
External Timing Resistance
54
1.4
70
k
Rext
External Timing Resistance
74
1.4
100
k
Cext
External Timing Capacitance
0
1000
µ
F
Output Duty Cycle
RT = 2.0 k
50
%
RT = MAX Rext
90
5-384
FAST AND LS TTL DATA
SN54/74LS221
AC WAVEFORMS
B INPUT
CLEAR
Q OUTPUT
Q OUTPUT
A INPUT IS LOW.
B INPUT
CLEAR
Q OUTPUT
A INPUT IS LOW.
B INPUT
CLEAR
Q OUTPUT
A INPUT IS LOW.
tW(in)
60 ns
tPLH
tPHL
tPLH
tPHL
1.3 V
3 V
0 V
3 V
0 V
VOH
VOL
VOH
VOL
60 ns
1.3 V
1.3 V
3 V
0 V
3 V
0 V
VOH
VOL
50 ns
0
ts
3 V
0 V
3 V
0 V
VOH
VOL
3 V
0 V
3 V
0 V
VOH
VOL
TRIGGERED
NOT TRIGGERED
50 ns
50 ns
B INPUT
CLEAR
Q OUTPUT
A INPUT IS LOW.
tW(out)
TRIGGER FROM B, THEN CLEAR -- CONDITION 1
TRIGGER FROM B, THEN CLEAR -- CONDITION 2
CLEAR OVERRIDING B, THEN TRIGGER FROM B
TRIGGERING FROM POSITIVE TRANSITION OF CLEAR
Figure 1
5-385
FAST AND LS TTL DATA
MIN
MIN
MAX
MAX
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
J
K
M
P
R
9.80
3.80
1.35
0.35
0.40
0.19
0.10
0
°
5.80
0.25
10.00
4.00
1.75
0.49
1.25
0.25
0.25
7
°
6.20
0.50
0.386
0.150
0.054
0.014
0.016
0.008
0.004
0
°
0.229
0.010
0.393
0.157
0.068
0.019
0.049
0.009
0.009
7
°
0.244
0.019
1.27 BSC
0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. 751B 01 IS OBSOLETE, NEW STANDARD
751B 03.
1
8
9
16
-A-
-B-
P
16 PL
D
-T-
K
C
G
M
R X 45
°
F
J
8 PL
SEATING
PLANE
Case 751B-03 D Suffix
16-Pin Plastic
SO-16
B
0.25 (0.010)
M
M
T
0.25 (0.010)
B
A
M
S
S
Case 648-08 N Suffix
16-Pin Plastic
MIN
MIN
MAX
MAX
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
H
J
K
L
M
S
18.80
6.35
3.69
0.39
1.02
0.21
2.80
7.50
0
°
0.51
19.55
6.85
4.44
0.53
1.77
0.38
3.30
7.74
10
°
1.01
0.740
0.250
0.145
0.015
0.040
0.008
0.110
0.295
0
°
0.020
0.770
0.270
0.175
0.021
0.070
0.015
0.130
0.305
10
°
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L" TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B" DOES NOT INCLUDE MOLD
FLASH.
5. ROUNDED CORNERS OPTIONAL.
6. 648 01 THRU 07 OBSOLETE, NEW STANDARD
648 08.
2.54 BSC
1.27 BSC
0.100 BSC
0.050 BSC
-A-
B
1
8
9
16
F
H
G
D
16 PL
S
C
-T-
SEATING
PLANE
K
J
M
L
T A
0.25 (0.010)
M
M
Case 620-09 J Suffix
16-Pin Ceramic Dual In-Line
MIN
MIN
MAX
MAX
MILLIMETERS
INCHES
DIM
19.05
6.10
0.39
1.40
0.23
0
°
0.39
19.55
7.36
4.19
0.53
1.77
0.27
5.08
15
°
0.88
0.750
0.240
0.015
0.055
0.009
0
°
0.015
0.770
0.290
0.165
0.021
0.070
0.011
0.200
15
°
0.035
1.27 BSC
2.54 BSC
7.62 BSC
0.050 BSC
0.100 BSC
0.300 BSC
A
B
C
D
E
F
G
J
K
L
M
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
5. 620 01 THRU 08 OBSOLETE, NEW STANDARD
620 09.
-B-
-A-
16 PL
-T-
C
D
E
F
G
J
K
M
N
SEATING
PLANE
16 PL
L
16
9
1
8
0.25 (0.010)
T A
M
S
0.25 (0.010)
T B
M
S
5-386
FAST AND LS TTL DATA
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