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Part Number SN54/74LS398

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5-557
FAST AND LS TTL DATA
QUAD 2-PORT REGISTER
The SN54 / 74LS398 and SN54 / 74LS399 are Quad 2-Port Registers. They
are the logical equivalent of a quad 2-input multiplexer followed by a quad 4-bit
edge-triggered register. A Common Select input selects between two 4-bit in-
put ports (data sources). The selected data is transferred to the output register
on the LOW-to-HIGH transition of the Clock input. The SN54/ 74LS398 fea-
tures both Q and Q inputs, while the SN54 / 74LS399 has only Q outputs.
·
Select From Two Data Sources
·
Fully Positive Edge-Triggered Operation
·
Both True and Complemented Outputs on SN54/ 74LS398
·
Input Clamp Diodes Limit High-Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
18
17
16
15
14
13
1
2
3
4
5
6
7
20
19
8
VCC
S
Qd Qd Iod I1d
I0c
I1c
Qc
Qa Qa I0a I1a I1b I0b Qb
9
10
Qb GND
12
11
Qc CP
VCC = PIN 20
GND = PIN 10
SN54 / 74LS398
14
13
12
11
10
9
1
2
3
4
5
6
7
16
15
8
VCC
S
Qd
I0d
I1d
I1c
Qc
I0c
CP
Qa
I0a
I1a
I1b I0b
Qb GND
VCC = PIN 16
GND = PIN 8
SN54 / 74LS399
PIN NAMES
LOADING (Note a)
HIGH
LOW
S
Common Select Input
0.5 U.L.
0.25 U.L.
CP
Clock (Active HIGH Going Edge) Input
0.5 U.L.
0.25 U.L.
I0a ­ I0d Data Inputs From Source 0
0.5 U.L.
0.25 U.L.
I1a ­ I0d Data Inputs From Source 1
0.5 U.L.
0.25 U.L.
Qa ­ Qd
Register True Outputs (Note b)
10 U.L.
5 (2.5) U.L.
Qa ­ Qd
Register Complementary Outputs
(Note b)
10 U.L.
5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
µ
A HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial
(74) Temperature Ranges.
SN54/74LS398
SN54/74LS399
QUAD 2-PORT REGISTER
LOW POWER SCHOTTKY
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN
Plastic
SN74LSXXXDW SOIC
SN74LSXXXD
SOIC
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
16
1
D SUFFIX
SOIC
CASE 751B-03
20
1
J SUFFIX
CERAMIC
CASE 732-03
20
1
N SUFFIX
PLASTIC
CASE 738-03
20
1
DW SUFFIX
SOIC
CASE 751D-03
5-558
FAST AND LS TTL DATA
SN54/74LS398
·
SN54/74LS399
FUNCTIONAL BLOCK DIAGRAM
IOA
S
IIA
IOB
IIB
IOC
IIC
IOD
IID
S
S
S
S
R
R
R
R
QA
QA
QB
QB
QC
QC
QD
QD
*
*
*
*
* SN54 / 74LS398 only
FUNCTIONAL DESCRIPTION
The SN54 / 74LS398 and SN54 / 74LS399 are high-speed
Quad 2-Port Registers. They select four bits of data from two
sources (Ports) under the control of a common Select Input
(S). The selected data is transferred to a 4-Bit Output Register
synchronous with the LOW-to-HIGH transition of the Clock in-
put (CP). The 4-Bit RS type output register is fully edge-trig-
gered. The Data inputs (I) and Select inputs (S) must be stable
only a setup time prior to and hold time after the LOW-to-HIGH
transition of the Clock input for predictable operation. The
SN54 / 74LS398 has both Q and Q Outputs available.
FUNCTION TABLE
INPUTS
OUTPUTS
S
I0
I1
Q
Q*
I
I
X
L
H
I
h
X
H
L
h
X
I
L
H
h
X
h
H
L
*SN54 / 74LS398 only
I = LOW Voltage Level one setup time pior to the LOW-to-HIGH clock transition
h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition
L = LOW Voltage Level
H = HIGH Voltage Level
X = Immaterial
5-559
FAST AND LS TTL DATA
SN54/74LS398
·
SN54/74LS399
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
­ 55
0
25
25
125
70
°
C
IOH
Output Current -- High
54, 74
­ 0.4
mA
IOL
Output Current -- Low
54
74
4.0
8.0
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54
0.7
V
Guaranteed Input LOW Voltage for
All Inputs
VIL
Input LOW Voltage
74
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK
Input Clamp Diode Voltage
­ 0.65
­ 1.5
V
VCC = MIN, IIN = ­ 18 mA
VOH
Output HIGH Voltage
54
2.5
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOH
Output HIGH Voltage
74
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL
Output LOW Voltage
54, 74
0.25
0.4
V
IOL = 4.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VOL
Output LOW Voltage
74
0.35
0.5
V
IOL = 8.0 mA
VIN = VIL or VIH
per Truth Table
IIH
Input HIGH Current
20
µ
A
VCC = MAX, VIN = 2.7 V
IIH
Input HIGH Current
0.1
mA
VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
­ 0.4
mA
VCC = MAX, VIN = 0.4 V
IOS
Short Circuit Current (Note 1)
­ 20
­ 100
mA
VCC = MAX
ICC
Power Supply Current
13
mA
VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25
°
C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
tPLH
tPHL
Propagation Delay,
Clock to Output Q
18
21
27
32
ns
VCC = 5.0 V
CL = 15 pF
5-560
FAST AND LS TTL DATA
SN54/74LS398
·
SN54/74LS399
AC SETUP REQUIREMENTS
(TA = 25
°
C)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
tW
Clock Pulse Width
20
ns
VCC = 5.0 V
ts
Data Setup Time
25
ns
VCC = 5.0 V
ts
Select Setup Time
45
ns
VCC = 5.0 V
th
Hold Time, Any Input
0
ns
DEFINITIONS OF TERMS
SETUP TIME(ts) -- is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW-to-HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME(th) -- is defined as the minimum time following
the clock transition from LOW-to-HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative Hold Time indicates that the correct
logic level may be released prior to the clock transition from
LOW-to-HIGH and still be recognized.
1.3 V
1.3 V
AC WAVEFORMS
Figure 1
Figure 2
Figure 3
*The shaded areas indicate when the input is permitted to change for predictable output performance.
I0 I1 *
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
Q
Q
CP
CP
CP
Q or Q
Q = I0
Q = I1
ts(L)
th(L)
tPHL
tPLH
th(H)
ts(L)
ts(H)
th(L) = 0
th(H) = 0
tPHL
tPLH
tPLH
Q
tPHL
tW(H)
ts(H)
tW(L)
S*
5-561
FAST AND LS TTL DATA
MIN
MIN
MAX
MAX
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
J
K
M
P
R
9.80
3.80
1.35
0.35
0.40
0.19
0.10
0
°
5.80
0.25
10.00
4.00
1.75
0.49
1.25
0.25
0.25
7
°
6.20
0.50
0.386
0.150
0.054
0.014
0.016
0.008
0.004
0
°
0.229
0.010
0.393
0.157
0.068
0.019
0.049
0.009
0.009
7
°
0.244
0.019
1.27 BSC
0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. 751B 01 IS OBSOLETE, NEW STANDARD
751B 03.
1
8
9
16
-A-
-B-
P
16 PL
D
-T-
K
C
G
M
R X 45
°
F
J
8 PL
SEATING
PLANE
Case 751B-03 D Suffix
16-Pin Plastic
SO-16
B
0.25 (0.010)
M
M
T
0.25 (0.010)
B
A
M
S
S
Case 648-08 N Suffix
16-Pin Plastic
MIN
MIN
MAX
MAX
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
H
J
K
L
M
S
18.80
6.35
3.69
0.39
1.02
0.21
2.80
7.50
0
°
0.51
19.55
6.85
4.44
0.53
1.77
0.38
3.30
7.74
10
°
1.01
0.740
0.250
0.145
0.015
0.040
0.008
0.110
0.295
0
°
0.020
0.770
0.270
0.175
0.021
0.070
0.015
0.130
0.305
10
°
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L" TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B" DOES NOT INCLUDE MOLD
FLASH.
5. ROUNDED CORNERS OPTIONAL.
6. 648 01 THRU 07 OBSOLETE, NEW STANDARD
648 08.
2.54 BSC
1.27 BSC
0.100 BSC
0.050 BSC
-A-
B
1
8
9
16
F
H
G
D
16 PL
S
C
-T-
SEATING
PLANE
K
J
M
L
T A
0.25 (0.010)
M
M
Case 620-09 J Suffix
16-Pin Ceramic Dual In-Line
MIN
MIN
MAX
MAX
MILLIMETERS
INCHES
DIM
19.05
6.10
0.39
1.40
0.23
0
°
0.39
19.55
7.36
4.19
0.53
1.77
0.27
5.08
15
°
0.88
0.750
0.240
0.015
0.055
0.009
0
°
0.015
0.770
0.290
0.165
0.021
0.070
0.011
0.200
15
°
0.035
1.27 BSC
2.54 BSC
7.62 BSC
0.050 BSC
0.100 BSC
0.300 BSC
A
B
C
D
E
F
G
J
K
L
M
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
5. 620 01 THRU 08 OBSOLETE, NEW STANDARD
620 09.
-B-
-A-
16 PL
-T-
C
D
E
F
G
J
K
M
N
SEATING
PLANE
16 PL
L
16
9
1
8
0.25 (0.010)
T A
M
S
0.25 (0.010)
T B
M
S
5-562
FAST AND LS TTL DATA
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