MOTOROLA CMOS LOGIC DATA

MC14093B

Quad 2-Input NAND"

Schmitt Trigger

The MC14093B Schmitt trigger is constructed with MOS Pґchannel and

Nґchannel enhancement mode devices in a single monolithic structure.
These devices find primary use where low power dissipation and/or high
noise immunity is desired. The MC14093B may be used in place of the
MC14011B quad 2ґinput NAND gate for enhanced noise immunity or to
"square up" slowly changing waveforms.

Supply Voltage Range = 3.0 Vdc to 18 Vdc

Capable of Driving Two LowґPower TTL Loads or One LowґPower
Schottky TTL Load Over the Rated Temperature Range

Triple Diode Protection on All Inputs

PinґforґPin Compatible with CD4093

Can be Used to Replace MC14011B

Independent SchmittґTrigger at each Input

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MAXIMUM RATINGS*

(Voltages Referenced to VSS)

нннн

Symbol

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Parameter

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Value

ннн

Unit

нннн

VDD

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DC Supply Voltage

нннннн

ґ 0.5 to + 18.0

ннн

нннн

Vin, Vout

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Input or Output Voltage (DC or Transient)

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ґ 0.5 to VDD + 0.5

ннн

нннн

Iin, Iout

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Input or Output Current (DC or Transient),
per Pin

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╠

ннн

нннн

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Power Dissipation, per Package

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500

ннн

нннн

Tstg

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Storage Temperature

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ґ 65 to + 150

ннн

нннн

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Lead Temperature (8ґSecond Soldering)

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260

ннн

* Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating:

Plastic "P and D/DW" Packages: ґ 7.0 mW/

C From 65

C To 125

Ceramic "L" Packages: ґ 12 mW/

C From 100

C To 125

EQUIVALENT CIRCUIT SCHEMATIC

(1/4 OF CIRCUIT SHOWN)

This device contains protection circuitry to guard against damage

due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS

(Vin or Vout)

VDD.

Unused inputs must always be tied to an appropriate logic voltage

level (e.g., either VSS or VDD). Unused outputs must be left open.

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

╘

Motorola, Inc. 1995

REV 3
1/94

MC14077B

See Page 6-160

MC14078B, MC14081B, MC14082B

See Page 6-5

MC14093B

L SUFFIX

CERAMIC
CASE 632

ORDERING INFORMATION

MC14XXXBCP

Plastic

MC14XXXBCL

Ceramic

MC14XXXBD

SOIC

TA = ґ 55

╟

to 125

╟

C for all packages.

P SUFFIX

PLASTIC

CASE 646

D SUFFIX

SOIC

CASE 751A

LOGIC DIAGRAM

VDD = PIN 14

VSS = PIN 7

MOTOROLA CMOS LOGIC DATA

MC14093B
2

нннннннннннннннннннннннннннннннннн

ELECTRICAL CHARACTERISTICS

(Voltages Referenced to VSS)

нннннннннн

Characteristic

нннн

Symbol

ннн

VDD

Vdc

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ґ 55

нннннннн

нннннн

125

ннн

Unit

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Characteristic

нннн

Symbol

ннн

VDD

Vdc

ннн

Min

нннн

Max

ннн

Min

нннн

Typ #

ннн

Max

нннн

Min

ннн

Max

ннн

Unit

нннннннннн

Output Voltage

"0" Level

Vin = VDD or 0

"1" Level

Vin = 0 or VDD

нннн

VOL

ннн

5.0

10
15

ннн

--
--
--

нннн

0.05
0.05
0.05

ннн

--
--
--

нннн

0
0
0

ннн

0.05
0.05
0.05

нннн

--
--
--

ннн

0.05
0.05
0.05

ннн

Vdc

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"1" Level

Vin = 0 or VDD

нннн

VOH

ннн

5.0

10
15

ннн

4.95
9.95

14.95

нннн

--
--
--

ннн

4.95
9.95

14.95

нннн

5.0

10
15

ннн

--
--
--

нннн

4.95
9.95

14.95

ннн

--
--
--

ннн

Vdc

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Output Drive Current

(VOH = 2.5 Vdc)

Source

(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)

нннн

IOH

ннн

5.0
5.0

10
15

ннн

ґ 3.0

ґ 0.64

ґ 1.6
ґ 4.2

нннн

--
--
--
--

ннн

ґ 2.4

ґ 0.51

ґ 1.3
ґ 3.4

нннн

ґ 4.2

ґ 0.88
ґ 2.25

ґ 8.8

ннн

--
--
--
--

нннн

ґ 1.7

ґ 0.36

ґ 0.9
ґ 2.4

ннн

--
--
--
--

ннн

mAdc

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(VOL = 0.4 Vdc)

Sink

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)

нннн

IOL

ннн

5.0

10
15

ннн

0.64

1.6
4.2

нннн

--
--
--

ннн

0.51

1.3
3.4

нннн

0.88
2.25

8.8

ннн

--
--
--

нннн

0.36

0.9
2.4

ннн

--
--
--

ннн

mAdc

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Input Current

нннн

Iin

ннн

нннн

╠

0.1

ннн

нннн

╠

0.00001

ннн

╠

0.1

нннн

ннн

╠

1.0

ннн

╣

Adc

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Input Capacitance

(Vin = 0)

нннн

Cin

ннн

нннн

ннн

нннн

5.0

ннн

7.5

нннн

ннн

нннннннннн

Quiescent Current

(Per Package)

нннн

IDD

ннн

5.0

10
15

ннн

--
--
--

нннн

0.25

0.5
1.0

ннн

--
--
--

нннн

0.0005
0.0010
0.0015

ннн

0.25

0.5
1.0

нннн

--
--
--

ннн

7.5

15
30

ннн

╣

Adc

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Total Supply Current**

(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)

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ннн

5.0

10
15

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IT = (1.2

╣

A/kHz) f + IDD

IT = (2.4

╣

A/kHz) f + IDD

IT = (3.6

╣

A/kHz) f + IDD

ннн

╣

Adc

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Hysteresis Voltage

нннн

ннн

5.0

10
15

ннн

0.3
1.2
1.6

нннн

2.0
3.4
5.0

ннн

0.3
1.2
1.6

нннн

1.1
1.7
2.1

ннн

2.0
3.4
5.0

нннн

0.3
1.2
1.6

ннн

2.0
3.4
5.0

ннн

Vdc

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Threshold Voltage

PositiveґGoing

нннн

VT+

ннн

5.0

10
15

ннн

2.2
4.6
6.8

нннн

3.6
7.1

10.8

ннн

2.2
4.6
6.8

нннн

2.9
5.9
8.8

ннн

3.6
7.1

10.8

нннн

2.2
4.6
6.8

ннн

3.6
7.1

10.8

ннн

Vdc

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NegativeґGoing

нннн

VTґ

ннн

5.0

10
15

ннн

0.9
2.5
4.0

нннн

2.8
5.2
7.4

ннн

0.9
2.5
4.0

нннн

1.9
3.9
5.8

ннн

2.8
5.2
7.4

нннн

0.9
2.5
4.0

ннн

2.8
5.2
7.4

ннн

Vdc

#Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.

** The formulas given are for the typical characteristics only at 25

To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL ґ 50) Vfk

where: IT is in

╣

A (per package), CL in pF, V = (VDD ґ VSS) in volts, f in kHz is input frequency, and k = 0.004.

MOTOROLA CMOS LOGIC DATA

MC14093B

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SWITCHING CHARACTERISTICS

(CL = 50 pF, TA = 25

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Characteristic

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Symbol

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VDD

Vdc

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Min

нннн

Typ #

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Max

ннн

Unit

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Output Rise Time

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tTLH

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5.0

10
15

нннн

--
--
--

нннн

100

50
40

нннн

200
100

ннн

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Output Fall Time

нннн

tTHL

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5.0

10
15

нннн

--
--
--

нннн

100

50
40

нннн

200
100

ннн

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Propagation Delay Time

нннн

tPLH, tPHL

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5.0

10
15

нннн

--
--
--

нннн

125

50
40

нннн

250
100

ннн

#Data labeled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.

Figure 1. Switching Time Test Circuit and Waveforms

PULSE

GENERATOR

VDD

OUTPUT

VSS

INPUT

20 ns

VDD

VSS

VOH

VOL

tPLH

tPHL

OUTPUT

INPUT

tTHL

tTLH

90%

50%

10%

90%

50%

10%

Vout

Vin

VDD

VSS

VDD

VSS

(a) Schmitt Triggers will square up

(a)

inputs with slow rise and fall times.

(b) A Schmitt trigger offers maximum

(b)

noise immunity in gate applications.

Vout

Vin

VDD

VSS

VDD

VSS

Figure 2. Typical Schmitt Trigger Applications

MOTOROLA CMOS LOGIC DATA

MC14093B
6

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751Aґ03

ISSUE F

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

ґAґ

ґBґ

7 PL

0.25 (0.010)

ґTґ

X 45

SEATING
PLANE

14 PL

DIM

MIN

MAX

MIN

MAX

INCHES

MILLIMETERS

8.55

8.75

0.337

0.344

3.80

4.00

0.150

0.157

1.35

1.75

0.054

0.068

0.35

0.49

0.014

0.019

0.40

1.25

0.016

0.049

1.27 BSC

0.050 BSC

0.19

0.25

0.008

0.009

0.10

0.25

0.004

0.009

5.80

6.20

0.228

0.244

0.25

0.50

0.010

0.019

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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MC14093B/D

*MC14093B/D*

Part Number MC14093B