MC12009
MC12011
MC12013
SEMICONDUCTOR
TECHNICAL DATA
MECL PLL COMPONENTS
DUAL MODULUS PRESCALER
1
16
15
14
13
12
11
10
9
2
3
4
5
6
7
8
(Top View)
VCCO
Q
Q
MTTL VCC
MTTL Output
VEE
VCC
E5 MECL
PIN CONNECTIONS
Order this document by MC12009/D
P SUFFIX
PLASTIC PACKAGE
CASE 648
Clock
VBB
E2 MECL
E1 MECL
E3 MECL
E4 MECL
( )
( + )
16
1
Device
Operating
Temperature Range
Package
ORDERING INFORMATION
MC12009P
MC12011P
TA = 35
°
to +85
°
C
Plastic
MC12013P
Dual Modulus Prescaler
These devices are twomodulus prescalers which will divide by 5 and
6, 8 and 9, and 10 and 11, respectively. A MECLtoMTTL translator is
provided to interface directly with the MC12014 Counter Control Logic. In
addition, there is a buffered clock input and MECL bias voltage source.
·
MC12009 480 MHz (
B
5/6), MC12011 550 MHz (
B
8/9), MC12013
550 MHz (
B
10/11)
·
MECL to MTTL Translator on Chip
·
MECL and MTTL Enable Inputs
·
5.0 or 5.2 V Operation*
·
Buffered Clock Input -- Series Input RC Typ, 20 Ohms and 4 pF
·
VBB Reference Voltage
·
310 Milliwatts (Typ)
* When using a 5.0 V supply, apply 5.0 V to Pin 1 (VCCO), Pin 6
(MTTL VCC), Pin 16 (VCC), and ground Pin 8 (VEE). When using
5.2 V supply, ground Pin 1 (VCCO), Pin 6 (MTTL VCC), and
Pin 16 (VCC) and apply 5.2 V to Pin 8 (VEE). If the translator is not
required, Pin 6 may be left open to conserve dc power drain.
MAXIMUM RATINGS
Characteristic
Symbol
Rating
Unit
(Ratings above which device life may be impaired)
Power Supply Voltage
(VCC = 0)
VEE
8.0
Vdc
Input Voltage
(VCC = 0)
Vin
0 to VEE
Vdc
Output Source Current
Continuous
Surge
IO
t
50
t
100
mAdc
Storage Temperature Range
Tstg
65 to +175
°
C
(Recommended Maximum Ratings above which performance may be
degraded)
Operating Temperature Range
MC12009, MC12011, MC12013
TA
30 to +85
°
C
DC FanOut (Note 1)
(Gates and FlipFlops)
n
70
--
NOTES: 1. AC fanout is limited by desired system performance.
2. ESD data available upon request.
©
Motorola, Inc. 1997
Rev 2
MC12009 MC12011 MC12013
2
MOTOROLA RF/IF DEVICE DATA
MC12013
MECL
to
MTTL
Trans
lator
MTTL
Out
Q2
C
D
VBB
Toggle
Flip
Flop
Q4
C
5 4
+
0.1
µ
F
1 k
14
Q1
C
D
15
C
2
3
Q4
Q4
Q4
fref
LowPass Filter
fout
Phase Detector
MC4044
MC12009
MC12011
MC12013
B
A Programmable
Counter MC4016
Modulus Enable Line
Counter Control Logic
MC12014
B
Np Programmable
Counter MC4016
Counter Reset Line
Zero Detect Line
VoltageControlled
Oscillator MC1648
fout
Recommended Circuitry
For ac coupled Inputs.
0.1
µ
F
MC12011
1 k
14
VBB
3 2
Q4 Q4
15
Recommended Circuitry
For ac coupled Inputs.
MECL
to
MTTL
Trans
lator
MTTL
Out
+
4
5
Q4
Q2
C
Q4
D
C
Toggle
Flip
Flop
D
C
D
C
Q1
Q3
Q3
D
Figure 1. Logic Diagrams
MECL E1
MECL E2
MTTL E4
MECL E3
MTTL E5
MECL
to
MTTL
Trans
lator
MTTL
Out
+
0.1
µ
F
1 k
1000 pF
MC12009
4
5
Q3
2
Q3
3
14
VBB
15
Recommended Circuitry
For ac coupled Inputs.
C
D
C
D
Q1
Q1
C
D
Q2
Q3
Q3
9
10
11
12
13
MECL E1
MECL E2
MTTL E4
MECL E3
MTTL E5
9
10
11
12
13
MECL E1
MECL E2
MTTL E4
MECL E3
MTTL E5 9
10
11
12
13
7
7
7
÷
10 for one or all
E1 thru E5 high
÷
11 for all
E1 thru E5 low
Tie unused gate inputs low.
Pulldown resistors required on
Pins 2, 3 when not connected
to translator.
Basic IC Capability:
÷
10/11
Clock Input
1000 pF
Clock Input
1000 pF
Clock Input
1000 pF
Clock Input
Figure 2. Typical Frequency Synthesizer Application
MC12009 MC12011 MC12013
3
MOTOROLA RF/IF DEVICE DATA
ELECTRICAL CHARACTERISTICS
(Supply Voltage = 5.2 V, unless otherwise noted.)
Pi
Test Limits
Pin
Under
30
°
C
+25
°
C
+85
°
C
Characteristic
Symbol
Under
Test
Min
Max
Min
Max
Min
Max
Unit
Power Supply Drain Current
ICC1
8
88
80
80
mAdc
pp y
ICC2
6
5.2
5.2
5.2
mAdc
Input Current
IinH1
15
11
12
13
375
375
375
375
250
250
250
250
250
250
250
250
µ
Adc
IinH2
4
5
1.7
1.7
6.0
6.0
2.0
2.0
6.0
6.0
2.0
2.0
6.4
6.4
mAdc
IinH3
5
0.7
3.0
1.0
3.0
1.0
3.6
IinH4
9
10
100
100
100
100
100
100
µ
Adc
Leakage Current
IinL1
15
11
12
13
10
10
10
10
10
10
10
10
10
10
10
10
µ
Adc
IinL2
9
10
1.6
1.6
1.6
1.6
1.6
1.6
mAdc
Reference Voltage
VBB
14
1.360
1.160
Vdc
Logic `1' Output Voltage
VOH1
(Note 1)
2
3
1.100
1.100
0.890
0.890
1.000
1.000
0.810
0.810
0.930
0.930
0.700
0.700
Vdc
VOH2
7
2.8
2.6
2.4
Logic `0' Output Voltage
VOL1
(Note 1)
2
3
1.990
1.990
1.675
1.675
1.950
1.950
1.650
1.650
1.925
1.925
1.615
1.615
Vdc
VOL2
7
4.26
4.40
4.48
Logic `1' Threshold Voltage
VOHA
(Note 2)
2
3
1.120
1.120
1.020
1.020
0.950
0.950
Vdc
Logic `0' Threshold Voltage
VOLA
(Note 3)
2
3
1.655
1.655
1.630
1.630
1.595
1.595
Vdc
Short Circuit Current
IOS
7
65
20
65
20
65
20
mAdc
1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and
ground voltages must be maintained between tests. The clock input is the waveform shown.
2. In addition to meeting the output levels specified, the device must divide by 5, 8 or 10 during this test. The clock
input is the waveform shown.
3. In addition to meeting the output levels specified, the device must divide by 6, 9 or 11 during this test. The clock
input is the waveform shown.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50
resistor to 2.0 V. Test procedures are shown for only one gate. The other gates are tested in the same
manner.
VIHmax
VILmin
Clock Input
MC12009 MC12011 MC12013
4
MOTOROLA RF/IF DEVICE DATA
ELECTRICAL CHARACTERISTICS
(Supply Voltage = 5.2 V, unless otherwise noted.) (continued)
TEST VOLTAGE/CURRENT VALUES
Volts
@ Test Temperature
VIHmax
VILmin
VIHAmin VILAmax
VIH
VILH
30
°
C
0.890
1.990
1.205
1.500
2.8
4.7
+25
°
C
0.810
1.950
1.105
1.475
2.8
4.7
+85
°
C
0.700
1.925
1.035
1.440
2.8
4.7
Pin
Under
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
G d
Characteristic
Symbol
Under
Test
VIHmax
VILmin
VIHAmin VILAmax
VIH
VIL
Gnd
Power Supply Drain Current
ICC1
8
1,16
ICC2
6
4
5
6
Input Current
IinH1
15
11
12
13
15
11
12
13
1,16
1,16
1,16
1,16
IinH2
4
5
5
5
4
4
6
6
IinH3
5
4
5
6
IinH4
9
10
9
10
1,16
1,16
Leakage Current
IinL1
15
11
12
13
1,16
1,16
1,16
1,16
IinL2
9
10
9
10
1,16
1,16
Reference Voltage
VBB
14
1,16
Logic `1' Output Voltage
VOH1
(Note 1.)
2
3
11,12,13
11,12,13
9,10
9,10
1,16
1,16
VOH2
7
5
4
6
Logic `0' Output Voltage
VOL1
(Note 1.)
2
3
11,12,13
11,12,13
9,10
9,10
1,16
1,16
VOL2
7
4
5
6
Logic `1' Threshold Voltage
VOHA
(Note 2.)
2
3
11,12,13
11,12,13
1,16
1,16
Logic `0' Threshold Voltage
VOLA
(Note 3.)
2
3
11,12,13
11,12,13
1,16
1,16
Short Circuit Current
IOS
7
5
4
7
6
1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and
ground voltages must be maintained between tests. The clock input is the waveform shown.
2. In addition to meeting the output levels specified, the device must divide by 5, 8 or 10 during this test. The clock
input is the waveform shown.
3. In addition to meeting the output levels specified, the device must divide by 6, 9 or 11 during this test. The clock
input is the waveform shown.
VIHmax
VILmin
Clock Input
MC12009 MC12011 MC12013
5
MOTOROLA RF/IF DEVICE DATA
ELECTRICAL CHARACTERISTICS
(Supply Voltage = 5.2 V, unless otherwise noted.) (continued)
TEST VOLTAGE/CURRENT VALUES
Volts
mA
@ Test Temperature
VIHT
VILT
VEE
IL
IOL
IOH
30
°
C
3.2
4.4
5.2
0.25
16
0.40
+25
°
C
3.2
4.4
5.2
0.25
16
0.40
+85
°
C
3.2
4.4
5.2
0.25
16
0.40
Pin
Under
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
G d
Characteristic
Symbol
Under
Test
VIHT
VILT
VEE
IL
IOL
IOH
Gnd
Power Supply Drain Current
ICC1
8
8
1,16
ICC2
6
8
6
Input Current
IinH1
15
11
12
13
9,10
9,10
9,10
8
8
8
8
1,16
1,16
1,16
1,16
IinH2
4
5
8
8
6
6
IinH3
5
8
6
IinH4
9
10
8
8
1,16
1,16
Leakage Current
IinL1
15
11
12
13
8,15
8,11
8,12
8,13
1,16
1,16
1,16
1,16
IinL2
9
10
8
8
1,16
1,16
Reference Voltage
VBB
14
8
14
1,16
Logic `1' Output Voltage
VOH1
(Note 1.)
2
3
8
8
1,16
1,16
VOH2
7
8
7
6
Logic `0' Output Voltage
VOL1
(Note 1.)
2
3
8
8
1,16
1,16
VOL2
7
8
7
6
Logic `1' Threshold Voltage
VOHA
(Note 2.)
2
3
9,10
9,10
8
8
1,16
1,16
Logic `0' Threshold Voltage
VOLA
(Note 3.)
2
3
9,10
9,10
8
8
1,16
1,16
Short Circuit Current
IOS
7
8
6
1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and
ground voltages must be maintained between tests. The clock input is the waveform shown.
2. In addition to meeting the output levels specified, the device must divide by 5, 8 or 10 during this test. The clock
input is the waveform shown.
3. In addition to meeting the output levels specified, the device must divide by 6, 9 or 11 during this test. The clock
input is the waveform shown.
VIHmax
VILmin
Clock Input
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