3-83

Figure 1 - Functional Block Diagram

Mode

FSEL1

FSEL2

PRI

VDD

VSS

C1.5

C16

F0o

FP8-STB

FP8-GCI

Interface

Divider

Circuit

MCLKo

MCLKi

IC0

IC1

Phase

Loop

DCO

Detector

Filter

Select

Features

Provides T1 and E1 clocks, and ST-BUS/GCI
framing signals locked to an input reference of
either 8 kHz (frame pulse), 1.544 MHz (T1), or
2.048 MHz (E1)

Meets AT & T TR62411 and ETSI ETS 300 011
specifications for a 1.544 MHz (T1), or
2.048 MHz (E1) input reference

Typical unfiltered intrinsic output jitter is
0.013 UI peak-to-peak

Jitter attenuation of 15 dB @ 10 Hz,
34 dB @ 100 Hz and 50 dB @ 5 to 40 kHz

Low power CMOS technology

Applications

Synchronization and timing control for T1 and
E1 digital transmission links

ST-BUS clock and frame pulse sources

Primary Trunk Rate Converters

Description

The MT9041 is a digital phase-locked loop (PLL)
designed to provide timing and synchronization
signals for T1 and E1 primary rate transmission links
that are compatible with ST-BUS/GCI frame
alignment timing requirements. The PLL outputs can
be synchronized to either a 2.048 MHz, 1.544 MHz,
or 8 kHz reference. The T1 and E1 outputs are fully
compliant with AT & T TR62411 (ACCUNET

T1.5)

and ETSI ETS 300 011 intrinsic jitter and jitter
transfer specifications, respectively, when
synchronized to primary reference input clock rates
of either 1.544 MHz or 2.048 MHz.

The PLL also provides additional high speed output
clocks at rates of 3.088 MHz, 4.096 MHz, 8.192
MHz, and 16.384 MHz for backplane synchro-
nization.

Ordering Information

MT9041AP

28 Pin PLCC

-40

C to +85

ISSUE 1

May 1995

MT9041

Multiple Output Trunk PLL

Advance Information

MT9041

Advance Information

3-84

Figure 2 - Pin Connections

Pin Description

Pin #

Name

Description

Negative Power Supply Voltage. Nominally 0 Volts.

2,3

IC0

Internal Connection 0. Connect to V

SS.

PRI

Primary Reference Input (TTL compatible). This input (either 8 kHz, 1.544 MHz, or 2.048
MHz as controlled by the input frequency selection pins) is used as the primary reference
source for PLL synchronization.

Positive Supply Voltage. Nominally +5 volts.

MCLKo

Master Clock Oscillator Output. This is a CMOS buffered output used for driving a 20 MHz
crystal.

MCLKi

Master Clock Oscillator Input. This is a CMOS input for a 20 MHz crystal or crystal
oscillator. Signals should be DC coupled to this pin.

FP8-GCI Frame Pulse Output (CMOS compatible). This is an 8 kHz output framing pulse that

indicates the start of the active GCI-BUS frame. The pulse width is based upon the period of
the 8.192 MHz synchronization clock.

F0o

Frame Pulse Output (CMOS compatible). This is an 8 kHz output framing pulse that
indicates the start of the active ST-BUS frame. The pulse width is based upon the period of
the 4.096 MHz synchronization clock. This is an active low signal.

FP8-STB Frame Pulse Output (CMOS compatible). This is an 8 kHz output framing pulse that

indicates the start of the active ST-BUS frame. The pulse width is based upon the period of
the 8.192 MHz synchronization clock.

C1.5

Clock 1.544 MHz (CMOS compatible). This ouput is a 1.544 MHz (T1) output clock locked
to the reference input signal.

Clock 3.088 MHz (CMOS compatible). This output is a 3.088 MHz output clock locked to
the reference input signal.

Clock 2.048 MHz (CMOS compatible). This output is a 2.048 MHz (E1) output clock
locked to the reference input signal.

Clock 4.096 MHz (CMOS compatible). This output is a 4.096 MHz output clock locked to
the reference input signal.

Negative Power Supply Voltage. Nominally 0 Volts.

Clock 8.192 MHz (CMOS compatible). This output is an 8.192 MHz output clock locked to
the reference input signal.

8
9

PRI

VDD

MCLKo

MCLKi

FP8-GCI

F0o

FP8-STB

C1.5

IC0

IC1

IC0

SEL

RST

12 13 14 15 16 17 18

VSS

VDD

Advance Information

MT9041

3-85

C16

Clock 16.384 MHz (CMOS compatible). This output is a 16.384 MHz output clock locked
to the reference input signal.

Positive Supply Voltage. Nominally +5 volts.

IC0

Internal Connection 0. Connect to V

SS.

IC1

Internal Connection 1. Leave open circuit.

21, 22

IC0

Internal Connection 0. Connect to V

SS.

Mode Select Input (TTL compatible). This input selects the PLL mode of operation (i.e. ,
NORMAL or FREERUN, see Table 1).

24, 25

IC0

Internal Connection 0. Connect to V

SS.

FSEL2

Frequency Select - 2 Input (TTL compatible). This input, in conjunction with FSEL1,
selects the frequency of the input reference source (i.e., 8 kHz, 1.544 MHz, or 2.048 MHz;
see Table 3).

FSEL1

Frequency Select - 1 Input (TTL compatible). This input, in conjunction with FSEL2,
selects the frequency of the input reference source (i.e., 8 kHz, 1.544 MHz, or 2.048 MHz;
see Table 3).

RST

Reset (TTL compatible). This input (active LOW) puts the MT9041 in its reset state. To
guarantee proper operation, the device must be reset after power-up. The time constant for
a power-up reset circuit must be a minimum of five times the rise time of the power supply. In
normal operation, the RST pin must be held low for a minimum of 60 nsec to reset the
device.

Pin Description (continued)

Pin #

Name

Description

MT9041

Advance Information

3-86

Functional Description

The MT9041 is a fully digital, phase-locked loop
designed to provide timing references to interface
circuits for T1 and E1 Primary Rate Digital
Transmission links. As shown in Figure 1, the PLL
employs a high resolution Digitally Controlled
Oscillator (DCO) to generate the T1 and E1 outputs.

The interface circuit on the output of the DCO
generates 1.544 MHz (C1.5), 3.088 MHz (C3), 2.048
MHz (C2), 4.096 MHz (C4), 8.192 MHz (C8), 16.384
MHz (C16), and three 8 kHz frame pulses F0o, FP8-
STB, and FP8-GCI.

Figure 3 - PLL Block Diagram

As shown in Figure 3, the PLL of the MT9041
consists of a phase detector (PD), a loop filter, a high
resolution DCO, and a digital frequency divider. The
digitally controlled oscillator (DCO) is locked in
frequency (n x f

ref

) to one of three possible reference

frequencies, configured using pins FSEL1 and
FSEL2. The PLL is capable of providing a full range
of E1/T1 clock signals synchronized to the primary
PRI input. The loop filter is a first order lowpass
structure that provides approximately a 2 Hz
bandwidth.

Modes of Operation

The MT9041 can operate in one of two modes,
NORMAL or FREERUN, as controlled by mode
select pin MS (see Table 1).

Normal Mode

There are three possible input frequencies for
selection as the primary reference clock. These are 8
kHz, 1.544 MHz or 2.048 MHz. Frequency selection

Description of Operation

NORMAL

FREERUN

Table 1- Operating Modes of the MT9041

Divider

DCO

Phase

Loop

Filter

ref

sync

Detector

is controlled by the logic levels of FSEL1 and FSEL2,
as shown in Table 2. This variety of input frequencies
was chosen to allow the generation of all the
necessary T1 and E1 clocks from either a T1, E1 or
frame pulse reference source.

PLL Measures of Performance

To meet the requirements of AT & T TR62411 and
ETSI 300 011, the following PLL performance
parameters were measured:

locking range and lock time

free-run accuracy

intrinsic jitter

jitter transfer function

output jitter spectrum

wander

Locking Range and Lock Time

The locking range of the PLL is the range that the
input reference frequency can be deviated from its
nominal frequency while the output signals maintain
synchronization. The relevant value is usually
specified in parts-per-million (ppm). For both the T1
and E1 outputs, lock was maintained while an 8 kHz
input was varied between 7900 Hz to 8100 Hz
(corresponding to

12500 ppm). This is well beyond

the required

100 ppm. The lock range of 12500

ppm also applies to 1.544 MHz and 2.048 MHz
reference inputs.

The lock time is a measure of how long it takes the
PLL to reach steady state frequency after a
frequency step on the reference input signal. The
locking time is measured by applying an 8000 Hz
signal to the primary reference and an 8000.8 Hz
(+100 ppm) to the secondary reference. The output
is monitored with a time interval analyzer during slow
periodic rearrangements on the reference inputs.

The lock time for both the T1 and E1 outputs is
approximately 311 ms, which is well below the
required lock time of 1.0 seconds.

FSEL

Input Reference

Frequency

Reserved

8 kHz

1.544 MHz

2.048 MHz

Table 2 - Input Frequency Selection of the MT9041

Advance Information

MT9041

3-87

Freerun Accuracy

The Freerun accuracy of the PLL is a measure of
how accurately the PLL can reproduce the desired
output frequency. The freerun accuracy is a function
of master clock frequency which must be 20 MHz

32 ppm in order to meet AT & T TR62411 and ETSI

specifications.

Jitter Performance

The output jitter of a digital trunk PLL is composed of
intrinsic jitter, measured using a jitter free reference
clock, and frequency dependent jitter, measured by
applying known levels of jitter on the references
clock. The jitter spectrum indicates the frequency
content of the output jitter.

Intrinsic Jitter

Intrinsic jitter is the jitter added to an output signal by
the processing device, in this case the enhanced
PLL. Tables 3 and 4 show the average measured
intrinsic jitter of the T1 and E1 outputs. Each
measurement is an average based upon a

100 ppm

deviation (in steps of 20 ppm) on the input reference
clock. Jitter on the master clock will increase intrinsic
jitter of the device, hence attention to minimization of
master clock jitter is required.

Jitter Transfer Function

The jitter transfer function is a measure of the
transfer characteristics of the PLL to frequency
specific jitter on the referenced input of the PLL. It is
directly linked to the loop bandwidth and the
magnitude of the phase error suppression
characteristics of the PLL. It is measured by applying
jitter of specific magnitude and frequencies to the
input of the PLL, then measuring the magnitude of
the output jitter (both filtered and unfiltered) on the
T1 or E1 output.

Care must be taken when measuring the transfer
characteristics to ensure that critical jitter alias
frequencies are included in the measurement (i.e.,
for digital phase locked loops using an 8 kHz input).

Tables 5 and 6 provide measured results for the jitter
transfer characteristics of the PLL for both a 1.544
MHz and 2.048 MHz reference input clock. The
transfer characteristics for an 8 kHz reference input
will be the same.

Figures 4 and 5 show the jitter attenuation
performance of the T1 and E1 outputs plotted
against AT & T TR62411 and ETSI requirements,
respectively.

Output Jitter in UIp-p

Reference Input

FLT0 Unfiltered

FLT1

10Hz - 8kHz

FLT2

10Hz - 40kHz

FLT3

8kHz - 40kHz

8 kHz

.011

.004

.006

.002

1.544 MHz

.011

.001

.002

.001

2.048 MHz

.011

.001

.002

.001

Table 3 -Typical Intrinsic Jitter for the T1 Output

Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing

Output Jitter in UIp-p

Reference Input

FLT0 Unfiltered

FLT1

20Hz - 100kHz

FLT2

700Hz - 100kHz

8 kHz

.011

.002

1.544 MHz

.011

.002

2.048 MHz

.011

.002

Table 4 - Typical Intrinsic Jitter for the E1 Output

Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing

MT9041

Advance Information

3-88

Input Jitter

Modulation

Frequency

(Hz)

Input Jitter

Magnitude

(UIp-p)

Measured Jitter Output (UIp-p)

T1 Reference Input

E1 Reference Input

Output Jitter

Magnitude

(UIp-p)

Jitter

Attenuation

(dB)

Output Jitter

Magnitude

(UIp-p)

Jitter

Attenuation

(dB)

2.42

18.34

2.41

18.38

1.62

21.83

1.618

21.84

.900

26.94

.908

26.86

100

.375

34.54

.376

34.52

330

.060

44.44

.060

44.44

500

.032

47.96

.032

47.96

1000

.015

53.38

.015

53.38

5000

0.8

.003

48.52

.003

48.52

7900

1.044

.003

50.83

.003

50.83

7950

1.044

.003

50.83

.003

50.83

7980

1.044

.003

50.83

.003

50.83

7999

1.044

.003

50.83

.003

50.83

8001

1.044

.003

50.83

.003

50.83

8020

1.044

.003

50.83

.003

50.83

8050

1.044

.003

50.83

.003

50.83

8100

1.044

.003

50.83

.003

50.83

10000

0.4

.003

42.50

.003

42.50

Table 5 - Typical Jitter Transfer Function for the T1 Output

Notes

1) For input jitter from 10 kHz to 100 kHz, the jitter attenuation is of such magnitude that intrinsic jitter dominates the output
signal, rendering the jitter transfer function unmeasurable.

2) Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing

Advance Information

MT9041

3-89

Input Jitter

Modulation

Frequency

(Hz)

Input Jitter

Magnitude

(UIp-p)

Measured Jitter Output (UIp-p)

T1 Reference Input

E1 Reference Input

Output Jitter

Magnitude

(UIp-p)

Jitter

Attenuation

(dB)

Output Jitter

Magnitude

(UIp-p)

Jitter

Attenuation

(dB)

1.5

.355

12.52

.351

12.62

1.5

.186

18.13

.185

18.18

1.5

.095

23.97

.096

23.88

100

1.5

.039

31.70

.039

31.70

200

1.5

.021

37.08

.020

37.50

400

1.5

.012

41.94

.012

41.94

1000

1.5

.006

47.96

.007

46.62

7900*

1.044

.002

54.35

.002

54.35

7950*

1.044

.002

54.35

.002

54.35

7980*

1.044

.002

54.35

.002

54.35

7999*

1.044

.002

54.35

.002

54.35

8001*

1.044

.002

54.35

.002

54.35

8020*

1.044

.002

54.35

.002

54.35

8050*

1.044

.002

54.35

.002

54.35

8100*

1.044

.002

54.35

.002

54.35

10000

0.35

.004

38.84

.003

41.34

100000

0.20

.004

33.98

.003

36.48

Table 6 - Typical Jitter Transfer Function for the E1 Output

Notes

1) For input jitter from 10 kHz to 100 kHz, the jitter attenuation is of such magnitude that intrinsic jitter dominates the output
signal, rendering the jitter transfer function unmeasurable.

2) Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing

* Output jitter dominated by intrinsic jitter.

MT9041

Advance Information

3-90

Figure 4 - Typical Jitter Attenuation for T1 Output

Figure 5 - Typical Jitter Attenuation for E1 Output

100

300

10K

I
TT

I
O

(

)

SLOPE -20 dB PER DECADE

SLOPE -40 dB
PER DECADE

Frequency (Hz)

AAAA

AAA

-0.5

19.5

I
TT

I
O

(

)

400

10K

-20 dB/decade

Frequency (Hz)

Advance Information

MT9041

3-91

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

Absolute Maximum Ratings*

- Voltages are with respect to ground (V

) unless otherwise stated.

Parameter

Symbol

Min

Max

Units

Supply Voltage

-0.3

7.0

Voltage on any pin

-0.3

+0.3

Input/Output Diode Current

IK/OK

ą150

Output Source or Sink Current

ą150

DC Supply or Ground Current

ą300

Storage Temperature

-55

125

°C

Package Power Dissipation

PLCC

900

Recommended Operating Conditions

- Voltages are with respect to ground (V

) unless otherwise stated.

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Supply Voltage

4.5

5.0

5.5

Input HIGH Voltage

2.0

Input LOW Voltage

0.8

Operating Temperature

-40

°C

DC Electrical Characteristics

- Voltages are with respect to ground (V

) unless otherwise stated.

=5.0 Vą10%; V

=0V; T

=-40 to 85°C.

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

S
U
P

Supply Current

Under operating condition

Input HIGH voltage

2.0

Input LOW voltage

0.8

O
U

Output current HIGH

-4

=2.4 V

Output current LOW

=0.4 V

Leakage current on all inputs

MT9041

Advance Information

3-92

AC Electrical Characteristics (see Fig. 6)

-Voltages are with respect to ground (V

) unless otherwise stated.

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

8 kHz reference clock period

P8R

125

T
S

1.544 MHz reference clock period

P15R

648

2.048 MHz reference clock period

P20R

488

Input to output propagation delay
with an 8 kHz reference clock

PD8

183

MCLKi =
20.000 000MHz

Input to output propagation delay
with a 1.544 MHz reference clock

PD15

243

MCLKi =
20.000 000MHz

Input to output propagation delay
with a 2.048 MHz reference clock

PD20

183

MCLKi =
20.000 000MHz

Input rise time (except MCLKi)

Input fall time (except MCLKi)

Delay between C1.5 and C2

D-20-15

Frame pulse F0o output pulse
width

W-F0o

244

Frame pulse F0o output rise time

R-F0o

Load = 85pF

Frame pulse F0o output fall time

F-F0o

Load = 85pF

Frame pulse FP8-STB output
pulse width

W-FP8STB

122

Frame pulse FP8-STB output rise
time

R-FP8STB

Load = 85pF

Frame pulse FP8-STB output fall
time

F-FP8STB

Load = 85pF

O
U

T
P

T
S

Frame pulse FP8-GCI output
pulse width

W-FP8GCI

122

Frame pulse FP8-GCI output rise
time

R-FP8GCI

Load = 85pF

Frame pulse FP8-GCI output fall
time

F-FP8GC

Load = 85pF

C1.5 clock period

P-C1.5

648

C1.5 clock output rise time

RC1.5

Load = 85pF

C1.5 clock output fall time

FC1.5

Load = 85pF

C1.5 clock output duty cycle

C3 clock period

P-C3

324

C3 clock output rise time

RC3

Load = 85pF

C3 clock output fall time

FC3

Load = 85pF

C3 clock output duty cycle

C2 clock period

P-C2

488

C2 clock output rise time

RC2

Load = 85pF

C2 clock output fall time

FC2

Load = 85pF

C2 clock output duty cycle

Part Number MT9041