2004 Microchip Technology Inc.

Preliminary

DS21801C-page 1

MCP2515

Features

· Implements CAN V2.0B at 1 Mb/s:

- 0 8 byte length in the data field

- Standard and extended data and remote

frames

· Receive buffers, masks and filters:

- Two receive buffers with prioritized message

storage

- Six 29-bit filters

- Two 29-bit masks

· Data byte filtering on the first two data bytes

(applies to standard data frames)

· Three transmit buffers with prioritizaton and abort

features.

· High-speed SPITM Interface (10 MHz):

- SPI modes 0,0 and 1,1

· One-shot mode ensures message transmission is

attempted only one time

· Clock out pin with programmable prescaler:

- Can be used as a clock source for other

device(s)

· Start-of-Frame (SOF) signal is available for

monitoring the SOF signal:

- Can be used for time-slot-based protocols

and/or bus diagnostics to detect early bus
degredation

· Interrupt output pin with selectable enables

· Buffer Full output pins configurable as:

- Interrupt output for each receive buffer

- General purpose output

· Request-to-Send (RTS) input pins individually

configurable as:

- Control pins to request transmission for each

transmit buffer

- General purpose inputs

· Low-power CMOS technology:

- Operates from 2.7V 5.5V

- 5 mA active current (typical)

- 1 µA standby current (typical) (Sleep mode)

· Temperature ranges supported:

- Industrial (I): -40°C to +85°C

- Extended (E): -40°C to +125°C

Description

Microchip Technology's MCP2515 is a stand-alone
Controller Area Network (CAN) controller that imple-
ments the CAN specification, version 2.0B. It is capable
of transmitting and receiving both standard and
extended data and remote frames. The MCP2515 has
two acceptance masks and six acceptance filters that
are used to filter out unwanted messages, thereby
reducing the host MCUs overhead. The MCP2515
interfaces with microcontrollers (MCUs) via an industry
standard Serial Peripheral Interface (SPI).

Package Types

TXCAN

RXCAN

RESET

515

SCK

INT

RX0BF

RX1BF

OSC2

OSC1

CLKOUT/SOF

TX2RTS

Vss

TX0RTS

TX1RTS

MCP

251

TXCAN

RXCAN

TX0RTS

OSC1

CLKOUT/SOF

OSC2

RESET

SCK
INT

RX0BF
RX1BF

TX1RTS

TX2RTS

13
12

1
2

3
4
5

7
8
9

20
19

18
17
16

18-Lead PDIP/SOIC

20-LEAD TSSOP

Stand-Alone CAN Controller With SPITM Interface

2004 Microchip Technology Inc.

Preliminary

DS21801C-page 3

MCP2515

1.0

DEVICE OVERVIEW

The MCP2515 is a stand-alone CAN controller
developed to simplify applications that require
interfacing with a CAN bus. A simple block diagram of
the MCP2515 is shown in Figure 1-1. The device
consists of three main blocks:

The CAN module, which includes the CAN
protocol engine, masks, filters, transmit and
receive buffers.

The control logic and registers that are used to
configure the device and its operation.

The SPI protocol block.

An example system implementation using the device is
shown in Figure 1-2.

1.1

CAN Module

The CAN module handles all functions for receiving
and transmitting messages on the CAN bus. Messages
are transmitted by first loading the appropriate
message buffer and control registers. Transmission is
initiated by using control register bits via the SPI
interface or by using the transmit enable pins. Status
and errors can be checked by reading the appropriate
registers. Any message detected on the CAN bus is
checked for errors and then matched against the user-
defined filters to see if it should be moved into one of
the two receive buffers.

1.2

Control Logic

The control logic block controls the setup and operation
of the MCP2515 by interfacing to the other blocks in
order to pass information and control.

Interrupt pins are provided to allow greater system
flexibility. There is one multi-purpose interrupt pin (as
well as specific interrupt pins) for each of the receive
registers that can be used to indicate a valid message
has been received and loaded into one of the receive
buffers. Use of the specific interrupt pins is optional.
The general purpose interrupt pin, as well as status
registers (accessed via the SPI interface), can also be
used to determine when a valid message has been
received.

Additionally, there are three pins available to initiate
immediate transmission of a message that has been
loaded into one of the three transmit registers. Use of
these pins is optional and initiating message
transmissions can also be accomplished by utilizing
control registers, accessed via the SPI interface.

1.3

SPI Protocol Block

The MCU interfaces to the device via the SPI interface.
Writing to, and reading from, all registers is
accomplished using standard SPI read and write
commands, in addition to specialized SPI commands.

FIGURE 1-1:

BLOCK DIAGRAM

SPITM

Interface

Logic

SPI
Bus

INT

CS
SCK

CAN

Protocol

Engine

RXCAN

TXCAN

Control Logic

RX0BF

RX1BF

TX0RTS

TX1RTS

TX2RTS

TX and RX Buffers

Masks and Filters

CAN Module

RESET

Timing

Generation

OSC1
OSC2

CLKOUT

Control

and

Interrupt

Registers

MCP2515

DS21801C-page 4

Preliminary

2004 Microchip Technology Inc.

FIGURE 1-2:

EXAMPLE SYSTEM IMPLEMENTATION

TABLE 1-1:

PINOUT DESCRIPTION

Name

PDIP/SOIC

Pin #

TSSOP

Pin #

I/O/P
Type

Description

Alternate Pin Function

TXCAN

Transmit output pin to CAN bus

RXCAN

Receive input pin from CAN bus

CLKOUT

Clock output pin with programmable
prescaler

Start-of-Frame signal

TX0RTS

Transmit buffer TXB0 request-to-send.
100 k

internal pull-up to V

General purpose digital input.
100 k

internal pull-up to V

TX1RTS

Transmit buffer TXB1 request-to-send.
100 k

internal pull-up to V

General purpose digital input.
100 k

internal pull-up to V

TX2RTS

Transmit buffer TXB2 request-to-send.
100 k

internal pull-up to V

General purpose digital input.
100 k

internal pull-up to V

OSC2

Oscillator output

OSC1

Oscillator input

External clock input

Ground reference for logic and I/O pins --

RX1BF

Receive buffer RXB1 interrupt pin or
general purpose digital output

General purpose digital output

RX0BF

Receive buffer RXB0 interrupt pin or
general purpose digital output

General purpose digital output

INT

Interrupt output pin

SCK

Clock input pin for SPITM interface

Data input pin for SPI interface

Data output pin for SPI interface

Chip select input pin for SPI interface

RESET

Active low device reset input

Positive supply for logic and I/O pins

6,15

No internal connection

Note:

Type Identification: I = Input; O = Output; P = Power

Node

Controller

MCP2515

XCVR

SPITM

CANH

CANL

Node

Controller

MCP2515

XCVR

SPI

Node

Controller

MCP2515

XCVR

SPI

2004 Microchip Technology Inc.

Preliminary

DS21801C-page 5

MCP2515

1.4

Transmit/Receive Buffers/Masks/
Filters

The MCP2515 has three transmit and two receive
buffers, two acceptance masks (one for each receive
buffer) and a total of six acceptance filters. Figure 1-3
shows a block diagram of these buffers and their
connection to the protocol engine.

FIGURE 1-3:

CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM

Acceptance Filter

RXF2

R
X
B
1

Identifier

Data Field

Identifier

Acceptance Mask

RXM1

Acceptance Filter

RXF3

Acceptance Filter

RXF4

Acceptance Filter

RXF5

M
A
B

Acceptance Filter

RXF0

Acceptance Filter

RXF1

R
X
B
0

TXRE

TXB2

TXE

AGE

Message

Queue

Control

Transmit Byte Sequencer

TXRE

TXB0

TXE

AGE

CRC<14:0>

Comparator

Receive<7:0>

Transmit<7:0>

Receive

Error

Transmit

Error

Protocol

REC

TEC

ErrPas

BusOff

Finite

State

Machine

Counter

Shift<14:0>

{Transmit<5:0>, Receive<8:0>}

Transmit

Logic

Bit

Timing

Logic

Configuration

Registers

Clock

Generator

PROTOCOL
ENGINE

BUFFERS

TXRE

TXB1

TXE

AGE

Acceptance Mask

RXM0

A
c
c
e
p
t

SOF

Part Number MCP2515

Document Outline