_______________General Description
The MAX9687 is a dual, ultra-fast ECL comparator
manufactured with a high-frequency bipolar process
(f
T
= 6GHz) capable of very short propagation delays.
This design maintains the excellent DC matching char-
acteristics normally found only in slower comparators.
The MAX9687 is pin-compatible with the AD9687 and
Am6687, but exceeds their AC characteristics.
The MAX9687 has differential inputs and complemen-
tary outputs that are fully compatible with ECL-logic lev-
els. Output current levels are capable of driving 50
terminated transmission lines. The ultra-fast operation
makes signal processing possible at frequencies in
excess of 600MHz.
A latch-enable (LE) function is provided to allow the
comparator to be used in a sample/hold or track/hold
mode. The latch-enable inputs are designed to be dri-
ven from the complementary outputs of a standard ECL
gate. When LE is high and
L
--
E
is low, the comparator
functions normally. When LE is forced low and
L
--
E
is
high, the comparator outputs are locked in the logical
states determined by the input conditions at the time of
the latch transition. If the latch-enable function is not
used on either of the two comparators, the appropriate
LE input must be connected to ground; the companion
L
--
E
input can be left open.
________________________Applications
High-Speed A/D Converters
High-Speed Line Receivers
Peak Detectors
Threshold Detectors
High-Speed Triggers
____________________________Features
o
1.4ns Propagation Delay
o
0.5ns Latch Setup Time
o
2.0ns Latch-Enable Pulse Width
o
+5V, -5.2V Power Supplies
o
Pin-Compatible with AD9687, Am6687, SP9687
o
Available in Commercial, Extended-Industrial,
and Military Temperature Ranges
o
Available in Narrow SO Package
______________Ordering Information
* Contact factory for availability of 20-pin PLCC.
** Contact factory for dice specifications.
MAX9687
Dual, Ultra-Fast ECL-Output Comparator
________________________________________________________________
Maxim Integrated Products
1
NONINVERTING
INPUT
RL
RL
LE LE
V
T
INVERTING
INPUT
NONINVERTING
INPUT
INVERTING
INPUT
Q OUT
Q OUT
RL
RL
LE LE
LATCH ENABLE
LATCH ENABLE
THE OUTPUTS ARE OPEN EMITTERS, REQUIRING EXTERNAL PULL-DOWN
RESISTORS. THESE RESISTORS MAY BE IN THE RANGE OF 50
200
CONNECTED TO -2.0V, OR 240
2000
CONNECTED TO -5.2V.
________________Functional Diagram
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q OUT
Q OUT
GND
LEB
LEB
V+
INB-
INB+
Q OUT
Q OUT
GND
LEA
LEA
V-
INA-
INA+
TOP VIEW
DIP/SO
A
B
___________________Pin Configuration
Call toll free 1-800-998-8800 for free samples or literature.
19-2400; Rev 1; 7/93
PART
TEMP. RANGE
PIN-PACKAGE*
MAX9687CPE
0°C to +70°C
16 Plastic DIP
MAX9687CSE
0°C to +70°C
16 Narrow SO
MAX9687CJE
0°C to +70°C
16 CERDIP
MAX9687C/D
0°C to +70°C
Dice**
MAX9687EPE
-40°C to +85°C
16 Plastic DIP
MAX9687ESE
-40°C to +85°C
16 Narrow SO
MAX9687MJE
-55°C to +125°C
16 CERDIP
MAX9687
Dual, Ultra-Fast ECL-Output Comparator
2
_______________________________________________________________________________________
Supply Voltages.....................................................................±6V
Output Short-Circuit Duration (Note 1) ..........................Indefinite
Input Voltages........................................................................±5V
Differential Input Voltages .....................................................3.5V
Output Current ....................................................................30mA
Continuous Power Dissipation (T
A
= +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C) ...........842mW
Narrow SO (derate 8.70mW/°C above +70°C) .............696mW
CERDIP (derate 10.00mW/°C above +70°C) ................800mW
Operating Temperature Ranges
MAX9687C_ E .....................................................0°C to +70°C
MAX9687E_ E ..................................................-40°C to +85°C
MAX9687MJE ................................................-55°C to +125°C
Storage Temperature Range .............................-55°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Common-Mode
Rejection Ratio
CMRR
80
dB
Input Voltage Range
V
CM
-2.5
+2.5
V
Input Offset Current
I
OS
5
µA
Temperature Coefficient
V
OS/
T
10
µV/°C
Power-Supply Rejection
Ratio
PSRR
60
dB
Input Resistance
R
IN
60
k
Input Capacitance
C
IN
3
pF
-5
5
Input Offset Voltage
(Note 2)
V
OS
-7
7
mV
(Note 2)
(Note 2)
T
A
= +25°C
(Note 2)
T
A
= +25°C
PARAMETER
SYMBOL
MAX9687C/E
MIN
TYP
MAX
UNITS
CONDITIONS
R
S
= 100
T
A
= T
MIN
to T
MAX
Input Bias Current
I
B
10
20
µA
T
A
= +25°C
80
-2.5
+2.5
5
15
60
60
3
10
20
-5
5
-8
8
MAX9687M
MIN
TYP
MAX
T
A
= T
MIN
to T
MAX
T
A
= T
MIN
to T
MAX
-1.16
-0.89
-1.05
-0.87
-0.88
-0.69
-0.96
-0.81
-0.89
-0.70
-0.96
-0.81
MAX9687C,
MAX9687M
-1.14
-0.88
-0.88
-0.70
T
A
= T
MIN
T
A
= T
MAX
T
A
= +25°C
T
A
= T
MIN
T
A
= T
MAX
Logic Output
High Voltage
V
OH
-0.96
-0.81
V
MAX9687E
T
A
= +25°C
-1.90
-1.65
-1.82
-1.55
-1.89
-1.65
-1.85
-1.65
-1.83
-1.57
-1.85
-1.65
MAX9687C,
MAX9687M
-1.90
-1.65
-1.83
-1.57
Logic Output
Low Voltage
V
OL
-1.85
-1.65
V
MAX9687E
T
A
= T
MIN
T
A
= T
MAX
T
A
= +25°C
T
A
= T
MIN
T
A
= T
MAX
T
A
= +25°C
8
30
12
40
30
46
30
46
T
A
= +25°C
mA
52
50
T
A
= T
MIN
to T
MAX
I
CC
Positive Supply Current
54
68
54
68
T
A
= +25°C
mA
74
72
T
A
= T
MIN
to T
MAX
I
EE
Negative Supply Current
ABSOLUTE MAXIMUM RATINGS
Note 1:
Continuous short-circuit protection is allowed on one comparator at a time up to case temperatures of +85°C and ambient
temperatures of +30°C.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
S
= ±15V, V
CM
= 0V, T
A
= +25°C, unless otherwise noted.)
MAX9687
Dual, Ultra-Fast ECL-Output Comparator
_______________________________________________________________________________________
3
Note 2:
Not tested, guaranteed by design.
Note 3:
VIN = 100mV, VOD = 10mV.
Figure 2. As a high-speed receiver, the MAX9687 is capable of
processing signals in excess of 600MHz. Figure 2 is a 100MHz
example with an input signal level of 14mV
RMS.
Figure 1. High-speed receiver application with 50
input and out-
put termination. With this configuration, in which a ground plane and
microstrip PC board was used, the minimum slew rate for clean out-
put switching is 1.6V/µs. For sine-wave inputs, this implies a mini-
mum signal size of 360mV
RMS
at 500MHz and 90mV at 2MHz.
0V
-0.9V
-1.7V
OUTPUT
INPUT
OUTPUT
500mV/div
INPUT
20mV/div
2ns/div
V
IN
-2V
50
C
f
R
f
50
50
50
LE
SWITCHING CHARACTERISTICS
(V
S
= ±5V, T
A
= +25°C, unless otherwise noted.)
1.4
1.9
PARAMETER
SYMBOL
MAX9687C/E
MIN
TYP
MAX
UNITS
T
A
= +25°C
CONDITIONS
E RMS =
Slew Rate
2 f
2
T
A
= 0°C to +70°C
1.6
2.2
1.4
1.9
MAX9687M
MIN
TYP
MAX
1.4
1.9
1.7
2.6
T
A
= +25°C
1.4
1.9
Input to Output High
(Notes 2, 3)
t
pd+
ns
T
A
= -55°C to +125°C
1.9
2.6
Input to Output Low
(Notes 2, 3)
1.3
1.8
T
A
= 0°C to +70°C
t
pd-
1.4
2.0
1.3
1.8
T
A
= -55°C to +125°C
ns
T
A
= +25°C
1.6
2.2
T
A
= 0°C to +70°C
1.3
1.8
1.5
2.0
1.7
2.6
Latch-Enable to Output Low
(Notes 2, 3)
t
pd-
(E)
T
A
= -55°C to +125°C
ns
1.6
1.9
T
A
= +25°C
1.4
1.8
T
A
= 0°C to +70°C
Latch-Enable to Output High
(Notes 2, 3)
t
pd+
(E)
ns
T
A
= -55°C to +125°C
3.0
2.0
Latch-Enable Pulse Width (Note 2)
0.5
1.0
t
pw
(E)
Minimum Setup Time
t
s
0.5
1.0
3.0
2.0
0.5
1.0
Minimum Hold Time
t
h
0.5
1.0
ns
__________Applications Information
Layout
Because of the MAX9687's large gain-bandwidth charac-
teristic, special precautions need to be taken if its high-
speed capabilities are to be used. A PC board with a
ground plane is mandatory. Mount all decoupling capaci-
tors as close to the power-supply pins as possible, and
process the ECL outputs in microstrip fashion, consistent
with the load termination of 50
to 120
. For low-imped-
ance applications, microstrip layout at the input may also
be helpful. Pay close attention to the bandwidth of the
decoupling and terminating components. Chip compo-
nents can be used to minimize lead inductance.
Input Slew-Rate Requirement
As with all high-speed comparators, the high gain-
bandwidth product of these devices creates oscillation
problems when the input traverses through the linear
region. For clean switching without oscillation or steps
in the output waveform, the input must meet certain
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
4
___________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1993 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX9687
Dual, Ultra-Fast ECL-Output Comparator
minimum slew-rate requirements. The tendency of the
part to oscillate is a function of the layout and source
impedance of the circuit employed. Both poor layout
and larger source impedance will increase the mini-
mum slew-rate specification.
In many applications, the addition of regenerative feed-
back will assist the input signal through the linear
region, which will lower the minimum slew-rate require-
ment considerably. For example, with the addition of
positive feedback components Rf = 1k
and
Cf = 10pF, the minimum slew-rate requirement can be
reduced by a factor of four.
____________________Timing Diagram
The timing diagram (Figure 3) illustrates the series of
events that complete the compare function, under
worst-case conditions.
The top line of the diagram illustrates two latch-enable
(LE) pulses; each pulse is high for the compare func-
tion and low for the latch function. The first pulse
demonstrates the compare function in which part of the
input action takes place during the compare mode.
The second pulse demonstrates a compare-function
interval during which there is no change in the input.
The leading edge of the input signal (illustrated as a
large-amplitude, small-overdrive pulse) switches the
comparator after time interval t
pd
. Outputs Q and
Q
are similar in timing. The input signal must occur at time
t
s
before the latch falling edge and, to be acquired,
must be maintained for time t
h
after the edge. After t
h
,
the output is no longer affected by the input status until
the latch is again strobed. A minimum latch pulse width
of t
pw
(E) is needed for the strobe operation, and the
output transitions occur after a time t
pd
(E).
Definition of Terms
V
OS
Input Offset Voltage--The voltage required
between the input terminals to obtain 0V differ-
ential at the output.
V
IN
Input Voltage Pulse Amplitude
V
OD
Input Voltage Overdrive
t
pd+
Input to Output High Delay--The propagation
delay measured from the time the input signal
crosses the input offset voltage to the 50% point
of an output low-to-high transition.
t
pd-
Input to Output Low Delay--The propagation
delay measured from the time the input signal
crosses the input offset voltage to the 50% point
of an output high-to-low transition.
t
pd+
(E) Latch-Enable to Output High Delay--The propa-
gation delay measured from the 50% point of the
latch-enable signal low-to-high transition to the
50% point of an output low-to-high transition.
t
pd-
(E)
Latch-Enable to Output Low Delay--The propa-
gation delay measured from the 50% point of the
latch-enable signal low-to-high transition to the
50% point of an output high-to-low transition.
t
pw
(E)
Minimum Latch-Enable Pulse Width--The mini-
mum time the latch-enable signal must be high
to acquire and hold an input signal.
t
s
Minimum Setup Time--The minimum time before
the negative transition of the latch-enable pulse
that an input signal must be present to be
acquired and held at the outputs.
t
h
Minimum Hold Time--The minimum time after
the negative transition of the latch-enable signal
that an input signal must remain unchanged to
be acquired and held at the outputs.
Figure 3. Timing Diagram
LATCH
ENABLE
DIFFERENTIAL
INPUT
VOLTAGE
Q
Q
LATCH
COMPARE
t
s
th
V
OD
V
IN
t
pd
(E)
V
OS
50%
50%
50%
t
pw
(E)
t
pd
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