General Description
The MAX3971 is a compact, low-power, 10.3Gbps limit-
ing amplifier. It accepts signals over a wide range of input
voltage levels and provides constant-level output volt-
ages with controlled edge speeds. It functions as a data
quantizer. The output of the amplifier is a 250mV
P-P
differ-
ential CML signal with a 100
differential termination.
The MAX3971 is designed to work with the MAX3970, a
10.3Gbps transimpedance amplifier (TIA). The limiting
amplifier operates on a single +3.3V supply and con-
sumes only 155mW. The part functions over the 0°C to
+85°C temperature range. It also has a disable function
that allows the outputs to be squelched if required by
the application.
The MAX3971 is offered in die form and in a compact
4mm x 4mm, 20-pin QFN plastic package.
Applications
10-Gigabit Ethernet Optical Receivers
VSR OC-192 Receivers
10-Gigabit Fibre Channel Receivers
____________________________Features
o Single +3.3V Power Supply
o 155mW Power Consumption
o 9.5mV
P-P
Input Sensitivity
o 800mV
P-P
Input Overload
o 3.4ps
P-P
Deterministic Jitter
o Dice and 4mm x 4mm QFN Packages
o Output Disable Feature
MAX3971
+3.3V, 10.3Gbps Limiting Amplifier
________________________________________________________________ Maxim Integrated Products
1
MAX3971
MAX3970
TIA
100
IN+
GNDIN-
GNDIN+
IN-
SUPPLY FILTER
V
CC
1 V
CC
2 V
CC
3
OUT+
OUT-
CZ-
CZ+
0.1
µF
0.1
µF
0.1
µF
0.1
µF
0.1
µF
DISABLE
100
+3.3V
+3.3V
Typical Application Circuit
*Exposed pad
**Dice are designed to operate over a 0°C to +110°C junction
temperature (T
J
) range, but are tested and guaranteed at
T
A
= +25°C.
Ordering Information
PART
TEMP. RANGE
PIN-PACKAGE
MAX3971UGP
0°C to +85°C
20 QFN*
MAX3971U/D
0°C to +85°C
Dice**
19-2086; Rev 1; 12/02
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Pin Configuration appears at end of data sheet.
MAX3971
+3.3V, 10.3Gbps Limiting Amplifier
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC1
, V
CC2
, V
CC3
.......................-0.5V to +0.5V
Voltage at IN+, IN-, DISABLE,
CZ+, CZ-, OUT+, OUT-........................+0.5V to (V
CC
+ 0.5V)
Differential Voltage Between CZ+ and CZ- ...........................±1V
Differential Voltage Between IN+ and IN-...........................±2.5V
Continuous Power Dissipation (T
A
= +85°C)
20-Lead QFN (derate 20mW/°C above +85°C) ..............1.3W
Operating Ambient Temperature Range .............-40°C to +85°C
Storage Temperature Range .............................-55°C to +150°C
Die Attach Temperature...................................................+400°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T
A
= 0°C to +85°C. Typical values are at V
CC
= +3.3V, output load = 50
to V
CC
, T
A
= +25°C, unless other-
wise noted. Data mark density is 50%.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Current
I
CC
47
85
mA
Small-Signal Bandwidth
BW
10
GHz
Low-Frequency Cutoff
CZ = 0.1µF
40
160
kHz
Data Rate
10
Gbps
10mV
P-P
input, K28.5 pattern at 10.3Gbps
(Note 1)
8
20mV
P-P
input, K28.5 pattern at 10.3Gbps
(Note 1)
4.7
14
Deterministic Jitter
800mV
P-P
input, K28.5 pattern at 10.3Gbps
(Note 1)
3.4
7
ps
P-P
Random Jitter
20mV
P-P
to 800mV
P-P
(Note 2)
0.7
1.0
ps
RMS
Transition Time, Output
t
r
, t
f
20% to 80%, OUT+, OUT-
20
30
ps
Input Sensitivity
V
IN-min
BER = 1E-12, 2
23
- 1PRBS, 10.3Gbps
9.5
mV
P-P
Input Overload
V
IN-max
800
mV
P-P
Data Input Resistance
R
IN
Single-ended
42
52
58
V
OD1
DISABLE high
1
50
Differential Data
Output-Voltage Swing
V
OD2
DISABLE low
190
250
400
mV
P-P
Data Output Common-Mode
Voltage
V
CM
V
CC
-
0.75
V
Output Resistance
R
OUT
Single-ended
42
52
58
Data Output Offset when
DISABLE is High
75
mV
P-P
DISABLE Input Current
High = V
CC
, low = GND
0.05
1
mA
DISABLE Input High Voltage
2.8
V
DISABLE Input Low Voltage
1.4
V
Note 1:
Deterministic jitter is measured with a K28.5 pattern (0011 1110 1011 0000 0101). It is the peak-to-peak deviation from the
ideal time crossings, measured at the zero-level crossings of the differential output.
Note 2:
Random jitter is measured with the minimum input signal applied. To achieve a bit error rate of 10
-12
, the peak-to-peak ran-
dom jitter is 14.1 times the RMS random jitter.
MAX3971
+3.3V, 10.3Gbps Limiting Amplifier
_______________________________________________________________________________________
3
40
45
50
55
60
65
70
0
20
10
30
40
50
60
70
80
90
SUPPLY CURRENT vs. TEMPERATURE
MAX3971 toc01
TEMPERATURE (
°C)
SUPPLY CURRENT (mA)
20ps/div
OUTPUT EYE DIAGRAM
(INPUT SIGNAL = 800mV
P-P
AT 10.3Gbps)
50mV/div
MAX3971 toc02
20ps/div
OUTPUT EYE DIAGRAM
(INPUT SIGNAL = 9mV
P-P
AT 10.3Gbps)
50mV/div
MAX3971 toc03
0
30
40
10
20
50
60
70
80
90
TRANSITION TIME vs. TEMPERATURE
(20% to 80%)
MAX3971 toc04
TEMPERATURE (
°C)
TIME (ps)
19
20
21
22
(1)
(2)
(1) V
CC
= +3.0V, INPUT = 800mV
P-P
(2) V
CC
= +3.6V, INPUT = 800mV
P-P
7
8
9
10
11
10
30
50
70
20
40
60
80
90
INPUT SENSITIVITY vs. TEMPERATURE
(FOR BIT-ERROR RATIO OF 1E-12)
MAX3971 toc07
TEMPERATURE (
°C)
SIGNAL INPUT LEVEL (mV
P-P
)
60
50
40
30
20
10
70
0
80
90
DETERMINISTIC JITTER vs. TEMPERATURE
(800mV
P-P
INPUT K28.5 PATTERN AT 10.3Gbps)
MAX3971 toc05
TEMPERATURE (
°C)
JITTER (ps
P-P
)
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
2.0
4.8
4.6
4.4
4.2
5.0
4.0
(1)
(2)
(1) V
CC
= +3.0V
(2) V
CC
= +3.6V
60
50
40
30
20
10
70
0
80
90
DETERMINISTIC JITTER vs. TEMPERATURE
(10mV
P-P
INPUT K28.5 PATTERN AT 10.3Gbps)
MAX3971 toc06
TEMPERATURE (
°C)
JITTER (ps
P-P
)
5.2
5.4
5.6
5.8
6.0
6.2
6.4
6.6
6.8
5.0
7.8
7.6
7.4
7.2
8.0
7.0
(1)
(2)
(1) V
CC
= +3.0V
(2) V
CC
= +3.6V
-50
-20
-30
-40
-10
0
10
100
4100
2100
6100
8100
10,100
INPUT RETURN (S11)
INPUT SIGNAL = -20dBm
MAX3971 toc08
FREQUENCY (MHz)
GAIN (dB)
-50
-20
-30
-40
-10
0
10
100
4100
2100
6100
8100
10,100
OUTPUT RETURN (S22)
INPUT SIGNAL = -20dBm
MAX3971 toc09
FREQUENCY (MHz)
GAIN (dB)
Typical Operating Characteristics
(V
CC
= +3.3V, output load = 50
to V
CC
, T
A
= +25°C, unless otherwise noted.)
MAX3971
+3.3V, 10.3Gbps Limiting Amplifier
4
_______________________________________________________________________________________
Typical Operating Characteristics (continued)
(V
CC
= +3.3V, output load = 50
to V
CC
, T
A
= +25°C, unless otherwise noted.)
0
20
10
40
30
50
60
1
10
100
1000
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
MAX3971 toc10
FREQUENCY (MHz)
PSRR (dB)
0
20
10
40
30
50
60
1
100
10
1000
10,000
COMMON-MODE REJECTION RATIO
vs. FREQUENCY
MAX3971 toc11
FREQUENCY (MHz)
CMMR (dB)
PIN
NAME
FUNCTION
1
GNDIN+
Input Ground for Shielding Input Signal IN+. Not connected internally.
2
IN+
Noninverting Input Signal
3
IN-
Inverting Input Signal
4
GNDIN-
Input Ground for Shielding Input Signal IN-. Not connected internally.
5, 7, 9, 10
N.C.
No Connection. Leave unconnected.
6, 8, 11
GND
Ground
12, 15
V
CC
3
Output Circuitry Power Supply
13
OUT-
Inverting Output of Amplifier
14
OUT+
Noninverting Output of Amplifier
16
DISABLE
When High, the Outputs are Disabled
17
V
CC
2
Power Supply to Circuitry Other than Input and Output Circuits
18
CZ+
Filter Capacitor for Offset Correction. Attach other side of a capacitor to pin 19. See the Detailed
Description.
19
CZ-
See pin 18.
20
V
CC1
Input Circuitry Power Supply
EP
Exposed
Pad
Exposed Pad. Must be soldered to supply ground for proper electrical and thermal operation.
Pin Description
Detailed Description and
Applications Information
Figure 1 is a functional diagram of the MAX3971 limit-
ing amplifier.The signal path consists of an input buffer
followed by a gain stage and output amplifier. A feed-
back loop provides offset correction by driving the
average value of the differential output to zero.
Gain Stage and Offset Correction
The limiting amplifier provides approximately 50dB
gain. This large gain makes the amplifier susceptible to
small DC offsets, which cause deterministic
jitter. A low-frequency loop is integrated into the limiting
amplifier to reduce output offset, typically to less than
2mV.
The external capacitor CZ is required to set the low-fre-
quency cutoff for the offset correction loop and for sta-
bility. The time constant of the loop is set by the
product of an equivalent 20k
on-chip resistor and the
value of the off-chip capacitor, CZ. For stable opera-
tion, the minimum value of CZ is 0.01µF. To minimize
pattern-dependent jitter, CZ should be as large as pos-
sible. For 10-Gigabit Ethernet applications, the typical
value of CZ is 0.1µF. Keep CZ as close to the package
as possible.
CML Input Circuit
The input buffer is designed to accept CML input sig-
nals such as the output from the MAX3970 transimped-
ance amplifier. An equivalent circuit for the input is
shown in Figure 2. DC-coupling the inputs is not recom-
mended because doing so prevents the part's offset
correction circuitry from working properly. Thus, AC-
coupling capacitors are required on the input.
CML Output Circuit
An equivalent circuit for the output network is shown in
Figure 3. It consists of two 50
resistors connected to
V
CC
driven by the collectors of an output differential
transistor pair (Q1 and Q2). The differential output sig-
nals are clamped by transistors Q3 and Q4 when the
DISABLE input is high.
Disable Function
A logic signal can be applied to the DISABLE pin to
squelch the output signal. When the output is disabled,
an offset is added to the output, preventing the follow-
ing stage from oscillating (if DC-coupled).
MAX3971
+3.3V, 10.3Gbps Limiting Amplifier
_______________________________________________________________________________________
5
MAX3971
CZ-
CZ+
LOWPASS
FILTER
CZ
OFFSET
CORRECTION
AMP
INPUT
AMPLIFIER
GAIN
50dB
OUTPUT
AMPLIFIER
OUT+
OUT-
IN+
GNDIN+
GNDIN-
IN-
DISABLE
Figure 1. Functional Diagram
V
CC
1
50
50
IN+
GNDIN+
GNDIN-
IN-
ESD
STRUCTURES
Figure 2. CML Input Equivalent Circuit
V
CC
3
50
50
Q1
Q2
Q3
Q4
OUT+
OUT-
DISABLE
DATA
ESD
STRUCTURES
Figure 3. CML Input Equivalent Circuit Showing Clamping
Circuit for Squelching the Output Signal
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