General Description
The MAX3881 deserializer with clock recovery is ideal
for converting 2.488Gbps serial data to 16-bit-wide,
155Mbps parallel data for SDH/SONET applications.
Operating from a single +3.3V supply, this device
accepts high-speed serial-data inputs and delivers sin-
gle-ended PECL parallel data outputs and a differential
PECL parallel clock output for interfacing with digital
circuitry.
The MAX3881 includes a low-power clock recovery and
data retiming function for 2.488Gbps applications. The
fully integrated phase-locked loop (PLL) recovers a
synchronous clock signal from the serial NRZ data
input; the signal is then retimed by the recovered clock.
The MAX3881's jitter performance exceeds all
SDH/SONET specifications. An additional 2.488Gbps
serial input is available for system loopback diagnostic
testing. The device also includes a TTL-compatible
loss-of-lock (LOL) monitor.
The MAX3881 is available in the extended temperature
range (-40°C to +85°C) in a 64-pin TQFP-EP package.
Applications
2.488Gbps SDH/SONET Transmission Systems
Add/Drop Multiplexers
Digital Cross-Connects
Features
o Single +3.3V Supply
o 530mW Operating Power
o Fully Integrated Clock Recovery and Data
Retiming
o Exceeds ANSI, ITU, and Bellcore Specifications
o Additional High-Speed Input Facilitates System
Loopback Diagnostic Testing
o 2.488Gbps Serial to 155Mbps Parallel Conversion
o Differential PECL Clock Output
o Single-Ended PECL Data Outputs
o Tolerates >2000 Consecutive Identical Digits
o Loss-of-Lock Indicator
MAX3881
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
________________________________________________________________ Maxim Integrated Products
1
19-1996; Rev 1; 12/01
PART
MAX3881ECB
-40°C to +85°C
TEMP. RANGE
PIN-PACKAGE
64 TQFP-EP*
Ordering Information
*Exposed pad
EVALUATION KIT
AVAILABLE
Pin Configuration
V
CC
PD13
V
CC
GND
V
CC
PD14
GND
V
CC
PD11
V
CC
PD12
V
CC
PD15
GND
LOL
GND
SLBI+
V
CC
SDI-
SDI+
V
CC
PHADJ-
GND
GND
SIS
V
CC
SLBI-
PHADJ+
V
CC
FIL-
FIL+
GND
PCLK+
PCLK-
V
CC
PD0
V
CC
PD1
V
CC
GND
V
CC
PD2
V
CC
PD3
V
CC
PD4
V
CC
GND
PD10
TOP VIEW
V
CC
PD9
V
CC
PD8
V
CC
GND
V
CC
PD7
V
CC
PD6
V
CC
PD5
V
CC
GND
V
CC
TQFP-EP*
58
59
60
61
62
54
55
56
57
63
38
39
40
41
42
43
44
45
46
47
52
53
49
50
51
33
34
35
36
37
48
64
23
22
21
20
19
27
26
25
24
18
29
28
32
31
30
17
11
10
9
8
7
6
5
4
3
2
16
15
14
13
12
1
MAX3881
*EXPOSED PAD IS CONNECTED TO GND.
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Typical Application Circuit appears at end of data sheet.
MAX3881
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, PECL loads = 50
to (V
CC
- 2V), T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at
V
CC
= +3.3V, T
A
= +25°C.)
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Positive Supply Voltage (V
CC
)...............................-0.5V to +7.0V
Input Voltage Level (SDI+, SDI-,
SLBI+, SLBI-) ...............................(V
CC
- 0.5V) to (V
CC
+ 0.5V)
Input Current Level (SDI+, SDI-, SLBI+, SLBI-)................±10mA
Voltage at LOL, SIS, PHADJ+, PHADJ-,
FIL+, FIL- .................................................-0.5V to (V
CC
+ 0.5V)
PECL Output Current ..........................................................50mA
Continuous Power Dissipation (T
A
= +85°C)
64-Pin TQFP (derate 33.3mW/°C above +85°C)............1.44W
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Figure 1
Excluding PECL outputs
Figure 2
T
A
= 0°C to +85°C
CONDITIONS
mVp-p
50
800
V
ID
Differential Input Voltage
mA
160
240
I
CC
Supply Current
V
V
CC
- 0.4
V
CC
+ 0.2
V
IS
Single-Ended Input Voltage
50
R
IN
Input Termination to V
CC
V
CC
- V
CC
-
1.025
0.88
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
V
0.8
V
IL
Input Low Voltage
V
2.0
V
IH
Input High Voltage
I
OH
40µA
V
2.4
V
CC
V
OH
Output High Voltage
µA
-10
+10
Input Current
I
OL
1mA
V
0.4
V
OL
Output Low Voltage
T
A
= -40°C to 0°C
V
V
CC
- V
CC
-
1.085
0.88
V
OH
PECL Output High Voltage
T
A
= 0°C to +85°C
V
CC
- V
CC
-
1.81
1.62
T
A
= -40°C to 0°C
V
V
CC
- V
CC
-
1.83
1.555
V
OL
PECL Output Low Voltage
SERIAL DATA INPUTS (SDI±, SLBI±)
PECL OUTPUTS (PD_, PCLK±)
TTL INPUTS AND OUTPUTS (SIS, LOL)
MAX3881
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
_______________________________________________________________________________________
3
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, PECL loads = 50
to (V
CC
- 2V), T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at
V
CC
= +3.3V, T
A
= +25°C.) (Note 1)
Note 1: AC characteristics are guaranteed by design and characterization.
Note 2: At jitter frequencies <70kHz, the jitter tolerance of the MAX3881 outperforms the ITU/Bellcore specifications.
Figure 2
100kHz to 2.5GHz
f = 10MHz
f = 70kHz (Note 2)
f = 100kHz
f = 1MHz
2.5GHz to 4.0GHz
CONDITIONS
dB
-11
Input Return Loss (SDI±, SLBI±)
ps
200
450
900
t
CLK-Q
Parallel Clock-to-Data Output
Delay
Mbps
155.52
Gbps
2.488
SDI
Serial Data Rate
Parallel Output Data Rate
-18
Bits
>2,000
Tolerated Consecutive Identical
Digits
UIp-p
0.28
0.46
Jitter Tolerance
2.31
3.3
1.74
2.41
0.38
0.57
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
SDI+
SDI-
V
ID
(SDI+) - (SDI-)
50mVp-p MIN
800mVp-p MAX
25mV MIN
400mV MAX
Figure 1. Input Amplitude
PCLK
PD0PD15
t
CLK-Q
Figure 2. Timing Parameters
20% to 80%
Output Edge Speed
800
t
R
, t
F
ps
MAX3881
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
4
_______________________________________________________________________________________
1
0.1
10
100
1000
JITTER TOLERANCE vs. INPUT VOLTAGE
0.3
0.2
MAX3881 toc04
INPUT VOLTAGE (mVp-p)
JITTER TOLERNCE (UIp-p)
0.5
0.4
0.7
0.8
0.6
0.9
0
SONET SPEC
JITTER FREQUENCY = 5MHz
JITTER FREQUENCY = 1MHz
10
-10
10
-8
10
-9
10
-6
10
-7
10
-4
10
-5
10
-3
8.0
8.5
9.0
9.5
10
BIT ERROR RATIO vs. INPUT VOLTAGE
MAX3881-05
INPUT VOLTAGE (mVp-p)
BIT ERROR RATIO
200
300
400
600
500
700
-50
0
-25
25
50
75
100
PARALLEL CLOCK TO DATA OUTPUT
PROPAGATION DELAY vs. TEMPERATURE
MAX3881-06
TEMPERATURE (°C)
PCLK TO DATA OUTPUT PROPAGATION DELAY (ps)
Typical Operating Characteristics
(V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.)
1.64ns/div
DATA
CLOCK
RECOVERED DATA AND CLOCK
MAX3881-01
2
23
- 1 PATTERN
140
150
160
170
180
190
200
-50
-25
0
25
50
75
100
SUPPLY CURRENT vs. TEMPERATURE
MAX3881-02
TEMPERATURE (
°C)
SUPPLY CURRENT (mA)
V
CC
= +3.6V
V
CC
= +3.0V
10.0
0.1
1,000
10,000
1.0
JITTER FREQUENCY (kHz)
INPUT JITTER (UIp-p)
100
10
JITTER TOLERANCE
MAX3881 toc03
C
F
= 0.1
µF
C
F
= 1.0
µF
MAX3881
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
_______________________________________________________________________________________
5
NAME
FUNCTION
1, 15, 16, 17,
25, 33, 41,
49, 57, 62,
64
GND
Ground
PIN
Pin Description
2
FIL+
Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
3
FIL-
Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
4, 7, 10, 13,
20, 22, 24,
26, 28, 30,
32, 34, 36,
38, 40, 42,
44, 46, 48,
50, 52, 54,
56, 58, 60
V
CC
+3.3V Supply Voltage
5
PHADJ+
Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to V
CC
if not
used.
6
PHADJ-
Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to V
CC
if not
used.
8
SDI+
Positive Serial Data Input. 2.488Gbps data stream.
9
SDI-
Negative Serial Data Input. 2.488Gbps data stream.
11
SLBI+
Positive System Loopback Input. 2.488Gbps data stream.
12
SLBI-
Negative System Loopback Input. 2.488Gbps data stream.
14
SIS
Signal Input Selection. TTL low for normal data input (SDI). TTL high for system loopback input
(SLBI).
18
PCLK+
Positive Parallel Clock PECL Output
19
PCLK-
Negative Parallel Clock PECL Output
21, 23, 27,
29, 31, 35,
37, 39, 43,
45, 47, 51,
53, 55, 59, 61
PD0 to PD15
Parallel Data Single-Ended PECL Outputs. Data is updated on the negative transition of the PCLK
signal (Figure 2).
63
LOL
Loss-of-Lock Output. PLL loss-of-lock monitor, TTL active low (internal 10k
pullup resistor).
The LOL monitor is valid only when a data stream is present on the inputs to the MAX3881.
EP
Exposed Pad
Ground. This must be soldered to a circuit board for proper electrical and thermal performance
(see Package Information).
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