_______________General Description
The MAX199 multi-range, 12-bit data-acquisition system
(DAS) requires only a single +5V supply for operation,
and converts analog signals up to ±4V at its inputs. This
system provides eight analog input channels that are
independently software programmable for a variety of
ranges: ±V
REF
, ±V
REF/2
, 0V to V
REF
, or 0V to V
REF/2
.
This increases effective dynamic range to 14 bits, and
provides the user flexibility to interface 4mA-to-20mA,
±12V, and ±15V powered sensors to a single +5V sys-
tem. In addition, the converter is fault-protected to
±16.5V; a fault condition on any channel will
not
affect
the conversion result of the selected channel. Other fea-
tures include a 5MHz bandwidth track/hold, 100ksps
throughput rate, internal/external clock, internal/external
acquisition control, 8+4 parallel interface, and operation
with an internal 4.096V or external reference.
A hardware SHDN pin and two programmable power-
down modes (STBYPD, FULLPD) provide low-current
shutdown between conversions. In STBYPD mode, the
reference buffer remains active, eliminating start-up
delays.
The MAX199 employs a standard microprocessor (µP)
interface. Its three-state data I/O interface is configured
to operate with 8-bit data buses, and data-access and
bus-release timing specifications are compatible with
most popular µPs. All logic inputs and outputs are
TTL/CMOS compatible.
The MAX199 is available in 28-pin DIP, wide SO, SSOP,
and ceramic SB packages.
For a different combination of input ranges (±10V, ±5V,
0V to 10V, 0V to 5V), see the MAX197 data sheet. For 12-
bit bus interfaces, see the MAX196/MAX198 data sheet.
________________________Applications
Industrial-Control Systems
Robotics
Data-Acquisition Systems
Automatic Testing Systems
Medical Instruments
Telecommunications
____________________________Features
o
12-Bit Resolution, 1/2LSB Linearity
o
Single +5V Operation
o
Software-Selectable Input Ranges:
±V
REF
, ±V
REF/2
, 0V to V
REF
, 0V to V
REF/2
o
Internal 4.096V or External Reference
o
Fault-Protected Input Multiplexer (±16.5V)
o
8 Analog Input Channels
o
6µs Conversion Time, 100ksps Sampling Rate
o
Internal or External Acquisition Control
o
Two Power-Down Modes
o
Internal or External Clock
MAX199
Multi-Range (±4V, ±2V, +4V, +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface
________________________________________________________________
Maxim Integrated Products
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DGND
V
DD
REF
REFADJ
INT
CH7
AGND
CH6
CH5
CH4
CH3
CH2
CH1
CH0
D0/D8
D1/D9
D2/D10
D3/D11
D4
D5
D6
D7
SHDN
HBEN
RD
WR
CS
CLK
DIP/SO/SSOP/Ceramic SB
TOP VIEW
MAX199
__________________Pin Configuration
Call toll free 1-800-722-8266 for free samples or literature.
19-0401; Rev 0; 6/95
PART
MAX199ACNI
MAX199BCNI
MAX199ACWI
0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP. RANGE
PIN-PACKAGE
28 Narrow Plastic DIP
28 Narrow Plastic DIP
28 Wide SO
______________Ordering Information
MAX199BCWI
0°C to +70°C
28 Wide SO
MAX199ACAI
0°C to +70°C
28 SSOP
MAX199BCAI
0°C to +70°C
28 SSOP
MAX199BC/D
0°C to +70°C
Dice*
Functional Diagram appears at end of data sheet.
Ordering Information continued at end of data sheet.
*Dice are specified at T
A
= +25°C, DC parameters only.
MAX199
Multi-Range (±4V, ±2V, +4V, +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V
DD
= 5V ±5%; unipolar/bipolar range; external reference mode, V
REF
= 4.096V; 4.7µF at REF pin; external clock, f
CLK
= 2.0MHz
with 50% duty cycle; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
DD
to AGND............................................................-0.3V to +7V
AGND to DGND.....................................................-0.3V to +0.3V
REF to AGND..............................................-0.3V to (V
DD
+ 0.3V)
REFADJ to AGND.......................................-0.3V to (V
DD
+ 0.3V)
Digital Inputs to DGND...............................-0.3V to (V
DD
+ 0.3V)
Digital Outputs to DGND ............................-0.3V to (V
DD
+ 0.3V)
CH0CH7 to AGND ..........................................................±16.5V
Continuous Power Dissipation (T
A
= +70°C)
Narrow Plastic DIP (derate 14.29mW/°C above +70°C)....1143mW
Wide SO (derate 12.50mW/°C above +70°C)..............1000mW
SSOP (derate 9.52mW/°C above +70°C) ......................762mW
Narrow Ceramic SB (derate 20.00mW/°C above +70°C)..1600mW
Operating Temperature Ranges
MAX199_C_ _ .......................................................0°C to +70°C
MAX199_E_ _.....................................................-40°C to +85°C
MAX199_M_ _ ..................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
MAX199A
Internal CLK mode/internal acquisition
control (Note 4)
External CLK mode/external acquisition
control
External CLK mode/external acquisition control
50kHz, V
IN
= ±4V (Note 3)
Bipolar
Unipolar
Up to the 5th harmonic
Bipolar
MAX199B
Unipolar
CONDITIONS
10
ps
<50
Aperture Jitter
ns
15
Aperture Delay
dB
-86
Channel-to-Channel Crosstalk
dB
80
SFDR
Spurious-Free Dynamic Range
dB
-85
-78
THD
Total Harmonic Distortion
dB
70
LSB
±1/2
INL
Integral Nonlinearity
Bits
12
Resolution
±0.5
LSB
±0.1
Channel-to-Channel Offset
Error Matching
±10
±5
±1
LSB
±1
DNL
Differential Nonlinearity
LSB
±3
Offset Error
±5
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
MAX199A
MAX199B
MAX199A
MAX199B
Bipolar
Unipolar
Bipolar
Unipolar
5
ppm/°C
3
Gain Temperature Coefficient
(Note 2)
±10
MAX199A
±7
MAX199B
MAX199A
MAX199B
LSB
±7
Gain Error
(Note 2)
±10
69
SINAD
Signal-to-Noise + Distortion Ratio
ACCURACY
(Note 1)
DYNAMIC SPECIFICATIONS
(10kHz sine-wave input, ±4.096Vp-p, f
SAMPLE
= 100ksps)
MAX199A
MAX199B
ns
MAX199
Multi-Range (±4V, ±2V, +4V, +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 5V ±5%; unipolar/bipolar range; external reference mode, V
REF
= 4.096V; 4.7µF at REF pin; external clock, f
CLK
= 2.0MHz
with 50% duty cycle; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
f
CLK
= 2.0MHz
MAX199_C
T
A
= +25°C
(Note 5)
Unipolar (see Table 2)
CONDITIONS
mA
30
Output Short-Circuit Current
ppm/°C
±15
REF Output Tempco
(
Contact Maxim Applications
for guaranteed temperature
drift specifications)
V
4.076
4.096
4.116
V
REF
REF Output Voltage
pF
40
Input Capacitance
µs
3
Track/Hold Acquisition Time
0
V
REF/2
V
0
V
REF
Input Voltage Range
1.25
-3dB rolloff
2.5
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
MHz
5
Small-Signal Bandwidth
2.5
Bipolar
-600
10
Unipolar range
-1200
10
±V
REF
range
±V
REF/2
range
Bipolar
0.1
10
Unipolar
10
M
40
Input Dynamic Resistance
Bipolar (see Table 2)
-V
REF/2
V
REF/2
-V
REF
V
REF
0mA to 0.5mA output current (Note 6)
7.5
V
2.465
2.500
2.535
REFADJ Output Voltage
µF
4.7
Capacitive Bypass at REF
With recommended circuit (Figure 1)
%
±1.5
REFADJ Adjustment Range
V/V
1.6384
Buffer Voltage Gain
V
2.4
4.18
Input Voltage Range
µA
400
Input Current
V
REF
= 4.18V
1
V
V
DD
- 50mV
REFADJ Threshold for
Buffer Disable
Normal, or STANDBY power-down mode
k
10
Input Resistance
FULL power-down mode
5
M
±V
REF
range
±V
REF/2
range
0V to V
REF
range
0V to V
REF/2
range
Normal, or STANDBY
power-down mode
FULL power-down
mode
TC V
REF
µA
Input Current
MAX199_M
±40
MAX199_E
±30
k
0mA to 0.1mA output current (Note 6)
mV
0.8
Load Regulation
ANALOG INPUT
INTERNAL REFERENCE
REFERENCE INPUT
(Buffer disabled, reference input applied to REF pin)
MAX199
Multi-Range (±4V, ±2V, +4V, +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 5V ±5%; unipolar/bipolar range; external reference mode, V
REF
= 4.096V; 4.7µF at REF pin; external clock, f
CLK
= 2.0MHz
with 50% duty cycle; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Internal acquisition
3.0
5.0
External reference = 4.096V
After FULLPD or STBYPD
External acquisition (Note 9)
CONDITIONS
Full power-down mode (FULLPD) (Note 7)
5
µs
3.0
t
ACQI
Acquisition Time
LSB
±
1
/
2
PSRR
Power-Supply Rejection Ratio
(Note 8)
3.0
t
ACQE
External CLK
µs
V
4.75
5.25
V
DD
Supply Voltage
6.0
t
CONV
Conversion Time
Internal CLK, C
CLK
= 100pF
6.0
7.7
10.0
To 0.1mV, REF
bypass capacitor
fully discharged
ms
8
Reference Buffer Settling
60
120
60
Normal mode, bipolar ranges
700
850
Normal mode, unipolar ranges
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Standby power-down (STBYPD)
mA
18
I
DD
Supply Current
6
10
µA
Internal reference
±
1
/
2
C
CLK
= 100pF
MHz
1.25
1.56
2.00
f
CLK
Internal Clock Frequency
0.1
2.0
f
CLK
External Clock Frequency Range
MHz
External CLK
Internal CLK
Power-up (Note 10)
µs
200
Bandgap Reference
Start-Up Time
External CLK
ksps
100
Throughput Rate
Internal CLK, C
CLK
= 100pF
62
C
REF
= 4.7µF
C
REF
= 33µF
V
2.4
V
INH
Input High Voltage
V
0.8
V
INL
Input Low Voltage
V
IN
= 0V or V
DD
µA
±10
I
IN
Input Leakage Current
(Note 5)
pF
15
C
IN
Input Capacitance
V
DD
= 4.75V, I
SINK
= 1.6mA
V
0.4
V
OL
Output Low Voltage
V
DD
= 4.75V, I
SOURCE
= 1mA
V
V
DD
- 1
V
OH
Output High Voltage
(Note 5)
pF
15
C
OUT
Three-State Output Capacitance
POWER REQUIREMENTS
TIMING
DIGITAL INPUTS
(D7D0, CLK, RD, WR, CS, HBEN, SHDN) (Note 11)
DIGITAL OUTPUTS
(D7D4, D3/D11, D2/D10, D1/D9, D0/D8, INT)
MAX199
Multi-Range (±4V, ±2V, +4V, +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface
_______________________________________________________________________________________
5
Note 1:
Accuracy specifications tested at V
DD
= 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply
Rejection test. Tested for the ±4.096V input range.
Note 2:
External reference: V
REF
= 4.096V, offset error nulled, ideal last code transition = FS - 3/2LSB.
Note 3:
Ground "on" channel; sine wave applied to all "off" channels.
Note 4:
Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz.
Note 5:
Guaranteed by design. Not tested.
Note 6:
Use static loads only.
Note 7:
Tested using internal reference.
Note 8:
PSRR measured at full-scale. V
DD
= 4.75V to 5.25V.
Note 9:
External acquisition timing: starts at rising edge of WR with control bit ACQMOD = low; ends at rising edge of WR with
ACQMOD = high.
Note 10:
Not subject to production testing. Provided for design guidance only.
Note 11:
All input control signals specified with t
R
= t
F
= 5ns from a voltage level of 0.8V to 2.4V.
Note 12:
t
DO
and t
DO1
are measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V
or 2.4V.
Note 13:
t
TR
is defined as the time required for the data lines to change by 0.5V.
TIMING CHARACTERISTICS
(V
DD
= 5V ±5%; unipolar/bipolar range; external reference mode, V
REF
= 4.096V; 4.7µF at REF pin; external clock, f
CLK
= 2.0MHz
with 50% duty cycle; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
(Note 13)
ns
70
CONDITIONS
t
TR
RD High to Output Disable
ns
120
t
INT1
RD Low to INT High Delay
ns
80
t
CS
CS Pulse Width
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
ns
80
t
WR
WR Pulse Width
ns
0
t
CSWS
ns
0
t
CSWH
CS to WR Hold Time
CS to WR Setup Time
ns
0
t
CSRS
ns
0
t
CSRH
CS to RD Hold Time
CS to RD Setup Time
ns
100
t
CWS
ns
50
t
CWH
CLK to WR Hold Time
CLK to WR Setup Time
ns
60
t
DS
ns
0
t
DH
Data Valid to WR Hold
Data Valid to WR Setup
Figure 2, C
L
= 100pF (Note 12)
Figure 2, C
L
= 100pF (Note 12)
ns
120
t
DO
ns
120
t
DO1
HBEN High or HBEN Low to
Output Valid
RD Low to Output Data Valid
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