_______________General Description
The MAX194 is a 14-bit successive-approximation ana-
log-to-digital converter (ADC) that combines high
speed, high accuracy, low power consumption, and a
10µA shutdown mode. Internal calibration circuitry cor-
rects linearity and offset errors to maintain the full rated
performance over the operating temperature range
without external adjustments. The capacitive-DAC
architecture provides an inherent 85ksps track/hold
function.
The MAX194, with an external reference (up to +5V),
offers a unipolar (0V to V
REF
) or bipolar (-V
REF
to V
REF
)
pin-selectable input range. Separate analog and digital
supplies minimize digital-noise coupling.
The chip select (CS) input controls the three-state seri-
al-data output. The output can be read either during
conversion as the bits are determined, or following con-
version at up to 5Mbps using the serial clock (SCLK).
The end-of-conversion (EOC) output can be used to
interrupt a processor, or can be connected directly to
the convert input (CONV) for continuous, full-speed
conversions.
The MAX194 is available in 16-pin DIP, wide SO, and
ceramic sidebraze packages. The output data format
provides pin-for-pin and functional compatibility with
the 16-bit MAX195 ADC.
________________________Applications
Portable Instruments
Audio
Industrial Controls
Robotics
Multiple Transducer
Medical Signal
Measurements
Acquisition
Vibrations Analysis
Digital Signal
Processing
____________________________Features
o
True 14-Bit Accuracy:
1
/
2
LSB INL
82dB SINAD
o
9.4µs Conversion Time
o
10µA Shutdown Mode
o
Built-In Track/Hold
o
AC and DC Specified
o
Unipolar (0V to V
REF
) and Bipolar (-V
REF
to V
REF
)
Input Range
o
Three-State Serial-Data Output
o
Small 16-Pin DIP, SO, and Ceramic SB Packages
o
Pin-Compatible 16-Bit Upgrade (MAX195)
______________Ordering Information
MAX194
14-Bit, 85ksps ADC with 10µA Shutdown
________________________________________________________________
Maxim Integrated Products
1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VDDA
VSSA
AGND
AIN
VDDD
SCLK
CLK
BP/UP/SHDN
TOP VIEW
MAX194
REF
VSSD
RESET
CONV
CS
EOC
DGND
DOUT
DIP/Wide SO/Ceramic SB
MAX194
AIN
REF
CONV
SCLK
CLK
BP/UP/SHDN
CS
RESET
VSSD
DGND
VDDD
VDDA
AGND
VSSA
DOUT
EOC
SAR
CONTROL LOGIC
COMPARATOR
CALIBRATION
DACs
THREE-STATE BUFFER
4
6
11
16
14
15
5
7
10
8
1
9
3
2
13
12
MAIN DAC
________________Functional Diagram
__________________Pin Configuration
19-0345; Rev 4; 12/97
PART
MAX194ACPE
MAX194BCPE
MAX194ACWE
0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP. RANGE
PIN-PACKAGE
16 Plastic DIP
16 Plastic DIP
16 Wide SO
MAX194BCWE
0°C to +70°C
16 Wide SO
MAX194AEPE
-40°C to +85°C
16 Plastic DIP
MAX194BEPE
-40°C to +85°C
16 Plastic DIP
MAX194AEWE
-40°C to +85°C
16 Wide SO
MAX194BEWE
-40°C to +85°C
16 Wide SO
MAX194AMDE
-55°C to +125°C
16 Ceramic SB
MAX194BMDE
-55°C to +125°C
16 Ceramic SB
EVALUATION KIT
AVAILABLE
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
MAX194
14-Bit, 85ksps ADC with 10µA Shutdown
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDDD = VDDA = +5V, VSSD = VSSA = -5V, f
CLK
= 1.7MHz, V
REF
= +5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C.)
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDD to DGND .....................................................................+7V
VDDA to AGND......................................................................+7V
VSSD to DGND.........................................................+0.3V to -6V
VSSA to AGND .........................................................+0.3V to -6V
VDDD to VDDA, VSSD to VSSA ..........................................±0.3V
AIN, REF ....................................(VSSA - 0.3V) to (VDDA + 0.3V)
AGND to DGND ..................................................................±0.3V
Digital Inputs to DGND...............................-0.3V, (VDDA + 0.3V)
Digital Outputs to DGND............................-0.3V, (VDDA + 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C) ............842mW
Wide SO (derate 9.52mW/°C above +70°C)..................762mW
Ceramic SB (derate 10.53mW/°C above +70°C)...........842mW
Operating Temperature Ranges
MAX194_C_E ........................................................0°C to +70°C
MAX194_E_E .....................................................-40°C to +85°C
MAX194_MDE..................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
16(t
CLK
)
Unipolar
MAX194B, V
REF
= 4.75V
MAX194A, V
REF
= 4.75V
MAX194A
MAX194B
MAX194A, V
REF
= 4.75V
VSSA = -5.25V to -4.75V, V
REF
= 4.75V
MAX194B, V
REF
= 4.75V
VDDA = 4.75V to 5.25V, V
REF
= 4.75V
CONDITIONS
MHz
1.7
f
CLK
Clock Frequency
(Notes 2, 3)
µs
9.4
t
CONV
Conversion Time
dB
-90
Peak Spurious Noise
dB
-90
THD
Total Harmonic Distortion
(up to the 5th harmonic)
V
0
V
REF
Input Range
dB
65
Power-Supply Rejection
Ratio (VDDA and VSSA only)
65
LSB
±1
DNL
Differential Nonlinearity
Bits
14
RES
Resolution
ppm/°C
0.1
Full-Scale Tempco
LSB
±2
Unipolar Full-Scale Error
±1
Unipolar/Bipolar Offset Tempco
ppm/°C
0.4
±1/2
LSB
±1
INL
Integral Nonlinearity
±1
LSB
±2
Unipolar/Bipolar Offset Error
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Unipolar
pF
250
Input Capacitance
dB
82
SINAD
Signal-to-Noise plus Distortion
Ratio
MHz
5
f
SCLK
Serial Clock Frequency
Bipolar
Bipolar
125
-V
REF
V
REF
MAX194B, V
REF
= 4.75V
MAX194A, V
REF
= 4.75V
LSB
±4
Bipolar Full-Scale Error
±2
ACCURACY
(Note 1)
ANALOG INPUT
DYNAMIC PERFORMANCE
(f
s
= 85kHz, bipolar range AIN = -5V to +5V, 1kHz) (Note 1)
MAX194
14-Bit, 85ksps ADC with 10µA Shutdown
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(VDDD = VDDA = +5V, VSSD = VSSA = -5V, f
CLK
= 1.7MHz, V
REF
= +5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C.)
BP/UP/SHDN = open
VDDD = 5.25V
BP/UP/SHDN = open
BP/UP/SHDN = 0V
BP/UP/SHDN = VDDD
Digital inputs = 0 or 5V
VDDD = 4.75V
CONDITIONS
nA
-100
+100
BP/UP/SHDN Max Allowed
Leakage, Mid Input
V
2.75
V
FLT
BP/UP/SHDN Voltage,
Floating
V
1.5
VDDD - 1.5
V
IM
BP/UP/SHDN
Mid Input Voltage
µA
-4.0
I
IL
BP/UP/SHDN
Input Current, Low
µA
4.0
I
IH
BP/UP/SHDN
Input Current, High
V
0.5
V
IL
BP/UP/SHDN
Input Low Voltage
V
2.4
V
IH
CLK, CS, CONV, RESET, SCLK
Input High Voltage
V
VDDD - 0.5
V
IH
BP/UP/SHDN
Input High Voltage
µA
±10
CLK, CS, CONV, RESET, SCLK
Input Current
V
0.8
V
IL
CLK, CS, CONV, RESET, SCLK
Input Low Voltage
pF
10
CLK, CS, CONV, RESET, SCLK
Input Capacitance (Note 2)
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Output Low Voltage
V
OL
VDDD = 4.75V, I
SINK
= 1.6mA
0.4
V
Output High Voltage
V
OH
VDDD = 4.75V, I
SOURCE
= 1mA
VDDD - 0.5
V
DOUT Leakage Current
I
LKG
DOUT = 0 or 5V
±10
µA
Output Capacitance (Note 4)
10
pF
VDDD
4.75
5.25
V
VSSD
-5.25
-4.75
V
VDDA
By supply-rejection test
4.75
5.25
V
VSSA
By supply-rejection test
-5.25
-4.75
V
VDDD Supply Current
I
DDD
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V
2.5
4
mA
VSSD Supply Current
I
SSD
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V
0.9
2
mA
VDDA Supply Current
I
DDA
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V
3.8
5
mA
VSSA Supply Current
I
SSA
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V
3.8
5
mA
DIGITAL INPUTS
(CLK, CS, CONV, RESET, SCLK, BP/UP/SHDN)
DIGITAL OUTPUTS
(DOUT, EOC)
POWER REQUIREMENTS
MAX194
14-Bit, 85ksps ADC with 10µA Shutdown
4
_______________________________________________________________________________________
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V,
BP/UP/SHDN = 0V
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V,
BP/UP/SHDN = 0V
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V,
BP/UP/SHDN = 0V
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V,
BP/UP/SHDN = 0V
CONDITIONS
mW
80
Power Dissipation
µA
0.1
5
I
SSA
VSSA Shutdown Supply Current
µA
0.1
5
I
DDA
VDDA Shutdown Supply Current
µA
1.6
5
I
DDD
VDDD Shutdown Supply Current
(Note 5)
µA
0.1
5
I
SSD
VSSD Shutdown Supply Current
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
ELECTRICAL CHARACTERISTICS (continued)
(VDDD = VDDA = +5V, VSSD = VSSA = -5V, f
CLK
= 1.7MHz, V
REF
= +5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C.)
TIMING CHARACTERISTICS
(VDDD = VDDA = +5V, VSSD = VSSA = -5V, unless otherwise noted.)
Note 1:
Accuracy and dynamic performance tests performed after calibration.
Note 2:
Tested with 50% duty cycle. Duty cycles from 25% to 75% at 1.7MHz are acceptable.
Note 3:
See
External Clock section.
Note 4:
Guaranteed by design, not tested.
Note 5:
Measured in shutdown mode with CLK and SCLK low.
POWER REQUIREMENTS (cont.)
PARAMETER
SYMBOL CONDITIONS
T
A
= +25°C
TYP
T
A
= 0°C to
+70°C
MIN
MAX
T
A
= -40°C to
+85°C
MIN
MAX
T
A
= -55°C to
+125°C
MIN
MAX
UNITS
CONV Pulse Width
t
CW
20
30
35
ns
CONV to CLK Falling
Synchronization (Note 4)
t
CC1
10
10
10
ns
CONV to CLK Rising
Synchronization (Note 4)
t
CC2
40
40
ns
Data Access Time
t
DV
C
L
= 50pF
80
80
40
ns
Bus Relinquish Time
t
DH
C
L
= 10pF
40
40
40
ns
CLK to EOC High
t
CEH
C
L
= 50pF
300
300
350
ns
CLK to EOC Low
t
CEL
C
L
= 50pF
300
300
350
ns
CLK to DOUT Valid
t
CD
C
L
= 50pF
100
350
100
375
100
400
ns
SCLK to DOUT Valid
t
SD
C
L
= 50pF
20
140
20
160
20
160
ns
CS to SCLK Setup Time
t
CSS
75
75
75
ns
CS to SCLK Hold Time
t
CSH
-10
-10
-10
ns
Acquisition Time
t
AQ
2.4
2.4
2.4
µs
Calibration Time
t
CAL
14,000(
CLK
)
8.2
8.2
8.2
ms
RESET to CLK Setup Time
t
RCS
-40
-40
-40
ns
RESET to CLK Hold Time
t
RCH
120
120
120
Start-Up Time (Note 6)
t
SU
Exiting
shutdown
3.2
ns
90
µs
Note 6:
Settling time required after deasserting shutdown to achieve less than 0.1LSB additional error.
_______________Detailed Description
The MAX194 uses a successive-approximation register
(SAR) to convert an analog input to a 14-bit digital
code, which outputs as a serial data stream. The data
bits can be read either during the conversion, at the
CLK clock rate, or between conversions asynchronous
with CLK, at the SCLK rate (up to 5Mbps).
The MAX194 includes a capacitive digital-to-analog
converter (DAC) that provides an inherent track/hold
input. The interface and control logic are designed for
easy connection to most microprocessors (µPs), limiting
the need for external components. In addition to the
SAR and DAC, the MAX194 includes a serial interface, a
sampling comparator used by the SAR, ten calibration
DACs, and control logic for calibration and conversion.
The DAC consists of an array of capacitors with binary
weighted values plus one "dummy sub-LSB" capacitor
(Figure 1). During input acquisition in unipolar mode,
the array's common terminal is connected to AGND
and all free terminals are connected to the input signal
(AIN). After acquisition, the common terminal is discon-
nected from AGND and the free terminals are discon-
nected from AIN, trapping a charge proportional to the
input voltage on the capacitor array.
The free terminal of the MSB (largest) capacitor is con-
nected to the reference (REF), which pulls the common
terminal (connected to the comparator) positive.
Simultaneously, the free terminals of all other capaci-
tors in the array are connected to AGND, which drives
the comparator input negative. If the analog input is
near V
REF
, connecting the MSB's free terminal to REF
only pulls the comparator input slightly positive.
However, connecting the remaining capacitor's free ter-
minals to ground drives the comparator input well
below ground, so that the comparator input is negative,
the comparator output is low, and the MSB is set high.
If the analog input is near ground, the comparator out-
put is high and the MSB is low.
Following this, the next largest capacitor is disconnect-
ed from AGND and connected to REF, and the com-
parator determines the next bit. This continues until all
bits have been determined. For a bipolar input range,
the MSB capacitor is connected to REF rather than AIN
during input acquisition, which results in an input range
of V
REF
to -V
REF
.
MAX194
14-Bit, 85ksps ADC with 10µA Shutdown
_______________________________________________________________________________________
5
______________________________________________________________Pin Description
PIN
NAME
FUNCTION
1
BP/UP/SHDN
Bipolar/Unipolar/Shutdown Input. Three-state input selects bipolar or unipolar input range, or shutdown.
0V = shutdown, +5V = unipolar, floating = bipolar.
2
CLK
Conversion Clock Input
3
SCLK
Serial Clock Input is used to shift data out between conversions. May be asynchronous to CLK.
4
VDDD
+5V Digital Power Supply
5
DOUT
Serial Data Output, MSB first
6
DGND
Digital Ground
7
EOC
End-of-Conversion/Calibration Output--normally low. Rises at beginning of conversion or calibration and
falls at the end of either. May be used as an output framing signal.
8
CS
Chip-Select Input--active low. Enables the serial interface and the three-state data output (DOUT).
9
CONV
Convert-Start Input--active low. Conversion begins on the falling edge after CONV goes low if input signal
has been acquired; otherwise, on the falling clock edge after acquisition.
10
RESET
Reset Input. Pulling RESET low places ADC in inactive state. Rising edge resets control logic and begins
calibration.
11
VSSD
-5V Digital Power Supply
12
REF
Reference Input, 0 to 5V
13
AIN
Analog Input, 0 to V
REF
unipolar or ±V
REF
bipolar range
14
AGND
Analog Ground
15
VSSA
-5V Analog Power Supply
16
VDDA
+5V Analog Power Supply
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