General Description
The MAX1429 is a 5V, high-speed, high-performance
analog-to-digital converter (ADC) featuring a fully differ-
ential wideband track-and-hold (T/H) and a 15-bit con-
verter core. The MAX1429 is optimized for multichannel,
multimode receivers, which require the ADC to meet very
stringent dynamic performance requirements. With a
noise floor of -77.7dBFS, the MAX1429 allows for the
design of receivers with superior sensitivity.
The MAX1429 achieves two-tone, spurious-free dynamic
range (SFDR) of -100dBc for input tones of 10MHz and
15MHz. Its excellent signal-to-noise ratio (SNR) of 75.1dB
and single-tone SFDR performance (SFDR1/SFDR2) of
90dBc/94dBc at f
IN
= 15MHz and a sampling rate of
80Msps make this part ideal for high-performance digital
receivers.
The MAX1429 operates from an analog 5V and a digital
3V supply, features a 2.2V
P-P
full-scale input range,
and allows for a sampling speed of up to 100Msps. The
input T/H operates with a -1dB full-power bandwidth of
260MHz.
The MAX1429 features parallel, CMOS-compatible out-
puts in two's-complement format. To enable the interface
with a wide range of logic devices, this ADC provides a
separate output driver power-supply range of 2.3V to
3.5V. The MAX1429 is manufactured in an 8mm x 8mm,
56-pin thin QFN package with exposed paddle (EP) for
low thermal resistance, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Note that IF parts MAX1418, MAX1428, and MAX1430
(see Pin-Compatible Higher/Lower Speed Versions
Selection table) are recommended for applications that
require high dynamic performance for input frequen-
cies greater than f
CLK
/3. The MAX1429 is optimized for
input frequencies of less than f
CLK
/3.
Applications
Cellular Base-Station Transceiver Systems (BTS)
Wireless Local Loop (WLL)
Single- and Multicarrier Receivers
Multistandard Receivers
E911 Location Receivers
Power Amplifier Linearity Correction
Antenna Array Processing
Features
100Msps Minimum Sampling Rate
-77.7dBFS Noise Floor
Excellent Dynamic Performance
75.1dB SNR at f
IN
= 15MHz and A
IN
= -1dBFS
90dBc/94dBc Single-Tone SFDR1/SFDR2 at
f
IN
= 15MHz and A
IN
= -1dBFS
-100dBc Multitone SFDR at f
IN1
= 10MHz
and f
IN2
= 15MHz
Less than 0.25ps Sampling Jitter
Fully Differential Analog Input Voltage Range of
2.2V
P-P
CMOS-Compatible Two's-Complement Data Output
Separate Data Valid Clock and Overrange Outputs
Flexible-Input Clock Buffer
EV Kit Available for MAX1429
(Order MAX1427EVKIT)
MAX1429
15-Bit, 100Msps ADC with -77.7dBFS
Noise Floor for Baseband Applications
________________________________________________________________ Maxim Integrated Products
1
Ordering Information
19-3434; Rev 0; 10/04
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
Pin Configuration appears at end of data sheet.
PART
TEMP RANGE
PIN-PACKAGE
MAX1429ETN
-40°C to +85°C
56 Thin QFN-EP*
Pin-Compatible Higher/Lower
Speed Versions Selection
PART
SPEED GRADE
(Msps)
TARGET
APPLICATION
MAX1418
65
IF
MAX1419
65
Baseband
MAX1427
80
Baseband
MAX1428
80
IF
MAX1429
100
Baseband
MAX1430
100
IF
*
EP = Exposed paddle.
MAX1429
15-Bit, 100Msps ADC with -77.7dBFS
Noise Floor for Baseband Applications
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, GND = 0, INP and INN driven differentially with -1dBFS, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, C
L
= 5pF at digital outputs, f
CLK
= 100MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C, unless otherwise noted.
+25°C guaranteed by production test, <+25°C guaranteed by design and char-
acterization.)
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AV
CC
, DV
CC
, DRV
CC
to GND.................................. -0.3V to +6V
INP, INN, CLKP, CLKN, CM to GND........-0.3V to (AV
CC
+ 0.3V)
D0D14, DAV, DOR to GND..................-0.3V to (DRV
CC
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
56-Pin Thin QFN (derate 47.6mW/°C above +70°C)...3809.5mW
Operating Temperature Range ...........................-40°C to +85°C
Thermal Resistance
J
A
...................................................21°C/W
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300
°C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
15
Bits
Integral Nonlinearity
INL
f
IN
= 15MHz
±1.5
LSB
Differential Nonlinearity
DNL
f
IN
= 15MHz, no missing codes guaranteed
±0.4
LSB
Offset Error
-12
+12
mV
Gain Error
-4
+4
%FS
ANALOG INPUT (INP, INN)
Differential Input Voltage Range
V
DIFF
Fully differential inputs drive,
V
DIFF
= V
INP
- V
INN
2.20
V
P-P
Common-Mode Input Voltage
V
CM
Self-biased
3.33
V
Differential Input Resistance
R
IN
1
±15%
k
Differential Input Capacitance
C
IN
1
pF
Full-Power Analog Bandwidth
FPBW
-1dB
-1dB rolloff for a full-scale input
260
MHz
CONVERSION RATE
Maximum Clock Frequency
f
CLK
100
MHz
Minimum Clock Frequency
f
CLK
20
MHz
Aperture Jitter
t
AJ
0.21
ps
RMS
CLOCK INPUT (CLKP, CLKN)
Full-Scale Differential Input
Voltage
V
DIFFCLK
Fully differential input drive, V
CLKP
- V
CLKN
0.5 to
3.0
V
Common-Mode Input Voltage
V
CM
Self-biased
2.4
V
Differential Input Resistance
R
INCLK
2
±15%
k
Differential Input Capacitance
C
INCLK
1
pF
DYNAMIC CHARACTERISTICS
Thermal + Quantization Noise
Floor
NF
Analog input <-35dBFS
-77.7
dBFS
MAX1429
15-Bit, 100Msps ADC with -77.7dBFS
Noise Floor for Baseband Applications
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, GND = 0, INP and INN driven differentially with -1dBFS, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, C
L
= 5pF at digital outputs, f
CLK
= 100MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C, unless otherwise noted.
+25°C guaranteed by production test, <+25°C guaranteed by design and char-
acterization.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
IN
= 5MHz at -1dBFS
75.3
f
IN
= 15MHz at -1dBFS
72.1
75.1
Signal-to-Noise
Ratio (Note 1)
SNR
f
IN
= 35MHz at -1dBFS
74.8
dB
f
IN
= 5MHz at -1dBFS
75.0
f
IN
= 15MHz at -1dBFS
71.7
74.9
Signal-to-Noise
and Distortion
(Note 1)
SINAD
f
IN
= 35MHz at -1dBFS
71.1
dB
f
IN
= 5MHz at -1dBFS
90.0
f
IN
= 15MHz at -1dBFS
84.0
90.0
Spurious-Free Dynamic Range
(HD2 and HD3)
(Note 1)
SFDR1
f
IN
= 35MHz at -1dBFS
74.0
dBc
f
IN
= 5MHz at -1dBFS
96.0
f
IN
= 15MHz at -1dBFS
85.0
94.0
Spurious-Free Dynamic Range
(HD4 and Higher)
(Note 1)
SFDR2
f
IN
= 35MHz at -1dBFS
92.0
dBc
Two-Tone Intermodulation
Distortion
TTIMD
f
IN1
= 10MHz at -7dBFS,
f
IN2
= 15MHz at -7dBFS
-85
dBc
Two-Tone Spurious-Free
Dynamic Range
SFDR
TT
f
I N 1
= 10M H z at - 10d BFS < f
I N 1
< - 100d BFS ,
f
IN 2
= 15M H z at - 10d BFS < f
IN 2
< - 100d BFS
-100
dBFS
DIGITAL OUTPUTS (D0D14, DAV, DOR)
Digital Output-Voltage Low
V
OL
0.5
V
Digital Output-Voltage High
V
OH
DRV
CC
- 0.5
V
TIMING CHARACTERISTICS (DV
CC
= DRV
CC
= 2.5V)
CLKP/CLKN Duty Cycle
Duty Cycle
50
±5
%
Effective Aperture Delay
t
AD
230
ps
Output Data Delay
t
DAT
(Note 3)
3.0
4.5
7.5
ns
Data Valid Delay
t
DAV
(Note 3)
5.3
6.5
8.7
ns
Pipeline Latency
t
LATENCY
(Note 3)
3
Clock
cycles
CLKP Rising Edge to DATA Not
Valid
t
DNV
(Note 3)
2.6
3.8
5.7
ns
CLKP Rising Edge to DATA Valid
(guaranteed)
t
DGV
(Note 3)
3.4
5.2
8.6
ns
DATA Setup Time (Before DAV
Rising Edge)
t
SETUP
(Note 3)
t
CLKP
- 0.5
t
CLKP
+ 1.3
t
CLKP
+
2.4
ns
DATA Hold Time (After DAV
Rising Edge)
t
HOLD
(Note 3)
t
CLKN
-
3.6
t
CLKN
-
2.8
t
CLKN
-
2.0
ns
MAX1429
15-Bit, 100Msps ADC with -77.7dBFS
Noise Floor for Baseband Applications
4
_______________________________________________________________________________________
Note 1:
Dynamic performance is based on a 32,768-point data record with a sampling frequency of f
SAMPLE
= 100.007936MHz, an
input frequency of f
IN
= f
SAMPLE
x (4915/32768) = 15.000580MHz, and a frequency bin size of 3052Hz. Close-in (f
IN
±
36.6kHz) and low-frequency (DC to 73.2kHz) bins are excluded from the spectrum analysis.
Note 2:
Apply the same voltage levels to DV
CC
and DRV
CC
.
Note 3:
Guaranteed by design and characterization.
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, GND = 0, INP and INN driven differentially with -1dBFS, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, C
L
= 5pF at digital outputs, f
CLK
= 100MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C, unless otherwise noted.
+25°C guaranteed by production test, <+25°C guaranteed by design and char-
acterization.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (DV
CC
= DRV
CC
= 3.3V)
CLKP/CLKN Duty Cycle
Duty Cycle
50
±5
%
Effective Aperture Delay
t
AD
230
ps
Output Data Delay
t
DAT
(Note 3)
2.8
4.1
6.5
ns
Data Valid Delay
t
DAV
(Note 3)
5.3
6.3
8.6
ns
Pipeline Latency
t
LATENCY
3
Clock
cycles
CLKP Rising Edge to DATA Not
Valid
t
DNV
(Note 3)
2.5
3.4
5.2
ns
CLKP Rising Edge to DATA Valid
(guaranteed)
t
DGV
(Note 3)
3.2
4.4
7.4
ns
DATA Setup Time (Before DAV
Rising Edge)
t
SETUP
(Note 3)
t
CLKP
+
0.2
t
CLKP
+
1.7
t
CLKP
+
2.8
ns
DATA Hold Time (After DAV
Rising Edge)
t
HOLD
(Note 3)
t
CLKN
-
3.5
t
CLKN
-
2.7
t
CLKN
-
2.0
ns
POWER REQUIREMENTS
Analog Supply Voltage Range
AV
CC
5
±3%
V
Digital-Supply Voltage Range
DV
CC
(Note 2)
2.3 to
2.5
V
Output-Supply Voltage Range
DRV
CC
(Note 2)
2.3 to
2.5
V
Analog Supply Current
I
AVCC
390
440
mA
Digital + Output Supply Current
I
DVCC
+
I
DRVCC
f
CLK
= 100MHz, C
L
= 5pF
38
44
mA
Total Power Dissipation
PDISS
2045
mW
MAX1429
15-Bit, 100Msps ADC with -77.7dBFS
Noise Floor for Baseband Applications
_______________________________________________________________________________________
5
FFT PLOT (32,768-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1429 toc01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
25
20
15
10
5
-100
-80
-60
-40
-20
0
-120
0
50
45
40
35
30
f
CLK
= 100.0997MHz
f
IN
= 10.0014MHz
A
IN
= -1.05dBFS
SNR = 75.6dBc
SINAD = 75.4dBc
SFDR1 = 90dBc
SFDR2 = 96.4dBc
HD2 = -91dBFS
HD3 = -95.5dBFS
FFT PLOT (32,768-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1429 toc02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
25
20
15
10
5
-100
-80
-60
-40
-20
0
-120
0
50
45
40
35
30
f
CLK
= 100.0997MHz
f
IN
= 15.0021MHz
A
IN
= -0.96dBFS
SNR = 75.3dBc
SINAD = 74.8dBc
SFDR1 = 86.7dBc
SFDR2 = 93.9dBc
HD2 = -87.6dBFS
HD3 = -90.2dBFS
FFT PLOT (32,768-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1429 toc03
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
25
20
15
10
5
-100
-80
-60
-40
-20
0
-120
0
50
45
40
35
30
f
CLK
= 100.0997MHz
f
IN
= 34.9973MHz
A
IN
= -1.01dBFS
SNR = 75dBc
SINAD = 70.6dBc
SFDR1 = 73dBc
SFDR2 = 93.9dBc
HD2 = -83.6dBFS
HD3 = -74dBFS
TWO-TONE IMD PLOT (32,768-POINT DATA
RECORD, COHERENT SAMPLING)
MAX1429 toc04
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
25
20
15
10
5
-100
-80
-60
-40
-20
0
-120
0
50
45
40
35
30
f
CLK
= 100.0997MHz
f
IN1
= 10.1022MHz
A
IN1
= -7.09dBFS
f
IN2
= 15.0021MHz
A
IN2
= -7dBFS
IMD = -84.9dBc
f
IN1
f
IN2
f
IN2
- f
IN1
f
IN1
+ f
IN2
SNR vs. ANALOG INPUT FREQUENCY
(f
CLK
= 100.0997MHz, A
IN
= -1dBFS)
MAX1429 toc05
f
IN
(MHz)
SNR (dBc)
45
40
35
30
25
20
15
10
71
72
73
74
75
76
77
70
5
50
SFDR1/SFDR2 vs. ANALOG INPUT FREQUENCY
(f
CLK
= 100.0997MHz, A
IN
= -1dBFS)
MAX1429 toc06
f
IN
(MHz)
SFDR1/SFDR2 (dBc)
45
40
35
30
25
20
15
10
65
75
85
95
105
115
55
5
50
SFDR2
SFDR1
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(f
CLK
= 100.0997MHz, A
IN
= -1dBFS)
MAX1429 toc07
f
IN
(MHz)
HD2/HD3 (dBFS)
45
40
35
30
25
20
15
10
-100
-95
-90
-85
-80
-75
-70
-65
-105
5
50
HD3
HD2
SNR vs. SAMPLING FREQUENCY
(f
IN
= 15MHz, A
IN
= -1dBFS)
MAX1429 toc08
f
CLK
(MHz)
SNR (dBc)
90
80
30
40
50
60
70
71
72
73
74
75
76
77
78
70
20
100
SFDR1/SFDR2 vs. SAMPLING FREQUENCY
(f
IN
= 15MHz, A
IN
= -1dBFS)
MAX1429 toc09
f
CLK
(MHz)
SFDR1/SFDR2 (dBc)
90
80
30
40
50
60
70
75
80
85
90
95
100
105
70
20
100
SFDR2
SFDR1
Typical Operating Characteristics
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, INP and INN driven differentially with a -1dBFS amplitude, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, C
L
= 5pF at digital outputs, f
CLK
= 100MHz, T
A
= +25°C. All AC data is based on a 32k-point
FFT record and under coherent sampling conditions.)
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