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Part Number MAX1249

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_______________General Description
The MAX1248/MAX1249 10-bit data-acquisition sys-
tems combine a 4-channel multiplexer, high-bandwidth
track/hold, and serial interface with high conversion
speed and low power consumption. They operate from
a single +2.7V to +5.25V supply, and their analog
inputs are software configurable for unipolar/bipolar
and single-ended/differential operation.
The 4-wire serial interface connects directly to SPITM/
QSPITM and MICROWIRETM devices without external
logic. A serial strobe output allows direct connection
to TMS320-family digital signal processors. The
MAX1248/MAX1249 use either the internal clock or an
external serial-interface clock to perform successive-
approximation analog-to-digital conversions.
The MAX1248 has an internal 2.5V reference, while the
MAX1249 requires an external reference. Both parts
have a reference-buffer amplifier with a ±1.5% voltage
adjustment range.
These devices provide a hard-wired SHDN pin and a
software-selectable power-down, and can be pro-
grammed to automatically shut down at the end of a
conversion. Accessing the serial interface automatically
powers up the MAX1248/MAX1249, and the quick
turn-on time allows them to be shut down between all
conversions. This technique can cut supply current to
under 60µA at reduced sampling rates.
The MAX1248/MAX1249 are available in a 16-pin DIP
and a very small QSOP that occupies the same board
area as an 8-pin SO.
For 8-channel versions of these devices, see the
MAX148/MAX149 data sheet.
________________________Applications
Portable Data Logging
Data Acquisition
Medical Instruments
Battery-Powered Instruments
Pen Digitizers
System Supervision
____________________________Features
o
4-Channel Single-Ended or 2-Channel
Differential Inputs
o
Single +2.7V to +5.25V Operation
o
Internal 2.5V Reference (MAX1248)
o
Low Power: 1.2mA (133ksps, +3V supply)
54µA (1ksps, +3V supply)
1µA (power-down mode)
o
SPI/QSPI/MICROWIRE/TMS320-Compatible
4-Wire Serial Interface
o
Software-Configurable Unipolar or Bipolar Inputs
o
16-Pin QSOP Package (same area as 8-pin SO)
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
________________________________________________________________
Maxim Integrated Products
1
19-1072; Rev 2; 5/98
PART
MAX1248
ACPE
MAX1248BCPE
MAX1248ACEE
0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP. RANGE
PIN-PACKAGE
16 Plastic DIP
16 Plastic DIP
16 QSOP
_____________Ordering Information
Ordering Information continued at end of data sheet.
Contact factory for availability of alternate surface-mount
packages.
Pin Configuration appears at end of data sheet.
MAX1248BCEE
0°C to +70°C
16 QSOP
INL
(LSB)
±1/2
±1
±1/2
±1
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
V
DD
I/O
SCK (SK)
MOSI (SO)
MISO (SI)
V
SS
SHDN
SSTRB
DOUT
DIN
SCLK
CS
COM
AGND
DGND
V
DD
CH3
C1
4.7
µ
F
C2
0.01
µ
F
C3
0.1
µ
F
CH0
0V TO
+2.5V
ANALOG
INPUTS
MAX1248
CPU
+3V
VREF
REFADJ
__________Typical Operating Circuit
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V
DD
= +2.7V to +5.25V; COM = 0V; f
SCLK
= 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
MAX1248--4.7µF capacitor at VREF pin; MAX1249--external reference, VREF = 2.500V applied to VREF pin; T
A
= T
MIN
to T
MAX
,
unless otherwise noted.)
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
DD
to AGND, DGND .............................................. -0.3V to +6V
AGND to DGND.................................................... -0.3V to +0.3V
CH0­CH3, COM to AGND, DGND ............ -0.3V to (V
DD
+ 0.3V)
VREF to AGND........................................... -0.3V to (V
DD
+ 0.3V)
Digital Inputs to DGND............................................ -0.3V to +6V
Digital Outputs to DGND ........................... -0.3V to (V
DD
+ 0.3V)
Digital Output Sink Current .................................................25mA
Continuous Power Dissipation (T
A
= +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C) ......... 842mW
QSOP (derate 8.30mW/°C above +70°C) ................... 667mW
CERDIP (derate 10.00mW/°C above +70°C) .............. 800mW
Operating Temperature Ranges
MAX1248_C_E/MAX1249_C_E .......................... 0°C to +70°C
MAX1248_E_E/MAX1249_E_E........................ -40°C to +85°C
MAX1248_MJE/MAX1249_MJE .................... -55°C to +125°C
Storage Temperature Range ............................ -60°C to +150°C
Lead Temperature (soldering, 10sec) ............................ +300°C
6
µs
35
65
t
CONV
Conversion Time (Note 5)
5.5
7.5
MHz
1.0
Full-Power Bandwidth
MHz
2.25
Small-Signal Bandwidth
dB
-75
Channel-to-Channel Crosstalk
dB
70
SFDR
Spurious-Free Dynamic Range
dB
-70
THD
Total Harmonic Distortion
dB
66
SINAD
Signal-to-Noise + Distortion Ratio
LSB
±0.05
Channel-to-Channel Offset
Matching
ppm/°C
±0.25
Gain Temperature Coefficient
±0.5
Bits
10
Resolution
±1
Offset Error
LSB
±1.0
INL
Relative Accuracy (Note 2)
LSB
±1
DNL
±1
LSB
±2
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
External clock = 2MHz, 12 clocks/conversion
Internal clock, SHDN = V
DD
Internal clock, SHDN = FLOAT
MAX124_A
-3dB rolloff
65kHz, 2.500Vp-p (Note 4)
Up to the 5th harmonic
MAX124_A
MAX124_B
No missing codes over temperature
MAX124_A
MAX124_B
CONDITIONS
Differential Nonlinearity
ns
30
Aperture Delay
MHz
1.8
SHDN = FLOAT
ps
<50
Aperture Jitter
MHz
0.1
2.0
µs
1.5
t
ACQ
Track/Hold Acquisition Time
0.225
Internal Clock Frequency
SHDN = V
DD
0
2.0
External Clock Frequency
Data transfer only
LSB
Gain Error (Note 3)
±2
MAX124_B
DC ACCURACY
(Note 1)
DYNAMIC SPECIFICATIONS
(10kHz sine-wave input, 0V to 2.500Vp-p, 133ksps, 2.0MHz external clock, bipolar input mode)
CONVERSION RATE
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
_______________________________________________________________________________________
3
Multiplexer Leakage Current
pF
15
C
IN
DIN, SCLK, CS Input Capacitance
µA
±0.01
±1
I
IN
DIN, SCLK, CS Input Leakage
V
0.2
V
HYST
DIN, SCLK, CS Input Hysteresis
V
0.8
V
IL
DIN, SCLK, CS Input Low Voltage
2.0
µA
0.01
10
Shutdown VREF Input Current
k
18
25
VREF Input Resistance
µA
100
150
VREF Input Current
V
1.0
V
DD
+
50mV
VREF Input Voltage Range
(Note 9)
pF
16
Input Capacitance
0 to VREF
V
±VREF / 2
Input Voltage Range, Single-
Ended and Differential (Note 6)
µA
±0.01
±1
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
(Note 10)
V
IN
= 0V or V
DD
Unipolar, COM = 0V
V
DD
3.6V
VREF = 2.500V
Bipolar, COM = VREF / 2
On/off leakage current, V
CH_
= 0V or V
DD
CONDITIONS
µA
±4.0
I
S
SHDN Input Current
V
0.4
V
SL
SHDN Input Low Voltage
V
V
DD
- 0.4
V
SH
SHDN Input High Voltage
SHDN = 0V or V
DD
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +2.7V to +5.25V; COM = 0V; f
SCLK
= 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
MAX1248--4.7µF capacitor at VREF pin; MAX1249--external reference, VREF = 2.500V applied to VREF pin; T
A
= T
MIN
to T
MAX
,
unless otherwise noted.)
V
3.0
V
IH
DIN, SCLK, CS Input High Voltage
V
DD
> 3.6V
V
2.470
2.500
2.530
VREF Output Voltage
T
A
= +25°C (Note 7)
mA
30
VREF Short-Circuit Current
ppm/°C
±30
VREF Temperature Coefficient
MAX1248
µF
0
Capacitive Bypass at VREF
Internal compensation mode
4.7
External compensation mode
mV
0.35
Load Regulation (Note 8)
0mA to 0.2mA output load
µF
0.01
Capacitive Bypass at REFADJ
±1.5
REFADJ Adjustment Range
%
V
V
DD -
0.5
REFADJ Buffer-Disable Threshold
Capacitive Bypass at VREF
Internal compensation mode
0
µF
External compensation mode
4.7
Reference-Buffer Gain
MAX1248
2.06
V/V
MAX1249
2.00
REFADJ Input Current
MAX1248
±50
µA
MAX1249
±10
V
1.1
V
DD
- 1.1
V
SM
SHDN Input Mid Voltage
ANALOG/COM INPUTS
EXTERNAL REFERENCE AT VREF
(Buffer disabled)
DIGITAL INPUTS
(DIN, SCLK, CS, SHDN)
EXTERNAL REFERENCE AT REFADJ
INTERNAL REFERENCE
(MAX1248 only, reference buffer enabled)
V
DD
= 5.25V
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
4
_______________________________________________________________________________________
1.2
2.0
3.5
15
Operating mode,
full-scale input (Note 11)
30
70
Fast power-down (MAX1248)
nA
±100
SHDN Maximum Allowed
Leakage, Mid Input
V
V
DD
/ 2
V
FLT
SHDN Voltage, Floating
SHDN = FLOAT
SHDN = FLOAT
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
µA
1.2
10
I
DD
CONDITIONS
Positive Supply Current
mA
1.6
3.0
µA
±0.01
±10
I
L
Three-State Leakage Current
V
V
DD
- 0.5
V
OH
Output Voltage High
V
0.8
V
OL
Output Voltage Low
0.4
V
2.70
5.25
V
DD
Positive Supply Voltage
pF
15
C
OUT
Three-State Output Capacitance
Full power-down
CS = V
DD
(Note 10)
CS = V
DD
I
SOURCE
= 0.5mA
I
SINK
= 16mA
I
SINK
= 5mA
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +2.7V to +5.25V; COM = 0V; f
SCLK
= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
MAX1248--4.7µF capacitor at VREF pin; MAX1249--external reference; VREF = 2.500V applied to VREF pin, T
A
= T
MIN
to T
MAX
,
unless otherwise noted.)
mV
±0.3
PSR
Supply Rejection (Note 12)
V
DD
= 2.7V to 5.25V, full-scale input,
external reference = 2.500V
DIGITAL OUTPUTS
(DOUT, SSTRB)
POWER REQUIREMENTS
I
DD
V
DD
= 5.25V
V
DD
= 3.6V
V
DD
= 5.25V
V
DD
= 3.6V
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
_______________________________________________________________________________________
5
TIMING CHARACTERISTICS
(V
DD
= +2.7V to +5.25V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Note 1:
Tested at V
DD
= 2.7V; COM = 0V; unipolar single-ended input mode.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:
MAX1248--internal reference, offset nulled; MAX1249 -- external reference (VREF = +2.500V), offset nulled.
Note 4:
Ground "on" channel; sine wave applied to all "off" channels.
Note 5:
Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6:
The common-mode range for the analog inputs is from AGND to V
DD
.
Note 7
Sample tested to 0.1% AQL.
Note 8:
External load should not change during conversion for specified accuracy.
Note 9:
ADC performance is limited by the converter's noise floor, typically 300µVp-p.
Note 10
Guaranteed by design. Not subject to production testing.
Note 11:
The MAX1249 typically draws 400
µ
A less than the values shown.
Note 12:
Measured as
|
V
FS
(2.7V) - V
FS
(5.25V)
|
.
DIN to SCLK Setup
ns
240
t
STR
CS Rise to SSTRB Output Disable
ns
240
t
SDV
CS Fall to SSTRB Output Enable
240
t
SSTRB
SCLK Fall to SSTRB
ns
200
t
CL
SCLK Pulse Width Low
ns
200
SCLK Pulse Width High
ns
0
CS to SCLK Rise Hold
ns
100
t
CSS
CS to SCLK Rise Setup
ns
240
t
TR
CS Rise to Output Disable
ns
240
t
DV
CS Fall to Output Enable
t
DO
SCLK Fall to Output Data Valid
ns
0
t
DH
DIN to SCLK Hold
ns
µs
1.5
t
ACQ
Acquisition Time
0
t
SCK
SSTRB Rise to SCLK Rise
ns
100
t
DS
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Internal clock mode only (Note 10)
External clock mode only, Figure 2
External clock mode only, Figure 1
Figure 1
Figure 2
Figure 1
CONDITIONS
ns
20
240
Figure 1
t
CSH
t
CH
ns
MAX124_ _C/E
MAX124_ _M
20
200