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_______________General Description
The MAX1246/MAX1247 12-bit data-acquisition systems
combine a 4-channel multiplexer, high-bandwidth
track/hold, and serial interface with high conversion
speed and low power consumption. The MAX1246 oper-
ates from a single +2.7V to +3.6V supply; the MAX1247
operates from a single +2.7V to +5.25V supply. Both
devices' analog inputs are software configurable for
unipolar/bipolar and single-ended/differential operation.
The 4-wire serial interface connects directly to SPITM/
QSPITM and MicrowireTM devices without external logic. A
serial strobe output allows direct connection to TMS320-
family digital signal processors. The MAX1246/MAX1247
use either the internal clock or an external serial-interface
clock to perform successive-approximation analog-to-
digital conversions.
The MAX1246 has an internal 2.5V reference, while the
MAX1247 requires an external reference. Both parts have
a reference-buffer amplifier with a ±1.5% voltage-
adjustment range.
These devices provide a hard-wired SHDN pin and a
software-selectable power-down, and can be pro-
grammed to automatically shut down at the end of a con-
version. Accessing the serial interface automatically
powers up the MAX1246/MAX1247, and the quick turn-on
time allows them to be shut down between all conver-
sions. This technique can cut supply current to under
60µA at reduced sampling rates.
The MAX1246/MAX1247 are available in a 16-pin DIP and
a small QSOP that occupies the same board area as an
8-pin SO.
For 8-channel versions of these devices, see the
MAX146/MAX147 data sheet.
________________________Applications
Portable Data Logging
Data Acquisition
Medical Instruments
Battery-Powered Instruments
Pen Digitizers
Process Control
____________________________Features
o
4-Channel Single-Ended or 2-Channel
Differential Inputs
o
Single-Supply Operation:
+2.7V to +3.6V (MAX1246)
+2.7V to +5.25V (MAX1247)
o
Internal 2.5V Reference (MAX1246)
o
Low Power: 1.2mA (133ksps, 3V supply)
54µA (1ksps, 3V supply)
1µA (power-down mode)
o
SPI/QSPI/Microwire/TMS320-Compatible
4-Wire Serial Interface
o
Software-Configurable Unipolar or Bipolar Inputs
o
16-Pin QSOP Package (same area as 8-pin SO)
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
________________________________________________________________
Maxim Integrated Products
1
V
DD
I/O
SCK (SK)
MOSI (SO)
MISO (SI)
V
SS
SHDN
SSTRB
DOUT
DIN
SCLK
CS
COM
AGND
DGND
V
DD
CH3
4.7
µ
F
0.1
µ
F
CH0
0V TO
+2.5V
ANALOG
INPUTS
MAX1246
CPU
+3V
VREF
0.047
µ
F
REFADJ
__________Typical Operating Circuit
19-1071; Rev 1; 3/97
PART
MAX1246
ACPE
MAX1246BCPE
MAX1246ACEE
0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP. RANGE
PIN-PACKAGE
16 Plastic DIP
16 Plastic DIP
16 QSOP
EVALUATION KIT
AVAILABLE
______________Ordering Information
Ordering Information continued at end of data sheet.
Contact factory for availability of alternate surface-mount
packages.
MAX1246BCEE
0°C to +70°C
16 QSOP
INL
(LSB)
±1/2
±1
±1/2
±1
SPI and QSPI are registered trademarks of Motorola, Inc. Microwire is a registered trademark of National Semiconductor Corp.
Pin Configuration appears at end of data sheet.
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V
DD
= +2.7V to +3.6V (MAX1246); V
DD
= +2.7V to +5.25V (MAX1247); COM = 0V; f
SCLK
= 2.0MHz; external clock (50% duty cycle);
15 clocks/conversion cycle (133ksps); MAX1246--4.7µF capacitor at VREF pin; MAX1247--external reference, VREF = 2.500 V
applied to VREF pin; T
A
= T
MIN
to T
MAX
; unless otherwise noted.)
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
DD
to AGND, DGND................................................. -0.3V to 6V
AGND to DGND ...................................................... -0.3V to 0.3V
CH0CH3, COM to AGND, DGND ............ -0.3V to (V
DD
+ 0.3V)
VREF to AGND........................................... -0.3V to (V
DD
+ 0.3V)
Digital Inputs to DGND .............................................. -0.3V to 6V
Digital Outputs to DGND ........................... -0.3V to (V
DD
+ 0.3V)
Digital Output Sink Current .................................................25mA
Continuous Power Dissipation (T
A
= +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C) ......... 842mW
QSOP (derate 8.36mW/°C above +70°C) ................... 667mW
CERDIP (derate 10.00mW/°C above +70°C) .............. 800mW
Operating Temperature Ranges
MAX1246_C_E/MAX1247_C_E .......................... 0°C to +70°C
MAX1246_E_E/MAX1247_E_E........................ -40°C to +85°C
MAX1246_MJE/MAX1247_MJE .................... -55°C to +125°C
Storage Temperature Range ............................ -60°C to +150°C
Lead Temperature (soldering, 10sec) ............................ +300°C
µs
1.5
t
ACQ
Differential Nonlinearity
Track/Hold Acquisition Time
ns
30
Aperture Delay
6
µs
35
65
t
CONV
Conversion Time (Note 5)
5.5
7.5
ps
MHz
1.0
Full-Power Bandwidth
MHz
2.25
Small-Signal Bandwidth
dB
-85
Channel-to-Channel Crosstalk
dB
80
90
SFDR
Spurious-Free Dynamic Range
dB
-88
-80
THD
Total Harmonic Distortion
dB
70
73
SINAD
Signal-to-Noise + Distortion Ratio
LSB
±0.25
Channel-to-Channel Offset
Matching
ppm/°C
±0.25
Gain Temperature Coefficient
±0.5
<50
Bits
12
Resolution
LSB
Gain Error (Note 3)
±0.5
±4
Aperture Jitter
Offset Error
LSB
±1.0
INL
Relative Accuracy (Note 2)
LSB
±1
DNL
±0.5
±3
LSB
±0.5
±4
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
External clock = 2MHz, 12 clocks/conversion
Internal clock, SHDN = V
DD
Internal clock, SHDN = FLOAT
MAX124_A
-3dB rolloff
65kHz, 2.500V
p-p
(Note 4)
Up to the 5th harmonic
MAX124_B
No missing codes over temperature
MAX124_A
MAX124_B
CONDITIONS
1.8
SHDN = FLOAT
MHz
0.225
Internal Clock Frequency
SHDN = V
DD
0.1
2.0
MHz
0
2.0
External Clock Frequency
Data transfer only
DC ACCURACY
(Note 1)
DYNAMIC SPECIFICATIONS
(10kHz sine-wave input, 0V to 2.500Vp-p, 133ksps, 2.0MHz external clock, bipolar input mode)
CONVERSION RATE
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
_______________________________________________________________________________________
3
Multiplexer Leakage Current
µA
0.01
10
Shutdown VREF Input Current
k
18
25
VREF Input Resistance
µA
100
150
VREF Input Current
V
1.0
V
DD
+
50mV
VREF Input Voltage Range
(Note 9)
pF
16
Input Capacitance
0 to VREF
V
±VREF / 2
Input Voltage Range, Single-
Ended and Differential (Note 6)
µA
±0.01
±1
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Unipolar, COM = 0V
VREF = 2.500V
Bipolar, COM = VREF / 2
On/off leakage current, V
CH_
= 0V or V
DD
CONDITIONS
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +2.7V to +3.6V (MAX1246); V
DD
= +2.7V to +5.25V (MAX1247); COM = 0V; f
SCLK
= 2.0MHz; external clock (50% duty cycle);
15 clocks/conversion cycle (133ksps); MAX1246--4.7µF capacitor at VREF pin; MAX1247--external reference, VREF = 2.500 V
applied to VREF pin; T
A
= T
MIN
to T
MAX
; unless otherwise noted.)
V
2.480
2.500
2.520
VREF Output Voltage
T
A
= +25°C
mA
30
VREF Short-Circuit Current
±30
±50
MAX1246_C
±30
±60
MAX1246_E
ppm/°C
±30
±80
VREF Temperature Coefficient
MAX1246_M
mV
±0.35
Load Regulation (Note 8)
0mA to 0.2mA output load
0
Internal compensation mode
µF
4.7
Capacitive Bypass at VREF
External compensation mode
µF
0.047
Capacitive Bypass at REFADJ
%
±1.5
REFADJ Adjustment Range
V
V
DD
-
0.5
REFADJ Buffer Disable Threshold
µF
0
Capacitive Bypass at VREF
Internal compensation mode
2.00
V/V
2.06
Reference Buffer Gain
4.7
MAX1247
MAX1246
External compensation mode
±10
µA
±50
REFADJ Input Current
MAX1247
MAX1246
ANALOG/COM INPUTS
INTERNAL REFERENCE
(MAX1246 only, reference buffer enabled)
EXTERNAL REFERENCE AT VREF
(Buffer disabled)
EXTERNAL REFERENCE AT REFADJ
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +2.7V to +3.6V (MAX1246); V
DD
= +2.7V to +5.25V (MAX1247); COM = 0V; f
SCLK
= 2.0MHz; external clock (50% duty cycle);
15 clocks/conversion cycle (133ksps); MAX1246--4.7µF capacitor at VREF pin; MAX1247--external reference, VREF = 2.500 V
applied to VREF pin; T
A
= T
MIN
to T
MAX
; unless otherwise noted.)
V
3.0
V
IH
V
DD
= 3.6V
DIN, SCLK, CS Input High Voltage
V
DD
> 3.6V, MAX1247 only
mV
±0.3
PSR
Supply Rejection (Note 10)
V
DD
= 2.7V to V
DD(MAX)
, full-scale input,
external reference = 2.500V
pF
15
C
IN
DIN, SCLK, CS Input Capacitance
µA
±0.01
±1
I
IN
DIN, SCLK, CS Input Leakage
V
0.2
V
HYST
DIN, SCLK, CS Input Hysteresis
V
0.8
V
IL
DIN, SCLK, CS Input Low Voltage
2.0
µA
±4.0
I
S
SHDN Input Current
V
0.4
V
SL
SHDN Input Low Voltage
V
V
DD
- 0.4
V
SH
SHDN Input High Voltage
SHDN = 0V or V
DD
nA
±100
SHDN Maximum Allowed
Leakage, Mid Input
V
V
DD
/ 2
V
FLT
SHDN Voltage, Floating
SHDN = FLOAT
SHDN = FLOAT
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
(Note 7)
V
IN
= 0V or V
DD
V
DD
3.6V
I
DD
CONDITIONS
Positive Supply Current, MAX1246
µA
1.2
2.0
µA
±0.01
±10
I
L
Three-State Leakage Current
V
V
DD
- 0.5
V
OH
Output Voltage High
V
0.8
V
OL
Output Voltage Low
0.4
2.70
3.60
pF
15
C
OUT
Three-State Output Capacitance
MAX1246
CS = V
DD
(Note 7)
CS = V
DD
I
SOURCE
= 0.5mA
I
SINK
= 16mA
I
SINK
= 5mA
V
2.70
5.25
V
DD
Positive Supply Voltage
MAX1247
0.9
1.5
Operating mode,
full-scale input
30
70
V
DD
= 5.25V
V
DD
= 3.6V
3.5
15
V
DD
= 5.25V
V
DD
= 3.6V
1.2
10
Full power-down
mA
1.8
2.5
30
70
1.2
10
Operating mode, full-scale input
Fast power-down
Full power-down
mA
V
1.1
V
DD
- 1.1
V
SM
SHDN Input Mid Voltage
Fast power-down
I
DD
µA
Positive Supply Current, MAX1247
DIGITAL INPUTS
(DIN, SCLK, CS, SHDN)
DIGITAL OUTPUTS
(DOUT, SSTRB)
POWER REQUIREMENTS
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
_______________________________________________________________________________________
5
Figure 1
__________________________________________Typical Operating Characteristics
(V
DD
= 3.0V, VREF = 2.500V, f
SCLK
= 2.0MHz, C
LOAD
= 20pF, T
A
= +25°C, unless otherwise noted.)
0.5
0
1024
2048
3072
4096
INTEGRAL NONLINEARITY
vs. CODE
0.3
-0.3
-0.5
-0.1
0.1
0.4
0.2
-0.4
-0.2
0
MAX1247-01
CODE
INL (LSB)
0.50
0.00
2.25
2.75
4.25
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
V
DD
(V)
INL (LSB)
3.75
5.25
3.25
4.75
MAX1247-02
MAX1246
MAX1247
0.00
0.10
0.20
0.30
0.40
0.50
0.05
0.15
0.25
0.35
0.45
-60
-20
20
60
100
140
INTEGRAL NONLINEARITY
vs. TEMPERATURE
TEMPERATURE
(°C)
INL (LSB)
MAX1247-03
MAX1247
MAX1246
V
DD
= 2.7V
TIMING CHARACTERISTICS
(V
DD
= +2.7V to +3.6V (MAX1246); V
DD
= +2.7V to +5.25V (MAX1247); T
A
= T
MIN
to T
MAX
; unless otherwise noted.)
Note 1:
Tested at V
DD
= 2.7V; COM = 0V; unipolar single-ended input mode.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:
MAX1246--internal reference, offset nulled; MAX1247--external reference (VREF = +2.500V), offset nulled.
Note 4:
Ground "on" channel; sine wave applied to all "off" channels.
Note 5:
Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6:
The common-mode range for the analog inputs is from AGND to V
DD
.
Note 7:
Guaranteed by design. Not subject to production testing.
Note 8:
External load should not change during conversion for specified accuracy.
Note 9:
ADC performance is limited by the converter's noise floor, typically 300µVp-p.
Note 10:
Measured as
|
V
FS
(2.7V) - V
FS
(V
DD, MAX
)
|
.
Internal clock mode only (Note 7)
External clock mode only, Figure 2
External clock mode only, Figure 1
DIN to SCLK Setup
Figure 1
Figure 2
Figure 1
MAX124_ _C/E
CONDITIONS
MAX124_ _M
ns
20
240
Figure 1
ns
t
CSH
ns
240
t
STR
CS Rise to SSTRB Output Disable
ns
240
t
SDV
CS Fall to SSTRB Output Enable
240
t
SSTRB
SCLK Fall to SSTRB
ns
200
t
CL
SCLK Pulse Width Low
ns
200
SCLK Pulse Width High
ns
0
CS to SCLK Rise Hold
ns
100
t
CSS
CS to SCLK Rise Setup
ns
240
t
TR
CS Rise to Output Disable
ns
240
t
DV
CS Fall to Output Enable
t
CH
20
200
t
DO
SCLK Fall to Output Data Valid
ns
0
t
DH
DIN to SCLK Hold
ns
µs
1.5
t
ACQ
Acquisition Time
0
t
SCK
SSTRB Rise to SCLK Rise
ns
100
t
DS
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
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