General Description
The MAX1112/MAX1113 are low-power, 8-bit, 8-chan-
nel analog-to-digital converters (ADCs) that feature an
internal track/hold, voltage reference, clock, and serial
interface. They operate from a single +4.5V to +5.5V
supply and consume only 135µA while sampling at
rates up to 50ksps. The MAX1112's 8 analog inputs
and the MAX1113's 4 analog inputs are software-con-
figurable, allowing unipolar/bipolar and single-
ended/differential operation.
Successive-approximation conversions are performed
using either the internal clock or an external serial-inter-
face clock. The full-scale analog input range is deter-
mined by the 4.096V internal reference, or by an
externally applied reference ranging from 1V to V
DD
.
The 4-wire serial interface is compatible with the SPITM,
QSPITM, and MICROWIRETM serial-interface standards.
A serial-strobe output provides the end-of-conversion
signal for interrupt-driven processors.
The MAX1112/MAX1113 have a software-program-
mable, 2µA automatic power-down mode to minimize
power consumption. Using power-down, the supply
current is reduced to 13µA at 1ksps, and only 82µA at
10ksps. Power-down can also be controlled using the
SHDN input pin. Accessing the serial interface automat-
ically powers up the device.
The MAX1112 is available in 20-pin SSOP and DIP
packages. The MAX1113 is available in small 16-pin
QSOP and DIP packages.
________________________Applications
Portable Data Logging
Hand-Held Measurement Devices
Medical Instruments
System Diagnostics
Solar-Powered Remote Systems
420mA-Powered Remote
Data-Acquisition Systems
____________________________Features
o
+4.5V to +5.5V Single Supply
o
Low Power: 135µA at 50ksps
13µA at 1ksps
o
8-Channel Single-Ended or 4-Channel Differential
Inputs (MAX1112)
o
4-Channel Single-Ended or 2-Channel Differential
Inputs (MAX1113)
o
Internal Track/Hold; 50kHz Sampling Rate
o
Internal 4.096V Reference
o
SPI/QSPI/MICROWIRE-Compatible Serial Interface
o
Software-Configurable Unipolar or Bipolar Inputs
o
Total Unadjusted Error: ±1LSB (max)
±0.3LSB (typ)
MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
________________________________________________________________
Maxim Integrated Products
1
INPUT
SHIFT
REGISTER
CONTROL
LOGIC
INT
CLOCK
OUTPUT
SHIFT
REGISTER
+4.096V
REFERENCE
T/H
ANALOG
INPUT
MUX
8-BIT
SAR ADC
IN
DOUT
SSTRB
V
DD
DGND
AGND
SCLK
DIN
CH0
CH1
CH3
CH2
CH7*
CH6*
CH5*
CH4*
COM
REFOUT
*MAX1112 ONLY
REFIN
OUT
REF
CLOCK
MAX1112
MAX1113
CS
SHDN
Functional Diagram
19-1231; Rev 1; 10/98
PART
MAX1112
CPP
MAX1112CAP
0°C to +70°C
0°C to +70°C
TEMP. RANGE
PIN-PACKAGE
20 Plastic DIP
20 SSOP
EVALUATION KIT
AVAILABLE
Ordering Information
Ordering Information continued at end of data sheet.
*
Dice are specified at T
A
= +25°C, DC parameters only.
Pin Configurations appear at end of data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
MAX1112C/D
0°C to +70°C
Dice*
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
DD
to AGND ..............................................................-0.3V to 6V
AGND to DGND .......................................................-0.3V to 0.3V
CH0CH7, COM, REFIN,
REFOUT to AGND ...................................-0.3V to (V
DD
+ 0.3V)
Digital Inputs to DGND ...............................................-0.3V to 6V
Digital Outputs to DGND ............................-0.3V to (V
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
16 Plastic DIP (derate 10.53mW/°C above +70°C) ......842mW
16 QSOP (derate 8.30mW/°C above +70°C) ................667mW
16 CERDIP (derate 10.00mW/°C above +70°C) ..........800mW
20 Plastic DIP (derate 11.11mW/°C above +70°C) ......889mW
20 SSOP (derate 8.00mW/°C above +70°C) ................640mW
20 CERDIP (derate 11.11mW/°C above +70°C) ..........889mW
Operating Temperature Ranges
MAX1112C_P/MAX1113C_E................................0°C to +70°C
MAX1112E_P/MAX1113E_E .............................-40°C to +85°C
MAX1112MJP/MAX1113MJE..........................-55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
ELECTRICAL CHARACTERISTICS
(V
DD
= +4.5V to +5.5V; unipolar input mode; COM = 0V; f
SCLK
= 500kHz, external clock (50% duty cycle); 10 clocks/conversion
cycle (50ksps); 1µF capacitor at REFOUT; T
A
= T
MIN
to T
MAX
; unless otherwise noted.)
-3dB rolloff
MHz
1.5
Small-Signal Bandwidth
kHz
800
V
CH_
= 4.096Vp-p, 25kHz (Note 3)
External reference, 4.096V
No missing codes over temperature
CONDITIONS
Full-Power Bandwidth
±1
Internal or external reference
LSB
Gain Error (Note 2)
dB
-75
Channel-to-Channel Crosstalk
dB
68
SFDR
Spurious-Free Dynamic Range
dB
-70
THD
Total Harmonic Distortion
(up to the 5th harmonic)
LSB
±0.1
Channel-to-Channel
Offset Matching
ppm/°C
±0.8
Gain Temperature Coefficient
LSB
±1
DNL
Differential Nonlinearity
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
MAX111_C/E
LSB
±0.3
±1
TUE
Total Unadjusted Error
Bits
8
Resolution
dB
49
SINAD
Signal-to-Noise
and Distortion Ratio
LSB
±0.1
±0.5
INL
Relative Accuracy (Note 1)
LSB
±0.3
±1
Offset Error
DC ACCURACY
DYNAMIC SPECIFICATIONS
(10.034kHz sine-wave input, 4.096Vp-p, 50ksps, 500kHz external clock)
µA
MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +4.5V to +5.5V; unipolar input mode; COM = 0V; f
SCLK
= 500kHz, external clock (50% duty cycle); 10 clocks/conversion
cycle (50ksps); 1µF capacitor at REFOUT; T
A
= T
MIN
to T
MAX
; unless otherwise noted.)
On/off leakage current, V
CH_
= 0V or V
DD
Used for data transfer only
(Note 5)
External clock, 2MHz
CONDITIONS
ppm/°C
±50
mA
6
REFOUT Short-Circuit Current
pF
18
Input Capacitance
µA
±0.01
±1
Multiplexer Leakage Current
1
2
50
500
kHz
400
Internal Clock Frequency
0mA to 0.5mA output load
mV
4.5
Load Regulation (Note 7)
ns
10
Aperture Delay
µs
1
t
ACQ
Track/Hold Acquisition Time
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
ps
V
1
V
DD
+
50mV
Input Voltage Range
(Note 8)
µA
1
20
Input Current
<50
Aperture Jitter
External clock, 500kHz, 10 clocks/conversion
20
Internal clock
µs
25
55
t
CONV
Conversion Time (Note 4)
Bipolar input, COM = V
REFIN
/ 2
Unipolar input, COM = 0V
COM ±
V
REFIN
/ 2
V
0
V
REFIN
Input Voltage Range, Single-
Ended and Differential (Note 6)
V
3.936
4.096
4.256
REFOUT Voltage
External Clock-Frequency Range
MHz
kHz
Capacitive Bypass at REFOUT
µF
REFOUT Temperature Coefficient
V
4.5
5.5
V
DD
Supply Voltage
V
DD
= 4.5V to 5.5V; external reference,
4.096V; full-scale input
mV
±0.4
±4
PSR
Power-Supply Rejection
(Note 9)
2
Power-down
3.2
10
Software
SHDN at DGND
Operating mode
135
250
Full-scale input
C
LOAD
= 10pF
Reference disabled
95
I
DD
µA
Supply Current
CONVERSION RATE
ANALOG INPUT
INTERNAL REFERENCE
EXTERNAL REFERENCE AT REFIN
POWER REQUIREMENTS
MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +4.5V to +5.5V; unipolar input mode; COM = 0V; f
SCLK
= 500kHz, external clock (50% duty cycle); 10 clocks/conversion
cycle (50ksps); 1µF capacitor at REFOUT; T
A
= T
MIN
to T
MAX
; unless otherwise noted.)
CS = V
DD
(Note 5)
CS = V
DD
I
SOURCE
= 0.5mA
I
SINK
= 5mA
SHDN = open
SHDN = 0V or V
DD
(Note 5)
Digital inputs = 0V or V
DD
SHDN = open
CONDITIONS
pF
15
C
OUT
Three-State Output Capacitance
µA
±0.01
±10
I
L
Three-State Leakage Current
V
V
DD
- 0.5
V
OH
Output High Voltage
V
0.4
V
OL
Output Low Voltage
nA
±100
SHDN Maximum Allowed Leakage
for Mid-Input
V
V
DD
/ 2
V
FLT
SHDN Voltage, Floating
µA
±4
SHDN Input Current
V
V
DD
- 0.4
V
SH
SHDN Input High Voltage
V
0.8
V
IL
DIN, SCLK, CS Input Low Voltage
V
1.1
V
DD
- 1.1
I
SINK
= 16mA
V
SM
0.8
pF
15
C
IN
DIN, SCLK, CS Input Capacitance
µA
±1
I
IN
DIN, SCLK, CS Input Leakage
SHDN Input Mid-Voltage
V
0.2
V
HYST
DIN, SCLK, CS Input Hysteresis
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
V
0.4
V
SL
SHDN Input Low Voltage
V
V
IH
DIN, SCLK, CS Input High Voltage
3
DIGITAL INPUTS: DIN, SCLK,
CS
DIGITAL OUTPUTS: DOUT, SSTRB
SHDN
INPUT
MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
_______________________________________________________________________________________
5
ns
100
t
CSS
Figure 1, external clock mode only,
C
LOAD
= 100pF
ns
CS to SCLK Rise Setup
240
Figure 1, C
LOAD
= 100pF
ns
20
200
ns
0
t
CSH
CONDITIONS
CS to SCLK Rise Hold
240
t
DV
CS Fall to Output Enable
Figure 2, C
LOAD
= 100pF
ns
240
t
TR
CS Rise to Output Disable
t
SDV
CS Fall to SSTRB Output Enable
(Note 5)
Figure 2, external clock mode only,
C
LOAD
= 100pF
ns
240
t
STR
CS Rise to SSTRB Output
Disable (Note 5)
Figure 11, internal clock mode only
ns
0
t
SCK
SSTRB Rise to SCLK Rise
(Note 5)
ns
200
t
CH
SCLK Pulse Width High
ns
200
t
CL
SCLK Pulse Width Low
C
LOAD
= 100pF
ns
240
t
SSTRB
SCLK Fall to SSTRB
ns
0
t
DH
DIN to SCLK Hold
µs
1
t
ACQ
Track/Hold Acquisition Time
ns
100
t
DS
DIN to SCLK Setup
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
TIMING CHARACTERISTICS
(Figures 8 and 9)
(V
DD
= +4.5V to +5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Note 1:
Relative accuracy is the analog value's deviation (at any code) from its theoretical value after the full-scale range is calibrated.
Note 2:
V
REFIN
= 4.096V, offset nulled.
Note 3:
On-channel grounded; sine wave applied to all off-channels.
Note 4:
Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5:
Guaranteed by design. Not subject to production testing.
Note 6:
Common-mode range for the analog inputs is from AGND to V
DD
.
Note 7:
External load should not change during the conversion for specified accuracy.
Note 8:
External reference at 4.096V, full-scale input, 500kHz external clock.
Note 9:
Measured as
|
V
FS
(4.5V) - V
FS
(5.5V)
|
.
Note 10:
1µF at REFOUT; internal reference settling to 0.5LSB.
ns
20
240
t
DO
SCLK Fall to Output Data Valid
Figure 1,
C
LOAD
= 100pF
MAX111_C/E
MAX111_M
External reference
20
Internal reference (Note 10)
µs
24
t
WAKE
Wakeup Time
ms
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