1 of 18

091202

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here:

http://www.maxim-ic.com/errata

FEATURES

§ Integrated real-time clock (RTC), power-fail

control circuit, and NV RAM controller

§ Clock registers are accessed identically to the

static RAM; these registers are resident in the
16 top RAM locations

§ Century register
§ Greater than 10 years of timekeeping and data

retention in the absence of power with small
lithium coin cell(s) and low-leakage SRAM

§ Precision power-on reset
§ Programmable watchdog timer and RTC

alarm

§ BCD-coded year, month, date, day, hours,

minutes, and seconds with automatic leap-
year compensation valid up to the year 2100

§ Battery voltage-level indicator flag
§ Power-fail write protection allows for

10%

power-supply tolerance

§ Underwriters Laboratory (UL) recognized

ORDERING INFORMATION

PART

PIN-

PACKAGE

(V)

TOP

MARK

DS1558Y

48 TQFP

DS1558B

DS1558W

48 TQFP

3.3

DS1558D

PIN ASSIGNMENT (Top View)

Package Dimension Information

http://www.maxim-ic.com/TechSupport/DallasPackInfo.htm

PIN DESCRIPTION

A0A18

- Address Input

DQ0DQ7

- Data Input/Outputs

IRQ

\FT

- Interrupt, Frequency-Test

Output (Open Drain)

RST

- Power-On Reset Output

(Open Drain)

- Chip-Enable Input

CER

- Chip-Enable RAM

- Output-Enable Input

OER

- Output-Enable RAM

- Write Enable

- Power-Supply Input

CCO

- V

Out to RAM

GND

- Ground

N.C.

- No Connection

X1, X2

- Crystal Connection

BAT1

- +3V Battery Input

BAT2

- +3V Battery Input

DS1558

Watchdog Clock with

NV RAM Control

www.maxim-ic.com

A18

A16

A12

A4
A3

A2
A1

A14

N.C.

VCCO

1
2
3

4
5
6
7

VCC

N.C.

A17

GND

RST

N.C.

DQ0

DQ1 DQ

DQ6

VBAT1

IRQ/FT

A10

GND

VBAT

A15

A13

OER

A11

34
33

32
31
30
29

28
27
26

48 47

46 45 44 43

42 41 40 39

38 37

CER

DQ7

DQ5

DQ4

DQ3

GND

DS1558

N.C.

48-Pin TQFP

DS1558

2 of 18

TYPICAL OPERATING CIRCUIT

DESCRIPTION

The DS1558 is a full function, year 2000-compliant (Y2KC), real-time clock/calendar with an RTC
alarm, watchdog timer, power-on reset, battery monitor, and NV SRAM controller. User access to all
registers within the DS1558 is accomplished with a byte-wide interface as shown in Figure 1. The RTC
registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD
format. Corrections for day of month and leap year are made automatically.

The DS1558 maps the RTC registers into the SRAM address space and constantly monitors A0A18.
When any of the upper 16 address locations are accessed, the DS1558 inhibits

CER

and

OER

to the

SRAM, and redirects reads and writes to the RTC registers within the DS1558. The DS1558 can be used
with SRAMs up to 524,272 addresses. Smaller SRAMs can be used, provided that the unused upper
address lines on the DS1558 are connected to V

The RTC registers are double-buffered into an internal and external set. The user has direct access to the
external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow
the user to access static data. Assuming the internal oscillator is turned on, the internal set of registers is
continuously updated; this occurs regardless of external register settings to guarantee that accurate RTC
information is always maintained.

The DS1558 has interrupt (

IRQ

/FT) and reset (

RST

) outputs that can be used to control CPU activity.

The

IRQ

/FT interrupt output can be used to generate an external interrupt when the RTC register values

match user-programmed alarm values. The interrupt is always available while the device is powered from
the system supply, and it can be programmed to occur when in the battery-backed state to serve as a
system wake-up. The

IRQ

/FT output can also be used as a CPU watchdog timer. CPU activity is

monitored and an interrupt or reset output are activated if the correct activity is not detected within

DS1558

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programmed limits. The DS1558 power-on reset can be used to detect a system power-down or failure
and hold the CPU in a safe reset state until normal power returns and stabilizes; the

RST

output is used

for this function.

The DS1558 also contains its own power-fail circuitry, which automatically protects the data in the clock
and SRAM against out-of-tolerance V

CCI

conditions by inhibiting the

input when the V

supply

enters an out-of-tolerance condition. When V

CCI

goes below the level of V

BAT

, the external battery is

switched on to supply energy to the clock and the external SRAM. This feature provides a high degree of
data security during unpredictable system operation brought on by low V

levels.

Figure 1. BLOCK DIAGRAM

Note: Any unused upper address pins must be connected to V

to properly address the RTC.

SIGNAL DESCRIPTIONS

A0A18 Address inputs for address decode. The DS1558 uses the address inputs to determine whether
or not a read or write cycle should be directed to the attached SRAM or to the RTC registers.

DQ0DQ7 Data input/output pins for the RTC registers.

IRQ

/FT This pin is used to output the alarm interrupt or the frequency test signal. It is open drain and

requires an external pullup resistor.

DS1558

4 of 18

RST

This pin is an output used to signal that V

is out of tolerance. On power-up,

RST

is held low for

a period of time to allow the system to stabilize. The RTC and SRAM are not accessible while

RST

active. This pin is open drain and requires an external pullup resistor.

Chip-enable input that is used to access the RTC and the external SRAM.

CER

Chip-enable RAM output.

is passed through to

CER

, with an added propagation delay. When

the signals on A0A18 match an RTC address,

CER

is held high, disabling the SRAM. If

is also low,

the RTC outputs data on DQ0DQ7.

Output-enable input that is used to access the RTC and the external SRAM.

OER

Output-enable RAM output.

is passed through to

OER

, with an added propagation delay.

When the signals on A0A18 match an RTC address,

CER

is held high, disabling the SRAM. If

also low, the RTC outputs data on DQ0DQ7.

Write-enable input that is used to write data to the RTC registers.

, GND DC power is provided to the device on these pins. V

is the +5V input. When 5V (or 3.3V

for the 3.3V version) is applied within normal limits, the device is fully accessible and data can be written
and read. Reads and writes are inhibited when a 3V battery is connected to the device and V

is V

However, the timekeeping function continues unaffected by the lower input voltage. As V

falls below

BAT

, the RAM and RTC are switched over to the external power supply (nominal 3.0V DC) at V

BAT

CCO

output to RAM. While V

is above V

BAT

, the external SRAM is powered by V

. When

is below the battery level, the SRAM is powered by one of the V

BAT

inputs.

N.C. No internal connection.

X1, X2 Connections for a standard 32.768kHz quartz crystal. The internal oscillator circuitry is
designed for operation with a crystal having a specified load capacitance (C

) of 6pF. For more

information about crystal selection and crystal layout considerations, refer to Application Note 58
"Crystal Considerations with Dallas Real-Time Clocks." The DS1558 can also be driven by an external
32.768kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator signal and
the X2 pin is floated.

BAT1

, V

BAT2

Battery inputs for any standard 3V lithium cell or other energy source. Battery voltage

must be held between 2.5V and 3.7V for proper operation. UL recognized to ensure against reverse
charging current when used with a lithium battery. If only one battery is used, it should be attached to
V

BAT1

, and V

BAT2

should be grounded.

See "Conditions of Acceptability" at

http://www.maxim-ic.com/TechSupport/QA/ntrl.htm

DS1558

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Table 1. OPERATING MODES

DQ0DQ7

MODE

POWER

High-Z

Deselect

Standby

Write

Active

OUT

Read

Active

> V

High-Z

Read

Active

< V

High-Z

Deselect

CMOS Standby

< V

High-Z

Data Retention

Battery Current

DATA READ MODE

The DS1558 is in the read mode whenever

is low and

is high. The device architecture allows

ripple-through access to any valid address location. Valid data is available at the DQ pins within t

after

the last address input is stable, provided that

and

access times are satisfied. If

access

times are not met, valid data is available at the latter of chip-enable access (t

CEA

) or at output-enable

access time (t

OEA

). The state of the data input/output pins (DQ) is controlled by

and

. If the

outputs are activated before t

, the data lines are driven to an intermediate state until t

. If the address

inputs are changed while

and

remain valid, output data remains valid for output-data hold time

), but then goes indeterminate until the next address access.

DATA WRITE MODE

The DS1558 is in the write mode whenever

and

are in their active state. The start of a write is

referenced to the latter occurring transition of

. The addresses must be held valid throughout

the cycle.

and

must return inactive for a minimum of t

prior to the initiation of a subsequent

read or write cycle. Data in must be valid t

prior to the end of the write and remain valid for t

afterward. In a typical application, the

signal is high during a write cycle. However,

can be active

provided that care is taken with the data bus to avoid bus contention. If

is low prior to

transitioning low, the data bus can become active with read data defined by the address inputs. A low
transition on

then disables the outputs t

WEZ

after

goes active.

DATA RETENTION MODE

The 5V device is fully accessible and data can be written and read only when V

is greater than V

However, when V

is below the power-fail point V

(point at which write protection occurs), the

internal clock registers and SRAM are blocked from any access. When V

falls below the battery switch

point V

(battery supply level), device power is switched from the V

pin to the backup battery. RTC

operation and SRAM data are maintained from the battery until V

is returned to nominal levels.

The 3.3V device is fully accessible and data can be written and read only when V

is greater than V

When V

falls below V

, access to the device is inhibited. If V

is less than V

, the device power is

switched from V

to the internal backup lithium battery when V

drops below V

. If V

is greater

than V

, the device power is switched from V

to the internal backup lithium battery when V

drops

below V

. RTC operation and SRAM data are maintained from the battery until V

is returned to

nominal levels.

All control, data, and address signals must be powered down when V

is powered down.

DS1558

6 of 18

BATTERY LONGIVITY

The battery lifetime is dependent on the RAM battery standby current and the DS1558 internal clock
oscillator current. The total battery current is I

OSC

+ I

CCO

. When V

is above V

, I

BAT

current is less than

50nA. The DS1558 has an internal circuit to prevent battery charging. No external protection components
are required, and none should be used. The DS1558 has two battery pins that operate independently; the
DS1558 selects the higher of the two inputs. If only one battery is used, the battery should be attached to
V

BAT1

, and V

BAT2

should be grounded.

INTERNAL BATTERY MONITOR

The DS1558 constantly monitors the battery voltage of the internal battery. The battery-low flag (BLF)
bit of the flags register (B4 of 7FFF0h) is not writable and should always be a 0 when read. If a 1 is ever
present, both battery inputs are below 1.8V and both the contents of the RTC and RAM are questionable.

POWER-ON RESET

A temperature-compensated comparator circuit monitors the level of V

. When V

falls to the power-

fail trip point, the

RST

signal (open drain) is pulled low. When V

returns to nominal levels, the

RST

signal continues to be pulled low for a period of 40ms to 200ms. The power-on reset function is
independent of the RTC oscillator and thus is operational whether or not the oscillator is enabled.

DS1558

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CLOCK OPERATIONS

Table 2 and the following paragraphs describe the operation of the RTC, alarm, and watchdog functions.

Table 2. DS1558 REGISTER MAP

DATA

ADDRESS

FUNCTION/RANGE

7FFFFh

10 YEAR

YEAR

0099

7FFFEh

10 M

MONTH

0112

7FFFDh

10 DATE

DATE

0131

7FFFCh

DAY

0107

7FFFBh

10 HOUR

HOUR

0023

7FFFAh

10 MINUTES

MINUTES

0059

7FFF9h

OSC

10 SECONDS

SECONDS

0059

7FFF8h

10 CENTURY

CENTURY

CONTROL

0039

7FFF7h

WDS

BMB4

BMB3

BMB2

BMB1

BMB0

RB1

RB0

WATCHDOG

7FFF6h

ABE

INTERRUPTS

7FFF5h

AM4

10 DATE

DATE

ALARM DATE

0131

7FFF4h

AM3

10 HOURS

HOURS

ALARM HOURS

0023

7FFF3h

AM2

10 MINUTES

MINUTES

ALARM MINUTES

0059

7FFF2h

AM1

10 SECONDS

SECONDS

ALARM SECONDS

0059

7FFF1h

UNUSED

7FFF0h

BLF

FLAGS

X = Unused, Read/Writeable Under Write and Read Bit Control

AE = Alarm Flag Enable

FT = Frequency Test Bit

Y = Unused, Read/Writeable Without Write and Read Bit Control

OSC = Oscillator Start/Stop Bit

ABE = Alarm in Backup-Battery Mode Enable

W = Write Bit

AM1AM4 = Alarm Mask Bits

R = Read Bit

WF = Watchdog Flag

WEN = Watchdog Enable Bit

AF = Alarm Flag

BMB0BMB4 = Watchdog Multiplier Bits

0 = Reads as a 0 and Cannot Be Changed

RB0RB1 = Watchdog Resolution Bits

BLF = Battery Low Flag

CLOCK OSCILLATOR CONTROL

The oscillator can be turned off to minimize current drain from the battery. The

OSC

bit is the MSB of

the seconds register (B7 of 7FFF9h). Setting

OSC

to a 1 stops the oscillator; setting to a 0 starts the

oscillator. The initial state of

OSC

is not guaranteed. When power is applied for the first time, the

OSC

bit should be enabled. Oscillator operation and frequency can be verified by setting the FT bit and
monitoring the

IRQ

/FT pin for 512Hz.

OSCILLATOR STARTUP TIME

Oscillator startup times are highly dependent upon crystal characteristics and layout. High ESR and
excessive capacitive loads are the major contributors to long startup times. A circuit using a crystal with
the recommended characteristics and following the recommended layout usually starts within 1 second.

DS1558

8 of 18

READING THE CLOCK

When reading the RTC data, it is recommended to halt updates to the external set of double-buffered
RTC registers. This puts the external registers into a static state, allowing data to be read without register
values changing during the read process. Normal updates to the internal registers continue while in this
state. External updates are halted when a 1 is written into the read bit, B6 of the control register
(7FFF8h). As long as a 1 remains in the control register read bit, updating is halted. After a halt is issued,
the registers reflect the RTC count (day, date, and time) that was current at the moment the halt command
is issued. Normal updates to the external set of registers resume within 1 second after the read bit is set to
a 0 for a minimum of 500

ms. The read bit must be a 0 for a minimum of 500ms to ensure the external

registers are updated.

SETTING THE CLOCK

The MSB bit, B7, of the control register is the write bit. Setting the write bit to a 1, like the read bit, halts
updates to the 7FFF8h7FFFFh registers. After setting the write bit to a 1, RTC registers can be loaded
with the desired RTC count (day, date, and time) in 24-hour BCD format. Setting the write bit to a 0 then
transfers the values written to the internal RTC registers and allows normal operation to resume.

CLOCK ACCURACY

The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match
between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was
trimmed. Additional error is added by the crystal-frequency drift caused by temperature shifts. External
circuit noise coupled into the oscillator circuit can result in the clock running fast. Refer to Application
Note 58 "Crystal Considerations with Dallas Real-Time Clocks" for detailed information.

FREQUENCY TEST MODE

The DS1558 frequency test mode uses the open-drain

IRQ

/FT output. With the oscillator running, the

IRQ

/FT output toggles at 512Hz when the FT bit is a 1, the alarm-flag enable bit (AE) is a 0, and the

watchdog-enable bit (WDS) is a 1, or the watchdog register is reset (register 7FFF7h = 00h). The

IRQ

/FT

output and the frequency test mode can be used as a measure of the actual frequency of the 32.768kHz
RTC oscillator. The

IRQ

/FT pin is an open-drain output that requires a pullup resistor for proper

operation. The FT bit is cleared to a 0 on power-up.

USING THE CLOCK ALARM

The alarm settings and control for the DS1558 reside within registers 7FFF2h7FFF5h. Register 7FFF6h
contains two alarm-enable bits: alarm enable (AE) and alarm in backup enable (ABE). The AE and ABE
bits must be set as described below for the

IRQ

/FT output to be activated for a matched alarm condition.

The alarm can be programmed to activate on a specific day of the month or repeat every day, hour,
minute, or second. It can also be programmed to go off while the DS1558 is in the battery-backed state of
operation to serve as a system wake-up. Alarm mask bits AM1AM4 control the alarm mode. Table 3
shows the possible settings. Configurations not listed in the table default to the once-per-second mode to
notify the user of an incorrect alarm setting.

DS1558

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Table 3. ALARM MASK BITS

AM4

AM3

AM2

AM1

ALARM RATE

Once per second

When seconds match

When minutes and seconds match

When hours, minutes, and seconds match

When date, hours, minutes, and seconds match

When the RTC register values match alarm register settings, AF is set to a 1. If AE is also set to a 1, the
alarm condition activates the

IRQ

/FT pin. The

IRQ

/FT signal is cleared by a read or write to the flags

is active, the

IRQ

/FT signal can be cleared by having the address

stable for as short as 15ns and either

active, but is not guaranteed to be cleared unless t

fulfilled (Figure 2). Once the address has been selected for at least 15ns, the

IRQ

/FT signal can be cleared

immediately, but is not guaranteed to be cleared until t

is fulfilled (Figure 3). The alarm flag is also

cleared by a read or write to the flags register, but the flag does not change states until the end of the
read/write cycle and the

IRQ

/FT signal has been cleared.

The

IRQ

/FT pin can also be activated in the battery-backed mode. The

IRQ

/FT goes low if an alarm

occurs and both ABE and AE are set. The ABE and AE bits are cleared during the power-up transition,
but an alarm generated during power-up sets AF. Therefore, the AF bit can be read after system power-up
to determine if an alarm was generated during the power-up sequence. Figure 4 illustrates alarm timing
during the backup-battery mode and power-up states.

Figure 2. CLEARING IRQ WAVEFORMS ACTIVE

Figure 3. CLEARING IRQ WAVEFORMS

DS1558

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Figure 4. BACKUP MODE ALARM WAVEFORMS

USING THE WATCHDOG TIMER

The watchdog timer can be used to detect an out-of-control processor. The user programs the watchdog
timer by setting the desired amount of timeout into the 8-bit watchdog register (address 7FFF7h). The
five watchdog register bits BMB4BMB0 store a binary multiplier and the two lower-order bits
RB1RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and
11 = 4 seconds. The watchdog timeout value is then determined by the multiplication of the 5-bit
multiplier value with the 2-bit resolution value. (For example: writing 00001110 in the watchdog register
= 3 x 1 second or 3 seconds.) If the processor does not reset the timer within the specified period, the
watchdog flag (WF) is set and a processor interrupt is generated and stays active until either WF is read
or the watchdog register (7FFF7h) is read or written.

The MSB of the watchdog register is the watchdog steering bit (WDS). When set to a 0, the watchdog
activates the

IRQ

/FT output when the watchdog times out. WDS should not be written to a 1, and should

be initialized to a 0 if the watchdog function is enabled.

The watchdog timer resets when the processor performs a read or write of the watchdog register. The
timeout period then starts over. The watchdog timer is disabled by writing a value of 00h to the watchdog
register. The watchdog function is automatically disabled upon power-up and the watchdog register is
cleared.

POWER-ON DEFAULT STATES

Upon application of power to the device, the following register bits are set to a 0:

WDS = 0, BMB0BMB4 = 0, RB0RB1 = 0, AE = 0, and ABE = 0

All other bits are undefined.

DS1558

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ABSOLUTE MAXIMUM RATINGS*

Voltage Range on Any Pin Relative to Ground

-0.3V to +6.0V

Storage Temperature Range

-55

°C to +125°C

Soldering Temperature Range

See IPC/JEDEC J-STD-020A

*This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.

RECOMMENDED DC OPERATING CONDITIONS

= 3.3V ą10% or 5V ą10%, T

= -40°C to +85°C)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Logic 1 Voltage (All Inputs)

= +5V

ą10%

2.2

+ 0.3V

= +3.3V

ą10%

2.0

+ 0.3V

Logic 0 Voltage (All Inputs)

= +5V

ą10%

-0.3

+0.8

= +3.3V

ą10%

-0.3

+0.6

Battery Voltage

BAT

2.5

3.3

3.7

DS1558

12 of 18

DC ELECTRICAL CHARACTERISTICS

(

= +3.3V ą10% or +5V ą10%, T

= -40°C to +85°C)

PARAMETER

SYMBOL

MIN

TYP

MAX UNITS NOTES

Active Supply Current, +5V

2, 3

Active Supply Current, +3.3V

2, 3

TTL Standby, +5V (

= V

)

CC1

2, 3

TTL Standby, +3.3V (

= V

)

CC1

2, 3

CMOS Standby Current, +5V
(

ł V

- 0.2V)

CC2

2, 3

CMOS Standby Current, +3.3V
(

ł V

- 0.2V)

CC2

2, 3

Input Leakage Current
(Any Input)

-1

Output Leakage Current
(Any Output)

-1

Output Logic 1 Voltage
(I

OUT

= -1.0mA)

2.4

Output Logic 0 Voltage

OUT

= 2.1mA, DQ0DQ7

Outputs

OL1

0.4

OUT

= 7.0mA,

IRQ

/FT and

RST

Outputs

OL2

0.4

1, 5

Write Protection Voltage, +5V

4.25

4.37

4.50

Write Protection Voltage, +3.3V

2.80

2.88

2.97

Battery Switchover Voltage, +5V

BAT

Battery Switchover Voltage, +3.3V

1, 4

Battery Current OSC On

OSC

0.3

0.5

ľA

6,7

Battery Current OSC Off

BACKUP

100

Output Voltage I

CCO

= 70mA, +5V

CC01

CC1

- 0.3

Output Voltage I

CCO

= 40mA, +3.3V

CC01

CC1

- 0.3

Output Voltage I

CCO

= 10ľA

CC02

BAT

- 0.2

BAT

- 0.031

CRYSTAL SPECIFICATIONS

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

Nominal Frequency

32.768

kHz

Series Resistance

ESR

Load Capacitance

*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58 "Crystal Considerations

for Dallas Real-Time Clocks" for additional specifications.

DS1558

13 of 18

READ CYCLE, AC CHARACTERISTICS

= +3.3V ą10% or +5V ą10%, T

= -40°C to +85°C)

= +5.5V ą10%

= +3.3V ą10%

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS NOTES

Read Cycle Time

120

Address Access Time

120

to DQ Low-Z

CEL

Access Time

CEA

120

Data Off Time

CEZ

to DQ Low-Z

OEL

Access Time

OEA

100

Data Off Time

OEZ

Output Hold from
Address

CER

Propagation

Delay, +5V

CEPD

OER

Propagation

Delay, +5V

OEPD

CER

Propagation

Delay, +3.3V

CEPD

OER

Propagation

Delay, +3.3V

OEPD

Figure 5. READ CYCLE TIMING DIAGRAM

DS1558

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WRITE CYCLE, AC CHARACTERISTICS

(

= +3.3V ą10% or +5V ą10%, T

= -40°C to +85°C)

= +5.0V ą10%

= +3.3V ą10%

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS NOTES

Write Cycle Time

120

Address Access Time

Pulse Width

WEW

100

Pulse Width

CEW

110

Data Setup Time

Data Hold Time

DH1

Data Hold Time

DH2

Address Hold Time

AH1

Address Hold Time

AH2

Data Off Time

WEZ

Write Recovery Time

Figure 6. WRITE CYCLE TIMING, WRITE-ENABLE CONTROLLED

DS1558

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POWER-UP/DOWN CHARACTERISTICS

= +3.3V

10%,

= -40°C to +85°C

)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

at V

Before Power-Down

Fall Time: V

PF(MAX)

to V

PF(MIN)

300

Rise Time: V

PF(MIN)

to V

PF(MAX)

RST

High

REC

200

Figure 9. +3.3V POWER-UP/DOWN WAVEFORM TIMING

CAPACITANCE

(

= +25

°C

)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Capacitance On All Input Pins

Capacitance On

IRQ

/FT,

RST

, and

DQ Pins

DS1558

18 of 18

AC TEST CONDITIONS

Output Load:

25pF

Input Pulse Levels:

0V to +3V

Timing Measurement Reference Levels:

Input: +1.5V
Output: +1.5V

Input Pulse Rise and Fall Times: 5ns

NOTES:

1) Voltage referenced to ground.
2) Typical values are at +25

°C and nominal supplies.

3) Outputs are open.
4) Battery switchover occurs at the lower of either the battery voltage or V

5) The

IRQ

/FT and

RST

outputs are open drain.

6) Using the recommended crystal on X1 and X2.
7) V

CCO

CER

, and

OER

pins open.

8) t

AH1

, t

DH1

are measured from WE going high.

9) t

AH2

, t

DH2

are measured from CE going high.

10) Typical measured with V

BAT

at 3.0V. Typical with I

CCO

= 100ľA and V

BAT

= 3.0V is V

BAT

- 0.322.

Part Number DS1558