ChipFind - Datasheet

Part Number DS1265Y

Download:  PDF   ZIP
1 of 8
110602
FEATURES
§ 10 years minimum data retention in the
absence of external power
§ Data is automatically protected during power
loss
§ Unlimited write cycles
§ Low-power CMOS operation
§ Read and write access times as fast as 70 ns
§ Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
§ Full ±10% V
CC
operating range (DS1265Y)
§ Optional ±5% V
CC
operating range
(DS1265AB)
§ Optional industrial temperature range of
-40
°C to +85°C, designated IND
PIN ASSIGNMENT
PIN DESCRIPTION
A0 - A19
- Address Inputs
DQ0 - DQ7
- Data In/Data Out
CE
- Chip Enable
WE
- Write Enable
OE
- Output Enable
V
CC
- Power (+5V)
GND -
Ground
NC
- No Connect
DESCRIPTION
The DS1265 8M Nonvolatile SRAMs are 8,388,608-bit, fully static nonvolatile SRAMs organized as
1,048,576 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control
circuitry which constantly monitors V
CC
for an out-of-tolerance condition. When such a condition occurs,
the lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. There is no limit on the number of write cycles which can be executed and no
additional support circuitry is required for microprocessor interfacing.
DS1265Y/AB
8M Nonvolatile SRAM
www.maxim-ic.com
13
1
2
3
4
5
6
7
8
9
10
11
12
14
35
36-Pin ENCAPSULATED PACKAGE
740-mil EXTENDED
A18
A14
A7
A6
A5
A4
A3
A2
A0
A1
V
CC
A19
NC
A15
A17
WE
A13
A8
A9
A11
OE
A10
DQ7
CE
36
34
33
32
31
30
29
28
27
26
25
23
24
NC
A16
A12
NC
DQ0
DQ1
15
16
22
21
DQ6
DQ5
17
18
GND
DQ2
DQ3
DQ4
19
20
DS1265Y/AB
2 of 8
READ MODE
The DS1265 devices execute a read cycle whenever
WE
(Write Enable) is inactive (high) and
CE
(Chip
Enable) and
OE
(Output Enable) are active (low). The unique address specified by the 20 address inputs
(A
0
- A
19
) defines which of the 1,048,576 bytes of data is accessed. Valid data will be available to the
eight data output drivers within t
ACC
(Access Time) after the last address input signal is stable, providing
that
CE
and
OE
(Output Enable) access times are also satisfied. If
OE
and
CE
access times are not
satisfied, then data access must be measured from the later-occurring signal (
CE
or
OE
) and the limiting
parameter is either t
CO
for
CE
or t
OE
for
OE
rather than t
ACC
.
WRITE MODE
The DS1265 devices execute a write cycle whenever
WE
and
CE
signals are active (low) after address
inputs are stable. The later-occurring falling edge of
CE
or
WE
will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of
CE
or
WE
. All address inputs must be kept
valid throughout the write cycle.
WE
must return to the high state for a minimum recovery time (t
WR
)
before another cycle can be initiated. The
OE
control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled (
CE
and
OE
active) then
WE
will disable the outputs in t
ODW
from its falling edge.
DATA RETENTION MODE
The DS1265AB provides full functional capability for V
CC
greater than 4.75 volts and write protects by
4.5 volts. The DS1265Y provides full functional capability for V
CC
greater than 4.5 volts and write
protects by 4.25 volts. Data is maintained in the absence of V
CC
without any additional support circuitry.
The nonvolatile static RAMs constantly monitor V
CC
. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become don't care, and all outputs become high-
impedance. As V
CC
falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when V
CC
rises above approximately 3.0 volts,
the power switching circuit connects external V
CC
to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after V
CC
exceeds 4.75 volts for the DS1265AB and 4.5 volts for the
DS1265Y.
FRESHNESS SEAL
Each DS1265 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When V
CC
is first applied at a level greater than V
TP
, the lithium
energy source is enabled for battery backup operation.
DS1265Y/AB
3 of 8
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
-0.3V to +7.0V
Operating Temperature
0°C to 70°C; -40°C to +85°C for IND parts
Storage Temperature
-40°C to +70°C; -40°C to +85°C for IND parts
Soldering Temperature
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(
t
A
: See Note 10
)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
DS1265AB Power Supply Voltage
V
CC
4.75
5.0
5.25
V
DS1265Y Power Supply Voltage
V
CC
4.5
5.0
5.5
V
Logic 1 Input Voltage
V
IH
2.2
V
CC
V
Logic 0 Input Voltage
V
IL
0
+0.8
V
DC ELECTRICAL (V
CC
=5V
± 5% for DS1265AB)
CHARACTERISTICS (t
A
: See Note 10) (V
CC
=5V
± 10% for DS1265Y)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Input Leakage Current
I
IL
-2.0
+2.0
mA
I/O Leakage Current
I
IO
-2.0
+2.0
mA
Output Current @ 2.4V
I
OH
-1.0
mA
Output Current @ 0.4V
I
OL
2.0
mA
Standby Current
CE
=2.2V
I
CCS1
1.0
1.5
mA
Standby Current
CE
=V
CC
-0.5V
I
CCS2
100
200
mA
Operating Current
I
CCO1
85
mA
Write Protection Voltage (DS1265AB)
V
TP
4.50
4.62
4.75
V
Write Protection Voltage (DS1265Y)
V
TP
4.25
4.37
4.5
V
CAPACITANCE
(
t
A
=25
°
C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Input Capacitance
C
IN
10
20
pF
Output Capacitance
C
I/O
10
20
pF
DS1265Y/AB
4 of 8
AC ELECTRICAL (V
CC
=5V
± 5% for DS1265AB)
CHARACTERISTICS (t
A
: See Note 10) (V
CC
=5V
± 10% for DS1265Y)
DS1265AB-70
DS1265Y-70
DS1265AB-100
DS1265Y-100
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS NOTES
Read Cycle Time
t
RC
70
100
ns
Access Time
t
ACC
70
100
ns
OE
to Output Valid
t
OE
35
50
ns
CE
to Output Valid
t
CO
70
100
ns
OE
or
CE
to Output Active
t
COE
5
5
ns
5
Output High Z from Deselection
t
OD
25
35
ns
5
Output Hold from Address Change
t
OH
5
5
ns
Write Cycle Time
t
WC
70
100
ns
Write Pulse Width
t
WP
55
75
ns
3
Address Setup Time
t
AW
0
0
ns
Write Recovery Time
t
WR1
t
WR2
5
15
5
15
ns
ns
12
13
Output High Z from
WE
t
ODW
25
35
ns
5
Output Active from
WE
t
OEW
5
5
ns
5
Data Setup Time
t
DS
30
40
ns
4
Data Hold Time
t
DH1
t
DH2
0
10
0
10
ns
ns
12
13
TIMING DIAGRAM: READ CYCLE
SEE NOTE 1
DS1265Y/AB
5 of 8
TIMING DIAGRAM:
WRITE CYCLE 1
TIMING DIAGRAM: WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8 AND 13