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Part Number DS1249Y/AB

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110602
FEATURES
§ 10 years minimum data retention in the
absence of external power
§ Data is automatically protected during power
loss
§ Unlimited write cycles
§ Low-power CMOS operation
§ Read and write access times as fast as 70 ns
§ Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
§ Full ± 10% V
CC
operating range (DS1249Y)
§ Optional ± 5% V
CC
operating range
(DS1249AB)
§ Optional industrial temperature range of
-40
°C to +85°C, designated IND
§ JEDEC standard 32-pin DIP package
PIN ASSIGNMENT
PIN DESCRIPTION
A0 - A17
- Address Inputs
DQ0 - DQ7
- Data In/Data Out
CE
- Chip Enable
WE
- Write Enable
OE
- Output Enable
V
CC
- Power (+5V)
GND -
Ground
NC
- No Connect
DESCRIPTION
The DS1249 2048k Nonvolatile SRAMs are 2,097,152-bit, fully static, nonvolatile SRAMs organized as
262,144 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry
which constantly monitors V
CC
for an out-of-tolerance condition. When such a condition occurs, the
lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. There is no limit on the number of write cycles which can be executed and no
additional support circuitry is required for microprocessor interfacing.
DS1249Y/AB
2048k Nonvolatile SRAM
www.maxim-ic.com
13
1
2
3
4
5
6
7
8
9
10
11
12
14
31
32-Pin ENCAPSULATED PACKAGE
740-mil EXTENDED
A14
A7
A5
A4
A3
A2
A1
A0
DQ1
DQ0
V
CC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ5
DQ6
32
30
29
28
27
26
25
24
23
22
21
19
20
A16
A12
A6
NC
DQ2
GND
15
16
18
17
DQ4
DQ3
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DS1249Y/AB
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READ MODE
The DS1249 devices execute a read cycle whenever
WE
(Write Enable) is inactive (high) and
CE
(Chip
Enable) and
OE
(Output Enable) are active (low). The unique address specified by the 18 address inputs
(A
0
- A
17
) defines which of the 262,144 bytes of data is accessed. Valid data will be available to the eight
data output drivers within t
ACC
(Access Time) after the last address input signal is stable, providing that
CE
and
OE
access times are also satisfied. If
OE
and
CE
access times are not satisfied, then data access
must be measured from the later-occurring signal (
CE
or
OE
) and the limiting parameter is either t
CO
for
CE
or t
OE
for
OE
rather than t
ACC
.
WRITE MODE
The DS1249 executes a write cycle whenever the
WE
and
CE
signals are active (low) after address
inputs are stable. The later-occurring falling edge of
CE
or WE will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of
CE
or
WE
. All address inputs must be kept
valid throughout the write cycle.
WE
must return to the high state for a minimum recovery time (t
WR
)
before another cycle can be initiated. The
OE
control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled (
CE
and
OE
active) then
WE
will disable the outputs in t
ODW
from its falling edge.
DATA RETENTION MODE
The DS1249AB provides full functional capability for V
CC
greater than 4.75 volts and write protects by
4.5 volts. The DS1249Y provides full-functional capability for V
CC
greater than 4.5 volts and write
protects by 4.25 volts. Data is maintained in the absence of V
CC
without any additional support circuitry.
The nonvolatile static RAMs constantly monitor V
CC
. Should the supply voltage decay, the NV SRAMs
automatically write protects themselves, all inputs become "don't care," and all outputs become high
impedance. As V
CC
falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when V
CC
rises above approximately 3.0 volts,
the power switching circuit connects external V
CC
to the RAM and disconnects the lithium energy source.
Normal RAM operation can resume after V
CC
exceeds 4.75 volts for the DS1249AB and 4.5 volts for the
DS1249Y.
FRESHNESS SEAL
Each DS1249 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When V
CC
is first applied at a level greater than V
TP
, the lithium
energy source is enabled for battery backup operation.
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DS1249Y/AB
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ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
-0.3V to +7.0V
Operating Temperature
0°C to 70°C, -40°C to +85°C for IND parts
Storage Temperature
-40°C to +70°C, -40°C to +85°C for IND parts
Soldering Temperature
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(t
A
: See Note 10)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
DS1249AB Power Supply Voltage
V
CC
4.75
5.0
5.25
V
DS1249Y Power Supply Voltage
V
CC
4.5
5.0
5.5
V
Logic 1
V
IH
2.2
V
CC
V
Logic 0
V
IL
0.0
0.8
V
DC ELECTRICAL (V
CC
=5V
± 5% for DS1249AB)
CHARACTERISTICS (t
A
: See Note 10) (V
CC
=5V
± 10% for DS1249Y)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Input Leakage Current
I
IL
-2.0
+2.0
mA
I/O Leakage Current
CE
³ V
IH
£ V
CC
I
IO
-2.0
+2.0
mA
Output Current @ 2.4V
I
OH
-1.0
mA
Output Current @ 0.4V
I
OL
2.0
mA
Standby Current
CE
=2.2V
I
CCS1
1.0
1.5
mA
Standby Current
CE
=V
CC
-0.5V
I
CCS2
100
150
mA
Operating Current
I
CCO1
85
mA
Write Protection Voltage (DS1249AB)
V
TP
4.50
4.62
4.75
V
Write Protection Voltage (DS1249Y)
V
TP
4.25
4.37
4.5
V
CAPACITANCE
(
t
A
=25
°
C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Input Capacitance
C
IN
10
20
pF
Input/Output Capacitance
C
I/O
10
20
pF
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DS1249Y/AB
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AC ELECTRICAL (V
CC
=5V
± 5% for DS1249AB)
CHARACTERISTICS (t
A
: See Note 10) (V
CC
=5V
± 10% for DS1249Y)
DS1249AB-70
DS1249Y-70
DS1249AB-100
DS1249Y-100
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS NOTES
Read Cycle Time
t
RC
70
100
ns
Access Time
t
ACC
70
100
ns
OE
to Output Valid
t
OE
35
50
ns
CE
to Output Valid
t
CO
70
100
ns
OE
or
CE
to Output Active
t
COE
5
5
ns
5
Output High Z from Deselection
t
OD
25
35
ns
5
Output Hold from Address Change
t
OH
5
5
ns
Write Cycle Time
t
WC
70
100
ns
Write Pulse Width
t
WP
55
75
ns
3
Address Setup Time
t
AW
0
0
ns
Write Recovery Time
t
WR1
t
WR2
5
15
5
15
ns
ns
12
13
Output High Z from
WE
t
ODW
25
35
ns
5
Output Active from
WE
t
OEW
5
5
ns
5
Data Setup Time
t
DS
30
40
ns
4
Data Hold Time
t
DH1
t
DH2
0
10
0
10
ns
ns
12
13
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DS1249Y/AB
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READ CYCLE
SEE NOTE 1
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8, and 12