LTC3412A
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APPLICATIO S
U
DESCRIPTIO
U
FEATURES
TYPICAL APPLICATIO
U
Point-of-Load Regulation
Notebook Computers
Portable Instruments
Distributed Power Systems
High Efficiency: Up to 95%
3A Output Current
Low Quiescent Current: 64
µA
Low R
DS(ON)
Internal Switch: 77m
2.25V to 5.5V Input Voltage Range
Programmable Frequency: 300KHz to 4MHz
±2% Output Voltage Accuracy
0.8V Reference Allows Low Output Voltage
Selectable Forced Continuous/Burst Mode
®
operation
with Adjustable Burst Clamp
Synchronizable Switching Frequency
Low Dropout Operation: 100% Duty Cycle
Power Good Output Voltage Monitor
Overtemperature Protected
Available in 16-Lead Exposed Pad TSSOP and QFN
Packages
3A, 4MHz, Monolithic
Synchronous Step-Down Regulator
The LTC
®
3412A is a high efficiency monolithic synchro-
nous, step-down DC/DC converter utilizing a constant
frequency, current mode architecture. It operates from an
input voltage range of 2.25V to 5.5V and provides a
regulated output voltage from 0.8V to 5V while delivering
up to 3A of output current. The internal synchronous
power switch with 77m
on-resistance increases effi-
ciency and eliminates the need for an external Schottky
diode. Switching frequency is set by an external resistor or
can be synchronized to an external clock. 100% duty cycle
provides low dropout operation extending battery life in
portable systems. OPTI-LOOP
®
compensation allows the
transient response to be optimized over a wide range of
loads and output capacitors.
The LTC3412A can be configured for either Burst Mode
operation or forced continuous operation. Forced continu-
ous operation reduces noise and RF interference while
Burst Mode operation provides high efficiency by reduc-
ing gate charge losses at light loads. In Burst Mode
operation, external control of the burst clamp level allows
the output voltage ripple to be adjusted according to the
application requirements.
3412A F01a
SYNC/MODE
V
FB
PGOOD
SW
PGND
SGND
RT
RUN/SS
I
TH
SV
IN
PV
IN
LTC3412A
294k
22
µF
C
OUT
100
µF
×2
0.47
µH
V
OUT
2.5V AT 3A
V
IN
3.3V
1000pF
2.2M
820pF
12.1k
115k
69.8k
392k
Efficiency and Power Loss
Figure 1. 2.5V/3A Step-Down Regulator
LOAD CURRENT (A)
0.01
EFFICIENCY (%)
POWER LOSS (mW)
100
95
90
85
80
75
70
65
60
55
50
100000
10000
1000
100
10
1
0.1
1
10
!" ) .>
EFFICIENCY
POWER LOSS
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815, 6498466,
6611131, 6724174.
LTC3412A
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SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SV
IN
Signal Input Voltage Range
2.25
5.5
V
V
FB
Regulated Feedback Voltage
(Note 3)
0.784
0.800
0.816
V
I
FB
Voltage Feedback Leakage Current
0.1
0.2
µA
V
FB
Reference Voltage Line Regulation
V
IN
= 2.7V to 5.5V (Note 3)
0.04
0.2
%/V
V
LOADREG
Output Voltage Load Regulation
Measured in Servo Loop, V
ITH
= 0.36V
0.02
0.2
%
Measured in Servo Loop, V
ITH
= 0.84V
0.02
0.2
%
V
PGOOD
Power Good Range
±7.5
±9
%
R
PGOOD
Power Good Pull-Down Resistance
120
200
I
Q
Input DC Bias Current
(Note 4)
Active Current
V
FB
= 0.78V, V
ITH
= 1V
250
330
µA
Sleep
V
FB
= 1V, V
ITH
= 0V
64
80
µA
Shutdown
V
RUN
= 0V, V
MODE
= 0V
0.02
1
µA
Input Supply Voltage ................................... 0.3V to 6V
I
TH
, RUN/SS, V
FB
, PGOOD,
SYNC/MODE Voltages .................................. 0.3 to V
IN
SW Voltages ................................. 0.3V to (V
IN
+ 0.3V)
ABSOLUTE AXI U
RATI GS
W
W
W
U
PACKAGE/ORDER I FOR ATIO
U
U
W
(Note 1)
ELECTRICAL CHARACTERISTICS
The
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
°C. V
IN
= 3.3V unless otherwise specified.
Operating Ambient Temperature Range
(Note 2) .............................................. 40
°C to 85°C
Junction Temperature (Note 5) ............................. 125
°C
Lead Temperature (Soldering, 10 sec).................. 300
°C
T
JMAX
= 125
°C,
JA
= 38
°C/W,
JC
= 10
°C/W
ORDER PART NUMBER
FE PART MARKING
Consult LTC Marketing for parts specified with wider operating temperature ranges.
LTC3412AEFE
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking:
http://www.linear.com/leadfree/
3412AEFE
ORDER PART NUMBER
UF PART MARKING
LTC3412AEUF
3412A
T
JMAX
= 125
°C,
JA
= 34
°C/W,
JC
= 1
°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE CONNECTED TO PCB
1
2
3
4
5
6
7
8
TOP VIEW
FE PACKAGE
16-LEAD PLASTIC TSSOP
EXPOSED PAD IS SGND (PIN 17) MUST BE SOLDERED TO PCB
16
15
14
13
12
11
10
9
SV
IN
PGOOD
I
TH
V
FB
R
T
SYNC/MODE
RUN/SS
SGND
PV
IN
SW
SW
PGND
PGND
SW
SW
PV
IN
17
16 15 14 13
5
6
7
8
TOP VIEW
UF PACKAGE
16-LEAD (4mm
× 4mm) PLASTIC QFN
9
10
11
12
4
3
2
1
RUN/SS
SGND
PV
IN
SW
PGOOD
SV
IN
PV
IN
SW
SYNC/MODE
R
T
V
FB
I
TH
SW
PGND
PGND
SW
17
LTC3412A
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SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
f
OSC
Switching Frequency
R
OSC
= 294k
0.88
1
1.1
MHz
Switching Frequency Range
(Note 6)
0.3
4
MHz
f
SYNC
SYNC Capture Range
(Note 6)
0.3
4
MHz
R
PFET
R
DS(ON)
of P-Channel FET
I
SW
= 1A (Note 7)
77
110
m
R
NFET
R
DS(ON)
of N-Channel FET
I
SW
= 1A (Note 7)
65
90
m
I
LIMIT
Peak Current Limit
4.5
6
A
V
UVLO
Undervoltage Lockout Threshold
1.75
2
2.25
V
I
LSW
SW Leakage Current
V
RUN
= 0V, V
IN
= 5.5V
0.1
1
µA
V
RUN
RUN Threshold
0.5
0.65
0.8
V
I
RUN
RUN/SS Leakage Current
1
µA
ELECTRICAL CHARACTERISTICS
The
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
°C. V
IN
= 3.3V unless otherwise specified.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3412AE is guaranteed to meet performance specifications
from 0
°C to 85°C. Specifications over the 40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: The LTC3412A is tested in a feedback loop that adjusts V
FB
to
achieve a specified error amplifier output voltage (I
TH
).
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 5: T
J
is calculated from the ambient temperature T
A
and power
dissipation as follows: LTC3412AEFE: T
J
= T
A
+ P
D
(38
°C/W)
LTC3412AEUF: T
J
= T
A
+ P
D
(34
°C/W)
Note 6: 4MHz operation is guaranteed by design and not production tested.
Note 7: Switch on resistance is guaranteed by design and test condition in
the UF package and by final test correlation in the FE package.
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Efficiency vs Load Current
Efficiency vs Load Current, Burst
Mode Operation
Efficiency vs Load Current,
Forced Continuous Operation
LOAD CURRENT (A)
0.01
EFFICIENCY (%)
100
90
80
70
60
50
40
30
20
10
0
EFFICIENCY (%)
100
95
90
85
80
75
70
65
60
55
50
0.1
1
10
LOAD CURRENT (A)
0.01
0.1
1
10
LOAD CURRENT (A)
0.01
0.1
1
10
3412A GO1
EFFICIENCY (%)
100
90
80
70
60
50
40
30
20
10
0
3412A GO2
3412A GO3
Burst Mode
OPERATION
FORCED
CONTINUOUS
V
IN
= 3.3V
V
IN
= 3.3V
V
OUT
= 2.5V
FIGURE 4 CIRCUIT
V
OUT
= 2.5V
FIGURE 4 CIRCUIT
V
OUT
= 2.5V
FIGURE 4 CIRCUIT
V
IN
= 5V
V
IN
= 3.3V
V
IN
= 5V
LTC3412A
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INPUT VOLTAGE (V)
2.5
94
92
90
88
86
84
82
80
4.0
3412A GO4
3.0
3.5
4.5
5.0
3412A GO5
3412A GO8
3412A GO7
3412A GO9
EFFICIENCY (%)
LOAD CURRENT (A)
0
V
OUT
/V
OUT
(%)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.5
1.0
1.5
2.0
3412A GO6
2.5
3.0
0.1A
1A
3A
5
µs/DIV
5
µs/DIV
40
µs/DIV
V
OUT
20mV/DIV
INDUCTOR
CURRENT
1A/DIV
V
OUT
100mV/DIV
INDUCTOR
CURRENT
2A/DIV
FORCED
CONTINUOUS
20mV/DIV
PULSE
SKIPPING
20mV/DIV
BURST
MODE
20mV/DIV
V
IN
= 3.3V
V
OUT
= 2.5V
F = 1MHz
LOAD STEP = 50mA TO 2A
FIGURE 4 CIRCUIT
V
IN
= 3.3V
V
OUT
= 2.5V
FIGURE 4 CIRCUIT
FIGURE 4 CIRCUIT
EFFICIENCY (%)
96
95
94
93
92
91
90
89
88
87
FREQUENCY (MHz)
0
4.0
1.0
2.0
3.0
0.5
1.5
2.5
3.5
0.22
µH
0.47
µH
1
µH
FIGURE 4 CIRCUIT
V
IN
= 3.3V
FIGURE 4 CIRCUIT
FIGURE 4 CIRCUIT
V
IN
= 3.3V
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Burst Mode Operation
Load Step Transient Burst Mode
Operation
Efficiency vs Input Voltage
Efficiency vs Frequency
Load Regulation
Output Voltage Ripple
LTC3412A
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INPUT VOLTAGE (V)
2.5
ON-RESISTANCE (m
)
100
95
90
85
80
75
70
65
60
55
50
4.5
3412A G13
3.0
3.5
4.0
5.0
2.5
4.5
3.0
3.5
4.0
5.5
5.0
3412A G10
3412A G11
TEMPERATURE (
°C)
ON-RESISTANCE (m
)
3412A G14
120
100
80
60
40
20
0
40
0
40
60
20
20
80
100
120
INPUT VOLTAGE (V)
2.5
SWITCH LEAKAGE CURRENT (nA)
3.0
3.5
4.0
4.5
3412A G15
5.0
50
45
40
35
30
25
20
15
10
5
0
5.5
R
OSC
(k
)
40
FREQUENCY (kHz)
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
0
240
440 540
940
3412A G16
140
340
640 740 840
INPUT VOLTAGE (V)
FREQUENCY (kHz)
1060
1050
1040
1030
1020
1010
1000
990
3412A G17
TEMPERATURE (
°C)
40
FREQUENCY (kHz)
1020
1015
1010
1005
1000
995
990
985
980
975
970
0
40
60
3412A G18
20
20
80
100
120
TEMPERATURE (
°C)
45
V
REF
(V)
75
0.7975
0.7970
0.7965
0.7960
0.7955
0.7950
0.7945
0.7940
0.7935
0.7930
3412A G12
25
5
15
35
55
95
115
40
µs/DIV
1ms/DIV
V
OUT
100mV/DIV
V
OUT
2V/DIV
RUN/SS
2V/DIV
INDUCTOR
CURRENT
2A/DIV
INDUCTOR
CURRENT
2A/DIV
V
IN
= 3.3V
V
OUT
=2.5V
F = 1MHz
LOAD STEP = 0A TO 3A
FIGURE 4 CIRCUIT
V
IN
= 3.3V
V
OUT
=2.5V
LOAD STEP = 2A
FIGURE 4 CIRCUIT
PFET
PFET
PFET
NFET
NFET
NFET
V
IN
= 3.3V
V
IN
= 3.3V
V
IN
= 3.3V
R
OSC
= 294k
V
IN
= 3.3V
R
OSC
= 294k
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Start-Up Transient
Switch On-Resistance vs
Temperature
Switch Leakage Current vs
Input Voltage
Switch On-Resistance vs
Input Voltage
Frequency vs R
OSC
Frequency vs Input Voltage
Frequency vs Temperature
V
REF
vs Temperature
Load Step Transient Forced
Continuous
LTC3412A
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Quiescent Current vs
Temperature
Minimum Peak Inductor Current
vs Burst Clamp Voltage
Peak Current vs Input Voltage
Quiescent Current vs
Input Voltage
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
INPUT VOLTAGE (V)
QUIESCENT CURRENT (
µ
A)
350
300
250
200
150
100
50
0
3412A G19
QUIESCENT CURRENT (
µ
A)
350
300
250
200
150
100
50
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE (
°C)
40
80
3412A G20
0
40
120
20
20
60
100
V
BURST
(V)
0.1
0.2
MAXIMUM PEAK INDUCTOR CURRENT (mA)
0.3
0.5
0.4
0.6
0.7
3412A G21
4000
3500
3000
2500
2000
1500
1000
500
0
INPUT VOLTAGE (V)
2.25
2.75
PEAK INDUCTOR CURRENT (A)
3.25
4.25
3.75
4.75
3412A G22
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
ACTIVE
SLEEP
ACTIVE
SLEEP
V
IN
= 3.3V
LTC3412A
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SV
IN
(Pin 1/Pin 11): Signal Input Supply. Decouple this
pin to SGND with a capacitor.
PGOOD (Pin 2/Pin 12): Power Good Output. Open-drain
logic output that is pulled to ground when the output
voltage is not within
±7.5% of regulation point.
I
TH
(Pin 3/Pin 13): Error Amplifier Compensation Point.
The current comparator threshold increases with this
control voltage. Nominal voltage range for this pin is from
0.2V to 1.4V with 0.4V corresponding to the zero-sense
voltage (zero current).
V
FB
(Pin 4/Pin 14): Feedback Pin. Receives the feedback
voltage from a resistive divider connected across the
output.
R
T
(Pin 5/Pin 15): Oscillator Resistor Input. Connecting a
resistor to ground from this pin sets the switching fre-
quency.
SYNC/MODE (Pin 6/Pin 16): Mode Select and External
Clock Synchronization Input. To select forced continuous,
tie to SV
IN
. Connecting this pin to a voltage between 0V and
1V selects Burst Mode operation with the burst clamp set
to the pin voltage.
U
U
U
PI FU CTIO S
RUN/SS (Pin 7/Pin 1): Run Control and Soft-Start Input.
Forcing this pin below 0.5V shuts down the LTC3412A. In
shutdown all functions are disabled drawing < 1
µA of
supply current. A capacitor to ground from this pin sets the
ramp time to full output current.
SGND (Pin 8/Pin 2): Signal Ground. All small-signal
components, compensation components and the exposed
pad on the bottom side of the IC should connect to this
ground, which in turn connects to PGND at one point.
PV
IN
(Pins 9, 16/Pins 3, 10): Power Input Supply. Decouple
this pin to PGND with a capacitor.
SW (Pins 10, 11, 14, 15/Pins 4, 5, 8, 9): Switch Node
Connection to the Inductor. This pin connects to the drains
of the internal main and synchronous power MOSFET
switches.
PGND (Pins 12, 13/Pins 6, 7): Power Ground. Connect
this pin close to the () terminal of C
IN
and C
OUT
.
Exposed Pad (Pin 17/Pin 17): Signal Ground. Must be
soldered to PCB for electrical connection and rated ther-
mal performance.
(FE Package/UHF Package)
LTC3412A
8
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Main Control Loop
The LTC3412A is a monolithic, constant-frequency, cur-
rent-mode step-down DC/DC converter. During normal
operation, the internal top power switch (P-channel
MOSFET) is turned on at the beginning of each clock cycle.
Current in the inductor increases until the current com-
parator trips and turns off the top power MOSFET. The
peak inductor current at which the current comparator
shuts off the top power switch is controlled by the voltage
on the I
TH
pin. The error amplifier adjusts the voltage on
the I
TH
pin by comparing the feedback signal from a
resistor divider on the V
FB
pin with an internal 0.8V
reference. When the load current increases, it causes a
reduction in the feedback voltage relative to the reference.
The error amplifier raises the I
TH
voltage until the average
inductor current matches the new load current. When the
top power MOSFET shuts off, the synchronous power
switch (N-channel MOSFET) turns on until either the
bottom current limit is reached or the beginning of the next
clock cycle. The bottom current limit is set at 1.3A for
forced continuous mode and 0A for Burst Mode operation.
OPERATIO
U
+
2
7
4
+
+
+
0.74V
ERROR
AMPLIFIER
SYNC/MODE
BURST
COMPARATOR
BCLAMP
NMOS
CURRENT
COMPARATOR
PMOS CURRENT
COMPARATOR
REVERSE
CURRENT
COMPARATOR
0.86V
RUN
RUN/SS
15
13
12
14
11
SW
P-CH
N-CH
10
PGOOD
3
I
TH
V
FB
0.8V
5
R
T
6
SYNC/MODE
3412 FBD
16
PV
IN
9
8
SGND
1
SV
IN
SLOPE
COMPENSATION
VOLTAGE
REFERENCE
OSCILLATOR
LOGIC
SLOPE
COMPENSATION
RECOVERY
+
+
+
PGND
+
FU
N
CTIO
N
AL BLOCK DIAGRA
U
U
W
LTC3412A
9
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The operating frequency is externally set by an external
resistor connected between the RT pin and ground. The
practical switching frequency can range from 300kHz to
4MHz.
Overvoltage and undervoltage comparators will pull the
PGOOD output low if the output voltage comes out of
regulation by
± 7.5%. In an overvoltage condition, the top
power MOSFET is turned off and the bottom power MOSFET
is switched on until either the overvoltage condition clears
or the bottom MOSFET's current limit is reached.
Forced Continuous Mode
Connecting the SYNC/MODE pin to SV
IN
will disable Burst
Mode operation and force continuous current operation.
At light loads, forced continuous mode operation is less
efficient than Burst Mode operation, but may be desirable
in some applications where it is necessary to keep switch-
ing harmonics out of a signal band. The output voltage
ripple is minimized in this mode.
Burst Mode Operation
Connecting the SYNC/MODE pin to a voltage in the range
of 0V to 1V enables Burst Mode operation. In Burst Mode
operation, the internal power MOSFETs operate intermit-
tently at light loads. This increases efficiency by minimiz-
ing switching losses. During Burst Mode operation, the
minimum peak inductor current is externally set by the
voltage on the SYNC/MODE pin and the voltage on the I
TH
pin is monitored by the burst comparator to determine
when sleep mode is enabled and disabled. When the
average inductor current is greater than the load current,
the voltage on the I
TH
pin drops. As the I
TH
voltage falls
below 150mV, the burst comparator trips and enables
sleep mode. During sleep mode, the top power MOSFET is
held off and the I
TH
pin is disconnected from the output of
the error amplifier. The majority of the internal circuitry is
also turned off to reduce the quiescent current to 64
µA
while the load current is solely supplied by the output
capacitor. When the output voltage drops, the I
TH
pin is
reconnected to the output of the error amplifier and the top
power MOSFET along with all the internal circuitry is
switched back on. This process repeats at a rate that is
dependent on the load demand.
Pulse Skipping operation is implemented by connecting
the SYNC/MODE pin to ground. This forces the burst
clamp level to be at 0V. As the load current decreases, the
peak inductor current will be determined by the voltage on
the I
TH
pin until the I
TH
voltage drops below 400mV. At this
point, the peak inductor current is determined by the
minimum on-time of the current comparator. If the load
demand is less than the average of the minimum on-time
inductor current, switching cycles will be skipped to keep
the output voltage in regulation.
Frequency Synchronization
The internal oscillator of the LTC3412A can be synchro-
nized to an external clock connected to the SYNC/MODE
pin. The frequency of the external clock can be in the range
of 300kHz to 4MHz. For this application, the oscillator
timing resistor should be chosen to correspond to a
frequency that is 25% lower than the synchronization
frequency. During synchronization, the burst clamp is set
to 0V, and each switching cycle begins at the falling edge
of the clock signal.
Dropout Operation
When the input supply voltage decreases toward the
output voltage, the duty cycle increases toward the maxi-
mum on-time. Further reduction of the supply voltage
forces the main switch to remain on for more than one
cycle eventually reaching 100% duty cycle. The output
voltage will then be determined by the input voltage minus
the voltage drop across the internal P-channel MOSFET
and the inductor.
Low Supply Operation
The LTC3412A is designed to operate down to an input
supply voltage of 2.25V. One important consideration
at low input supply voltages is that the R
DS(ON)
of the
P-channel and N-channel power switches increases. The
user should calculate the power dissipation when the
LTC3412A is used at 100% duty cycle with low input
voltages to ensure that thermal limits are not exceeded.
OPERATIO
U
LTC3412A
10
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Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant fre-
quency architectures by preventing subharmonic oscilla-
tions at duty cycles greater than 50%. It is accomplished
internally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 40%. Normally,
the maximum inductor peak current is reduced when
slope compensation is added. In the LTC3412A, however,
slope compensation recovery is implemented to keep the
maximum inductor peak current constant throughout the
range of duty cycles. This keeps the maximum output
current relatively constant regardless of duty cycle.
Short-Circuit Protection
When the output is shorted to ground, the inductor current
decays very slowly during a single switching cycle. To
prevent current runaway from occurring, a secondary
current limit is imposed on the inductor current. If the
inductor valley current increases larger than 4.4A, the top
power MOSFET will be held off and switching cycles will be
skipped until the inductor current is reduced.
The basic LTC3412A application circuit is shown
in Figure 1. External component selection is determined
by the maximum load current and begins with the selec-
tion of the operating frequency and inductor value fol-
lowed by C
IN
and C
OUT
.
Operating Frequency
Selection of the operating frequency is a tradeoff between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.
The operating frequency of the LTC3412A is determined
by an external resistor that is connected between pin R
T
and ground. The value of the resistor sets the ramp current
that is used to charge and discharge an internal timing
capacitor within the oscillator and can be calculated by
using the following equation:
R
f
k
OSC
=
( )
3 08 10
10
11
.
·
Although frequencies as high as 4MHz are possible, the
minimum on-time of the LTC3412A imposes a minimum
limit on the operating duty cycle. The minimum on-time is
typically 110ns; therefore, the minimum duty cycle is
equal to 100 · 110ns · f(Hz).
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current
I
L
increases with higher V
IN
or V
OUT
and
decreases with higher inductance.
=
I
V
fL
V
V
L
OUT
OUT
IN
1
Having a lower ripple current reduces the core losses in
the inductor, the ESR losses in the output capacitors, and
the output voltage ripple. Highest efficiency operation is
achieved at low frequency with small ripple current. This,
however, requires a large inductor.
A reasonable starting point for selecting the ripple current
is
I
L
= 0.4(I
MAX
). The largest ripple current occurs at the
highest V
IN
. To guarantee that the ripple current stays
below a specified maximum, the inductor value should be
chosen according to the following equation:
L
V
f I
V
V
OUT
L MAX
OUT
IN MAX
=
(
)
(
)
1
The inductor value will also have an effect on Burst Mode
operation. The transition to low current operation begins
when the peak inductor current falls below a level set by
the burst clamp. Lower inductor values result in higher
ripple current which causes this to occur at lower load
currents. This causes a dip in efficiency in the upper range
of low current operation. In Burst Mode operation, lower
inductance values will cause the burst frequency to in-
crease.
Inductor Core Selection
Once the value for L is known, the type of inductor must be
selected. Actual core loss is independent of core size for a
fixed inductor value, but it is very dependent on the
inductance selected. As the inductance increases, core
losses decrease. Unfortunately, increased inductance re-
quires more turns of wire and therefore copper losses will
increase.
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Ferrite designs have very low core losses and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates "hard," which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy mate-
rials are small and don't radiate much energy, but gener-
ally cost more than powdered iron core inductors with
similar characteristics. The choice of which style inductor
to use mainly depends on the price verus size require-
ments and any radiated field/EMI requirements. New
designs for surface mount inductors are available from
Coiltronics, Coilcraft, Toko, and Sumida.
C
IN
and C
OUT
Selection
The input capacitance, C
IN
, is needed to filter the trapezoi-
dal wave current at the source of the top MOSFET. To
prevent large voltage transients from occurring, a low ESR
input capacitor sized for the maximum RMS current
should be used. The maximum RMS current is given by:
I
I
V
V
V
V
RMS
OUT MAX
OUT
IN
IN
OUT
=
(
)
1
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT/2
. This simple worst-case condition is com-
monly used for design because even significant deviations
do not offer much relief. Note that ripple current ratings
from capacitor manufacturers are often based on only
2000 hours of life which makes it advisable to further
derate the capacitor, or choose a capacitor rated at a
higher temperature than required. Several capacitors may
also be paralleled to meet size or height requirements in
the design. For low input voltage applications, sufficient
bulk input capacitance is needed to minimize transient
effects during output load changes.
The selection of C
OUT
is determined by the effective series
resistance (ESR) that is required to minimize voltage
ripple and load step transients as well as the amount of
bulk capacitance that is necessary to ensure that the
control loop is stable. Loop stability can be checked by
viewing the load transient response as described in a later
section. The output ripple,
V
OUT
, is determined by:
+
V
I ESR
fC
OUT
L
OUT
1
8
The output ripple is highest at maximum input voltage
since
I
L
increases with input voltage. Multiple capacitors
placed in parallel may be needed to meet the ESR and RMS
current handling requirements. Dry tantalum, special poly-
mer, aluminum electrolytic, and ceramic capacitors are all
available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only use
types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR, but can be used in cost-sensitive
applications provided that consideration is given to ripple
current ratings and long term reliability. Ceramic capaci-
tors have excellent low ESR characteristics but can have a
high voltage coefficient and audible piezoelectric effects.
The high Q of ceramic capacitors with trace inductance
can also lead to significant ringing.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input and
the power is supplied by a wall adapter through long wires,
a load step at the output can induce ringing at the input,
V
IN
. At best, this ringing can couple to the output and be
mistaken as loop instability. At worst, a sudden inrush of
current through the long wires can potentially cause a
voltage spike at V
IN
large enough to damage the part.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
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Output Voltage Programming
The output voltage is set by an external resistive divider
according to the following equation:
V
V
R
R
OUT
=
+
0 8
1
2
1
.
The resistive divider allows pin V
FB
to sense a fraction of
the output voltage as shown in Figure 2.
I
BURST
is determined by the desired amount of output
voltage ripple. As the value of I
BURST
increases, the sleep
period between pulses and the output voltage ripple in-
crease. The burst clamp voltage, V
BURST
, can be set by a
resistor divider from the V
FB
pin to the SGND pin as shown
in Figure 1.
Pulse skipping, which is a compromise between low
output voltage ripple and efficiency, can be implemented
by connecting pin SYNC/MODEto ground. This sets I
BURST
to 0A. In this condition, the peak inductor current is limited
by the minimum on-time of the current comparator. The
lowest output voltage ripple is achieved while still operat-
ing discontinuously. During very light output loads, pulse
skipping allows only a few switching cycles to be skipped
while maintaining the output voltage in regulation.
Frequency Synchronization
The LTC3412A's internal oscillator can be synchronized to
an external clock signal. During synchronization, the top
MOSFET turn-on is locked to the falling edge of the
external frequency source. The synchronization frequency
range is 300kHz to 4MHz. Synchronization only occurs if
the external frequency is greater than the frequency set
by the external resistor. Because slope compensation is
generated by the oscillator's RC circuit, the external
frequency should be set 25% higher than the frequency
set by the external resistor to ensure that adequate slope
compensation is present.
Soft-Start
The RUN/SS pin provides a means to shut down the
LTC3412A as well as a timer for soft-start. Pulling the
RUN/SS pin below 0.5V places the LTC3412A in a low
quiescent current shutdown state (I
Q
< 1
µA).
The LTC3412A contains an internal soft-start clamp that
gradually raises the clamp on I
TH
after the RUN/SS pin is
pulled above 2V. The full current range becomes available
on I
TH
after 1024 switching cycles. If a longer soft-start
period is desired, the clamp on I
TH
can be set externally
with a resistor and capacitor on the RUN/SS pin as shown
in Figure 1. The soft-start duration can be calculated by
using the following formula:
t
R
C
V
V
V
SECONDS
SS
SS
SS
IN
IN
=
ln
.
(
)
1 8
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3412A F02
LTC3412A
V
FB
SGND
V
OUT
R2
R1
Figure 2. Setting the Output Voltage
Burst Clamp Programming
If the voltage on the SYNC/MODE pin is less than V
IN
by 1V,
Burst Mode operation is enabled. During Burst Mode
Operation, the voltage on the SYNC/MODE pin determines
the burst clamp level, which sets the minimum peak
inductor current, I
BURST
. To select the burst clamp level,
use the graph of Minimum Peak Inductor Current vs Burst
Clamp Voltage in the Typical Performance Characteristics
section.
V
BURST
is the voltage on the SYNC/MODE pin. I
BURST
can
only be programmed in the range of 0A to 6A. For values
of V
BURST
greater than 1V, I
BURST
is set at 6A. For values
of V
BURST
less than 0.4V, I
BURST
is set at 0A. As the output
load current drops, the peak inductor currents decrease to
keep the output voltage in regulation. When the output
load current demands a peak inductor current that is less
than I
BURST
, the burst clamp will force the peak inductor
current to remain equal to I
BURST
regardless of further
reductions in the load current. Since the average inductor
current is greater than the output load current, the voltage
on the I
TH
pin will decrease. When the I
TH
voltage drops
to 150mV, sleep mode is enabled in which both power
MOSFETs are shut off along with most of the circuitry to
minimize power consumption. All circuitry is turned back
on and the power MOSFETs begin switching again when
the output voltage drops out of regulation. The value for
LTC3412A
13
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Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses: V
IN
quiescent current and I
2
R losses.
The V
IN
quiescent current loss dominates the efficiency
loss at very low load currents whereas the I
2
R loss
dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence.
1. The V
IN
quiescent current is due to two components:
the DC bias current as given in the electrical characteristics
and the internal main switch and synchronous switch gate
charge currents. The gate charge current results from
switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge dQ moves
from V
IN
to ground. The resulting dQ/dt is the current out
of V
IN
that is typically larger than the DC bias current. In
continuous mode, I
GATECHG
= f(QT + QB) where QT and QB
are the gate charges of the internal top and bottom
switches. Both the DC bias and gate charge losses are
proportional to V
IN
; thus, their effects will be more pro-
nounced at higher supply voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In con-
tinuous mode the average output current flowing through
inductor L is "chopped" between the main switch and the
synchronous switch. Thus, the series resistance looking
into the SW pin is a function of both top and bottom
MOSFET R
DS(ON)
and the duty cycle (DC) as follows:
R
SW
= (R
DS(ON)
TOP)(DC) + (R
DS(ON)
BOT)(1 DC)
The R
DS(ON)
for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. To obtain I
2
R losses, simply add R
SW
to R
L
and
multiply the result by the square of the average output
current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for less
than 2% of the total loss.
Thermal Considerations
In most applications, the LTC3412A does not dissipate
much heat due to its high efficiency.
However, in applications where the LTC3412A is running
at high ambient temperature with low supply voltage and
high duty cycles, such as in dropout, the heat dissipated
may exceed the maximum junction temperature of the
part. If the junction temperature reaches approximately
150
°C, both power switches will be turned off and the SW
node will become high impedance.
To avoid the LTC3412A from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
t
r
= (P
D
)(
JA
)
where P
D
is the power dissipated by the regulator and
JA
is the thermal resistance from the junction of the die to the
ambient temperature. For the 16-lead exposed TSSOP
package, the
JA
is 38
°C/W. For the 16-lead QFN package
the
JA
is 34
°C/W.
The junction temperature, T
J
, is given by:
T
J
= T
A
+ t
r
where T
A
is the ambient temperature.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R
DS(ON)
).
To maximize the thermal performance of the LTC3412A,
the exposed pad should be soldered to a ground plane.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current.
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When a load step occurs, V
OUT
immediately shifts by an
amount equal to
I
LOAD(ESR)
, where ESR is the effective
series resistance of C
OUT
.
I
LOAD
also begins to charge or
discharge C
OUT
generating a feedback error signal used by
the regulator to return V
OUT
to its steady-state value.
During this recovery time, V
OUT
can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. The I
TH
pin external components and output capaci-
tor shown in Figure 1 will provide adequate compensation
for most applications.
Design Example
As a design example, consider using the LTC3412A in an
application with the following specifications:
V
IN
= 3.3V, V
OUT
= 2.5V, I
OUT(MAX)
= 3A,
I
OUT(MIN)
= 100mA, f = 1MHz.
Because efficiency is important at both high and low load
current, Burst Mode operation will be utilized.
First, calculate the timing resistor:
R
k
k
OSC
=
=
3 08 10
1 10
10
298
11
6
.
·
·
Use a standard value of 294k. Next, calculate the inductor
value for about 40% ripple current at maximum V
IN
:
L
V
MHz
A
V
V
H
=
=
µ
2 5
1
1 2
1
2 5
3 3
0 51
.
(
)( .
)
.
.
.
Using a 0.47
µH inductor results in a maximum ripple
current of:
=
µ
=
I
V
MHz
H
V
V
A
L
2 5
1
0 47
1
2 5
3 3
1 29
.
(
)( .
)
.
.
.
C
OUT
will be selected based on the ESR that is required to
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, two
100
µF ceramic capacitors will be used.
C
IN
should be sized for a maximum current rating of:
I
A
V
V
V
V
A
RMS
RMS
=
=
(
)
.
.
.
.
.
3
2 5
3 3
3 3
2 5
1 1 29
Decoupling the PV
IN
and SV
IN
pins with two 22
µF capaci-
tors is adequate for most applications.
The burst clamp and output voltage can now be pro-
grammed by choosing the values of R1, R2, and R3. The
voltage on pin MODE will be set to 0.50V by the resistor
divider consisting of R2 and R3. According to the graph of
Minimum Peak Inductor Current vs Burst Clamp Voltage
in the Typical Performance Characteristics section, a burst
clamp voltage of 0.5V will set the minimum inductor
current, I
BURST
, to approximately 1.1A.
If we set the sum of R2 and R3 to 185k, then the following
equations can be solved:
R
R
k
R
R
V
V
2
3
185
1
2
3
0 8
0 50
+
=
+
=
.
.
The two equations shown above result in the following
values for R2 and R3: R2 = 69.8k , R3 = 115k. The value
of R1 can now be determined by solving the following
equation.
1
1
185
2 5
0 8
1 392
+
=
=
R
k
V
V
R
k
.
.
A value of 392k will be selected for R1. Figure 4 shows the
complete schematic for this design example.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3412A. Check the following in your layout:
1. A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small signal components returning to
the SGND pin at one point which is then connected to the
PGND pin close to the LTC3412A.
2. Connect the (+) terminal of the input capacitor(s), C
IN
,
as close as possible to the PV
IN
pin. This capacitor
provides the AC current into the internal power MOSFETs.
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Figure 4. 3.3V to 2.5V, 3A Regulator at 1MHz, Burst Mode Operation
APPLICATIO S I FOR ATIO
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Figure 3. LTC3412A Layout Diagram
8
SGND
C
SS
1000pF X7R
C
C
47pF
*
**
VISHAY IHLP-2525CZ-01
TDK 4532X5R0J107M
7
R
SS
2.2M
RUN
6 SYNC/MODE
R
OSC
294k
5
R
T
R2
69.8k
4
R3
115k
V
FB
R
ITH
17.4k
3
C
ITH
330pF X7R
I
TH
2
PGOOD
PGOOD
1
SV
IN
9
PV
IN
10
SW
11
SW
12
PGND
LTC3412A
EFE
13
L1*
0.47
µH
PGND
14
SW
15
SW
16
PV
IN
C
IN2
22
µF
X5R 6.3V
C
IN1
22
µF
C
OUT
**
100
µF
×2
V
OUT
2.5V
3A
V
IN
3.3V
GND
3412 F04
R1 392k
C
IN3
**
100
µF
R
PG
100k
C
FF
22pF X5R
Top
Bottom
3. Keep the switching node, SW, away from all sensitive
small signal nodes.
4. Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise of
power components. You can connect the copper areas to
any DC net (PV
IN
, SV
IN
, V
OUT
, PGND, SGND, or any other
DC rail in your system).
5. Connect the V
FB
pin directly to the feedback resistors.
The resistor divider must be connected between V
OUT
and SGND.
LTC3412A
16
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TYPICAL APPLICATIO S
U
1.2V, 3A, 1.5MHz 1mm Height Regulator Using All Ceramic Capacitors
1.8V, 3A Step-Down Regulator at 1MHz, Burst Mode Operation
2
SGND
C
SS
1000pF X7R
1
R
SS
2.2M
RUN
16
SYNC/MODE
R
OSC
196k
15
R
T
R2
187k
14
V
FB
R
ITH
6.34k
13
C
ITH
1000pF X7R
I
TH
12
PGOOD
PGOOD
11
SV
IN
3
PV
IN
4
SW
5
SW
6
PGND
LTC3412A
EUF
7
L1*
0.47
µH
PGND
8
SW
9
SW
10
PV
IN
C1
22pF X5R
C
IN2
10
µF
X5R 6.3V
C
IN1
10
µF
X5R 6.3V
C
OUT
**
22
µF
X3
V
OUT
1.2V
3A
V
IN
3.3V
GND
3412 TA01
R1 95.3k
*
**
COOPER SD10-R47
TAIYO YUDEN AMK212BJ226MD-B
C
C
22pF
R
PG
100k
8
SGND
C
SS
1000pF X7R
7
R
SS
2.2M
RUN
6
SYNC/MODE
R
OSC
294k
5
R
T
R2
69.8k
R3
115k
4
V
FB
R
ITH
15k
3
C
ITH
820pF X7R
I
TH
2
PGOOD
PGOOD
1
SV
IN
9
PV
IN
10
SW
11
SW
12
PGND
LTC3412A
EFE
13
PGND
14
SW
15
SW
16
PV
IN
C
IN2
22
µF
X5R 6.3V
C
IN1
22
µF
X5R 6.3V
C
OUT
**
100
µF
×3
V
OUT
1.8V
3A
V
IN
2.5V
GND
R1 232k
3412 TA02
L1
0.47
µH*
*
**
VISHAY IHLP-2525CZ-01
TDK C4532X5R0J107M
C2
47pF
C1 47pF X5R
R
PG
100k
C
IN3
**
100
µF
LTC3412A
17
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TYPICAL APPLICATIO S
U
3.3V, 3A Step-Down Regulator at 2MHz, Forced Continuous Mode Operation
8
SGND
C
SS
1000pF X7R
7
R
SS
2.2M
RUN
6
SYNC/MODE
R
OSC
137k
5
R
T
R2
200k
4
V
FB
R
ITH
7.5k
3
C
ITH
820pF X7R
I
TH
2
PGOOD
PGOOD
1
SV
IN
9
PV
IN
10
SW
11
SW
12
PGND
LTC3412A
EFE
13
PGND
14
SW
15
SW
16
PV
IN
C
IN2
22
µF
X5R 6.3V
C
IN1
22
µF
X5R 6.3V
C
OUT
**
100
µF
×2
V
OUT
3.3V
3A
V
IN
5V
GND
R1 634k
3412 TA03
L1*
0.47
µH
*
**
VISHAY IHLP-2525CZ-01
TDK C4532X5R0J107M
C
C
47pF
C1 22pF X5R
C
IN3
**
100
µF
R
PG
100k
2.5V, 3A Step-Down Regulator Synchronized to 1.8MHz
8
SGND
C
SS
1000pF X7R
7
R
SS
2.2M
RUN
6
SYNC/MODE
1.8MHz
EXT CLOCK
R
OSC
182k
5
R
T
R2 162k
4
V
FB
R
ITH
6.49k
R
PG
100k
3
C
ITH
220pF X7R
I
TH
2
PGOOD
PGOOD
1
SV
IN
9
PV
IN
10
SW
11
SW
12
PGND
LTC3412A
EFE
13
L1*
0.47
µH
PGND
14
SW
15
SW
16
PV
IN
C
IN2
22
µF
X5R 6.3V
C
IN1
22
µF
X5R 6.3V
C
OUT
**
150
µF
V
OUT
1.5V
3A
V
IN
3.3V
GND
R1 392k
3412 TA04
*
**
COOPER SD20-R47
SANYO POSCAP 4TPE150MAZB
C
C
22pF
C1 22pF X5R
+
LTC3412A
18
3412afa
PACKAGE DESCRIPTIO
U
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BA
FE16 (BA) TSSOP 0204
0.09 0.20
(.0035 .0079)
0
° 8°
0.25
REF
0.50 0.75
(.020 .030)
4.30 4.50*
(.169 .177)
1
3
4
5
6 7 8
10
9
4.90 5.10*
(.193 .201)
16 1514 13 12 11
1.10
(.0433)
MAX
0.05 0.15
(.002 .006)
0.65
(.0256)
BSC
2.74
(.108)
2.74
(.108)
0.195 0.30
(.0077 .0118)
TYP
2
MILLIMETERS
(INCHES)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
RECOMMENDED SOLDER PAD LAYOUT
3. DRAWING NOT TO SCALE
0.45
±0.05
0.65 BSC
4.50
±0.10
6.60
±0.10
1.05
±0.10
2.74
(.108)
2.74
(.108)
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
LTC3412A
19
3412afa
PACKAGE DESCRIPTIO
U
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
UF Package
16-Lead Plastic QFN (4mm
× 4mm)
(Reference LTC DWG # 05-08-1692)
4.00
± 0.10
(4 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.55
± 0.20
16
15
1
2
BOTTOM VIEW--EXPOSED PAD
2.15
± 0.10
(4-SIDES)
0.75
± 0.05
R = 0.115
TYP
0.30
± 0.05
0.65 BSC
0.200 REF
0.00 0.05
(UF16) QFN 10-04
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.72
±0.05
0.30
±0.05
0.65 BSC
2.15
± 0.05
(4 SIDES)
2.90
± 0.05
4.35
± 0.05
PACKAGE OUTLINE
PIN 1 NOTCH R = 0.20 TYP
OR 0.35
× 45° CHAMFER
LTC3412A
20
3412afa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
FAX: (408) 434-0507
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005
LT 1205 REV A · PRINTED IN USA
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