1
LTC3410
3410f
OUTPUT CURRENT (mA)
0.1
0
10
20
30
40
EFFICIENCY (%)
POWER LOSS (W)
50
60
70
80
90
100
1
0.1
0.01
0.001
0.0001
10
100
1
1000
3410 TA01b
EFFICIENCY
POWER LOSS
V
IN
= 2.7V
V
IN
= 3.6V
V
IN
= 4.2V
High Efficiency: Up to 96%
Very Low Quiescent Current: Only 26
µ
A
Low Output Voltage Ripple
300mA Output Current at V
IN
= 3V
380mA Minimum Peak Switch Current
2.5V to 5.5V Input Voltage Range
2.25MHz Constant Frequency Operation
No Schottky Diode Required
Low Dropout Operation: 100% Duty Cycle
Stable with Ceramic Capacitors
0.8V Reference Allows Low Output Voltages
Shutdown Mode Draws < 1
µA Supply Current
±2% Output Voltage Accuracy
Current Mode Operation for Excellent Line and
Load Transient Response
Overtemperature Protected
Available in Low Profile SC70 Package
The LTC
®
3410 is a high efficiency monolithic synchro-
nous buck regulator using a constant frequency, current
mode architecture. Supply current during operation is
only 26
µA, dropping to <1µA in shutdown. The 2.5V to
5.5V input voltage range makes the LTC3410 ideally suited
for single Li-Ion battery-powered applications. 100% duty
cycle provides low dropout operation, extending battery
life in portable systems.
Switching frequency is internally set at 2.25MHz, allowing
the use of small surface mount inductors and capacitors.
The LTC3410 is specifically designed to work well with
ceramic output capacitors, achieving very low output
voltage ripple and a small PCB footprint.
The internal synchronous switch increases efficiency and
eliminates the need for an external Schottky diode. Low
output voltages are easily supported with the 0.8V feed-
back reference voltage. The LTC3410 is available in a tiny,
low profile SC70 package.
Cellular Telephones
Wireless and DSL Modems
Digital Cameras
MP3 Players
Portable Instruments
2.25MHz, 300mA
Synchronous Step-Down
Regulator in SC70
APPLICATIO S
U
FEATURES
TYPICAL APPLICATIO
U
DESCRIPTIO
U
Efficiency and Power Loss
vs Output Current
V
IN
C
IN
4.7
µF
CER
V
IN
2.7V
TO 5.5V
LTC3410
RUN
4.7
µH
10pF
887k
412k
3410 TA01a
SW
V
FB
GND
C
OUT
4.7
µF
CER
V
OUT
2.5V
, LTC and LT are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents including
5481178, 6580258, 6304066, 6127815, 6498466, 6611131, 5994885.
2
LTC3410
3410f
RUN 1
GND 2
SW 3
6 V
FB
5 GND
4 V
IN
TOP VIEW
SC6 PACKAGE
6-LEAD PLASTIC SC70
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
VFB
Feedback Current
±30
nA
I
PK
Peak Inductor Current
V
IN
= 3V, V
FB
= 0.7V, Duty Cycle < 35%
380
490
mA
V
FB
Regulated Feedback Voltage
0.784
0.8
0.816
V
V
FB
Reference Voltage Line Regulation
V
IN
= 2.5V to 5.5V
0.04
0.4
%/V
V
LOADREG
Output Voltage Load Regulation
I
LOAD
= 50mA to 250mA
0.5
%
V
IN
Input Voltage Range
2.5
5.5
V
V
UVLO
Undervoltage Lockout Threshold
V
IN
Rising
2
2.3
V
V
IN
Falling
1.94
V
I
S
Input DC Bias Current
(Note 4)
Burst Mode
®
Operation
V
FB
= 0.83V, I
LOAD
= 0A
26
35
µA
Shutdown
V
RUN
= 0V
0.1
1
µA
f
OSC
Oscillator Frequency
V
FB
= 0.8V
1.8
2.25
2.7
MHz
V
FB
= 0V
310
kHz
R
PFET
R
DS(ON)
of P-Channel FET
I
SW
= 100mA
0.75
0.9
R
NFET
R
DS(ON)
of N-Channel FET
I
SW
= 100mA
0.55
0.7
I
LSW
SW Leakage
V
RUN
= 0V, V
SW
= 0V or 5V, V
IN
= 5V
±0.01
±1
µA
V
RUN
RUN Threshold
0.3
1
1.5
V
I
RUN
RUN Leakage Current
±0.01
±1
µA
Burst Mode is a registered trademark of Linear Technology Corporation.
LTC3410ESC6
ORDER PART
NUMBER
(Note 1)
Input Supply Voltage .................................. 0.3V to 6V
RUN, V
FB
Voltages ..................................... 0.3V to V
IN
SW Voltage (DC) ......................... 0.3V to (V
IN
+ 0.3V)
P-Channel Switch Source Current (DC) ............. 500mA
N-Channel Switch Sink Current (DC) ................. 500mA
Peak SW Sink and Source Current .................... 630mA
Operating Temperature Range (Note 2) .. 40
°C to 85°C
Junction Temperature (Notes 3, 5) ...................... 125
°C
Storage Temperature Range ................ 65
°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300
°C
SC6 PART MARKING
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The
denotes specifications which apply over the full operating temperature range, otherwise specifications are T
A
= 25
°C.
V
IN
= 3.6V unless otherwise specified.
ABSOLUTE AXI U RATI GS
W
W
W
U
PACKAGE/ORDER I FOR ATIO
U
U
W
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC3410E is guaranteed to meet performance specifications
from 0
°C to 70°C. Specifications over the 40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
according to the following formula:
LTC3410: T
J
= T
A
+ (P
D
)(250
°C/W)
Note 4: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
Note 5: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125
°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
T
JMAX
= 125
°C,
JA
= 250
°C/ W
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking:
http://www.linear.com/leadfree/
LBSD
3
LTC3410
3410f
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Efficiency vs Input Voltage
Efficiency vs Output Current
(From Figure1 Except for the Resistive Divider Resistor Values)
INPUT VOLTAGE (V)
2.5
100
90
80
70
60
50
40
30
4
5
3410 G02
3
3.5
4.5
5.5
EFFFICIENCY (%)
I
OUT
= 10mA
I
OUT
= 0.1mA
I
OUT
= 100mA
V
OUT
= 1.8V
I
OUT
= 1mA
I
OUT
= 250mA
OUTPUT CURRENT (mA)
0.1
0
10
20
30
40
EFFICIENCY (%)
50
60
70
80
90
100
10
100
1
1000
3410 G03
V
OUT
= 1.8V
V
IN
= 2.7V
V
IN
= 3.6V
V
IN
= 4.2V
Efficiency vs Output Current
Reference Voltage vs
Temperature
TEMPERATURE (
°C)
50
REFERENCE VOLTAGE (V)
0.804
0.809
0.814
25
75
3410 G05
0.799
0.794
25
0
50
100
125
0.789
0.784
V
IN
= 3.6V
Oscillator Frequency vs
Temperature
TEMPERATURE (
°C)
50
1.8
OSCILLATOR FREQUENCY (MHz)
1.9
2.1
2.2
2.3
50
2.7
3410 G06
2.0
0
25
75
100
25
125
2.4
2.5
2.6
V
IN
= 3.6V
Oscillator Frequency vs
Supply Voltage
SUPPLY VOLTAGE (V)
2
1.8
OSCILLATOR FREQUENCY (MHz)
1.9
2.1
2.2
2.3
4
6
2.7
3410 G07
2.0
3
5
2.4
2.5
2.6
Output Voltage vs Load Current
LOAD CURRENT (mA)
0
OUTPUT VOLTAGE (V)
1.74
1.76
1.78
300
500
3410 G08
1.72
1.70
1.68
100
200
400
1.80
1.82
1.84
OUTPUT CURRENT (mA)
0.1
0
10
20
30
40
EFFICIENCY (%)
50
60
70
80
90
100
10
100
1
1000
3410 G04
V
OUT
= 1.2V
V
IN
= 2.7V
V
IN
= 3.6V
V
IN
= 4.2V
4
LTC3410
3410f
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
(From Figure 1 Except for the Resistive Divider Resistor Values)
R
DS(ON
) vs Input Voltage
INPUT VOLTAGE (V)
1
R
DS (ON)
(
)
0.4
1.0
1.1
1.2
3
5
6
3410 G09
0.2
0.8
0.6
0.3
0.9
0.1
0
0.7
0.5
2
4
7
MAIN SWITCH
SYNCHRONOUS SWITCH
Switch Leakage vs Temperature
TEMPERATURE (
°C)
50
SWITCH LEAKAGE (nA)
30
90
100
110
0
50
75
3410 G13
10
70
50
20
80
0
60
40
25
25
100
125
V
IN
= 5.5V
RUN = 0V
SYNCHRONOUS
SWITCH
MAIN
SWITCH
Dynamic Supply Current
vs Temperature
TEMPERATURE (
°C)
50
25
0
DYNAMIC SUPPLY CURRENT (
µ
A)
20
50
0
50
75
3410 G12
10
40
30
25
100
125
Dynamic Supply Current vs V
IN
V
IN
(V)
1
DYNAMIC SUPPLY CURRENT (
µ
A)
30
40
50
5
3410 G11
20
10
0
2
3
4
6
V
OUT
= 1.2V
I
LOAD =
0A
R
DS(ON)
vs Temperature
TEMPERATURE (
°C)
50
0
R
DS (ON)
(
)
0.2
0.6
0.8
1.0
10
30
50
130
3410 G10
0.4
30
10
70
90 110
1.2
V
IN
= 2.7V
V
IN
= 3.6V
V
IN
= 4.2V
V
IN
= 2.7V
V
IN
= 3.6V
V
IN
= 4.2V
SYNCHRONOUS SWITCH
MAIN SWITCH
5
LTC3410
3410f
200
µs/DIV
RUN
2V/DIV
V
OUT
1V/DIV
I
L
200mA/DIV
3410 G19
V
IN
= 3.6V
V
OUT
= 1.8V
I
LOAD
= 0A
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
(From Figure 1 Except for the Resistive Divider Resistor Values)
Start-Up from Shutdown
Load Step
Load Step
200
µs/DIV
RUN
2V/DIV
I
L
200mA/DIV
V
OUT
1V/DIV
3410 G16
V
IN
= 3.6V
V
OUT
= 1.8V
I
LOAD
= 300mA
10
µs/DIV
V
OUT
100mV/DIV
AC COUPLED
I
L
200mA/DIV
I
LOAD
200mA/DIV
3410 G17
V
IN
= 3.6V
V
OUT
= 1.8V
I
LOAD
= 0mA TO 300mA
10
µs/DIV
V
OUT
100mV/DIV
AC COUPLED
I
L
200mA/DIV
I
LOAD
200mA/DIV
3410 G18
V
IN
= 3.6V
V
OUT
= 1.8V
I
LOAD
= 20mA TO 300mA
2
µs/DIV
SW
5V/DIV
V
IN
= 3.6V
V
OUT
= 1.8V
I
LOAD
= 10mA
I
L
100mA/DIV
V
OUT
50mV/DIV
AC COUPLED
3410 G15
Switch Leakage vs Input Voltage
INPUT VOLTAGE (V)
0
LEAKAGE CURRENT (pA)
200
500
550
600
2
4
5
3410 G14
100
400
300
150
450
50
0
350
250
1
3
6
MAIN
SWITCH
SYNCHRONOUS
SWITCH
Burst Mode Operation
Start-Up from Shutdown
6
LTC3410
3410f
U
U
U
PI FU CTIO S
RUN (Pin 1): Run Control Input. Forcing this pin above
1.5V enables the part. Forcing this pin below 0.3V shuts
down the device. In shutdown, all functions are disabled
drawing <1
µA supply current. Do not leave RUN floating.
GND (Pins 2, 5): Ground Pin.
SW (Pin 3): Switch Node Connection to Inductor. This pin
connects to the drains of the internal main and synchro-
nous power MOSFET switches.
V
IN
(Pin 4): Main Supply Pin. Must be closely decoupled
to GND, Pin 2, with a 2.2
µF or greater ceramic capacitor.
V
FB
(Pin 6): Feedback Pin. Receives the feedback voltage
from an external resistive divider across the output.
FU CTIO AL DIAGRA
U
U
W
+
+
+
EA
+
I
RCMP
+
I
COMP
6
1
RUN
OSC
SLOPE
COMP
OSC
FREQ
SHIFT
0.8V
0.8V REF
SHUTDOWN
0.4V
0.65V
SLEEP
V
IN
V
FB
EN
BURST
V
IN
S
R
RS LATCH
SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
ANTI-
SHOOT-
THRU
Q
Q
5
4
SW
3
5
GND
3410 BD
2
7
LTC3410
3410f
OPERATIO
U
(Refer to Functional Diagram)
Main Control Loop
The LTC3410 uses a constant frequency, current mode
step-down architecture. Both the main (P-channel
MOSFET) and synchronous (N-channel MOSFET) switches
are internal. During normal operation, the internal top
power MOSFET is turned on each cycle when the oscillator
sets the RS latch, and turned off when the current com-
parator, I
COMP
, resets the RS latch. The peak inductor
current at which I
COMP
resets the RS latch, is controlled by
the output of error amplifier EA. The V
FB
pin, described in
the Pin Functions section, allows EA to receive an output
feedback voltage from an external resistive divider. When
the load current increases, it causes a slight decrease in
the feedback voltage relative to the 0.8V reference, which
in turn, causes the EA amplifier's output voltage to in-
crease until the average inductor current matches the new
load current. While the top MOSFET is off, the bottom
MOSFET is turned on until either the inductor current
starts to reverse, as indicated by the current reversal
comparator I
RCMP
, or the beginning of the next clock cycle.
Burst Mode Operation
The LTC3410 is capable of Burst Mode operation in which
the internal power MOSFETs operate intermittently based
on load demand.
When the converter is in Burst Mode operation, the peak
current of the inductor is set to approximately 70mA re-
gardless of the output load. Each burst event can last from
a few cycles at light loads to almost continuously cycling
with short sleep intervals at moderate loads. In between
these burst events, the power MOSFETs and any unneeded
circuitry are turned off, reducing the quiescent current to
26
µA. In this sleep state, the load current is being supplied
solely from the output capacitor. As the output voltage
droops, the EA amplifier's output rises above the sleep
threshold signaling the BURST comparator to trip and
turn the top MOSFET on. This process repeats at a rate that
is dependent on the load demand.
Short-Circuit Protection
When the output is shorted to ground, the frequency of the
oscillator is reduced to about 310kHz, 1/7 the nominal
frequency. This frequency foldback ensures that the in-
ductor current has more time to decay, thereby preventing
runaway. The oscillator's frequency will progressively
increase to 2.25MHz when V
FB
rises above 0V.
Dropout Operation
As the input supply voltage decreases to a value approach-
ing the output voltage, the duty cycle increases toward the
maximum on-time. Further reduction of the supply volt-
age forces the main switch to remain on for more than one
cycle until it reaches 100% duty cycle. The output voltage
will then be determined by the input voltage minus the
voltage drop across the P-channel MOSFET and the
inductor.
8
LTC3410
3410f
OPERATIO
U
(Refer to Functional Diagram)
Another important detail to remember is that at low input
supply voltages, the R
DS(ON)
of the P-channel switch
increases (see Typical Performance Characteristics). There-
fore, the user should calculate the power dissipation when
the LTC3410 is used at 100% duty cycle with low input
voltage (See Thermal Considerations in the Applications
Information section).
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant fre-
quency architectures by preventing subharmonic oscilla-
tions at high duty cycles. It is accomplished internally by
adding a compensating ramp to the inductor current
signal at duty cycles in excess of 40%. Normally, this
results in a reduction of maximum inductor peak current
for duty cycles > 40%. However, the LTC3410 uses a
patented scheme that counteracts this compensating ramp,
which allows the maximum inductor peak current to
remain unaffected throughout all duty cycles.
9
LTC3410
3410f
The basic LTC3410 application circuit is shown in Figure 1.
External component selection is driven by the load require-
ment and begins with the selection of L followed by C
IN
and
C
OUT
.
Inductor Selection
For most applications, the value of the inductor will fall in
the range of 2.2
µH to 4.7µH. Its value is chosen based on
the desired ripple current. Large value inductors lower
ripple current and small value inductors result in higher
ripple currents. Higher V
IN
or V
OUT
also increases the ripple
current as shown in equation 1. A reasonable starting point
for setting ripple current is
I
L
= 120mA (40% of 300mA).
=
( )( )
-
I
f L
V
V
V
L
OUT
OUT
IN
1
1
1
( )
The DC current rating of the inductor should be at least
equal to the maximum load current plus half the ripple
current to prevent core saturation. Thus, a 360mA rated
inductor should be enough for most applications (300mA
+ 60mA). For better efficiency, choose a low DC-resistance
inductor.
The inductor value also has an effect on Burst Mode
operation. The transition to low current operation begins
when the inductor current peaks fall to approximately
100mA. Lower inductor values (higher
I
L
) will cause this
to occur at lower load currents, which can cause a dip in
efficiency in the upper range of low current operation. In
Burst Mode operation, lower inductance values will cause
the burst frequency to increase.
APPLICATIO S I FOR ATIO
W
U
U
U
Inductor Core Selection
Different core materials and shapes will change the size/
current and price/current relationship of an inductor. Tor-
oid or shielded pot cores in ferrite or permalloy materials
are small and don't radiate much energy, but generally cost
more than powdered iron core inductors with similar
electrical characteristics. The choice of which style induc-
tor to use often depends more on the price vs size require-
ments and any radiated field/EMI requirements than on
what the LTC3410 requires to operate. Table 1 shows some
typical surface mount inductors that work well in
LTC3410 applications.
Table 1. Representative Surface Mount Inductors
MAX DC
MANUFACTURER PART NUMBER
VALUE CURRENT DCR HEIGHT
Taiyo Yuden
CB2016T2R2M
2.2
µH 510mA 0.13 1.6mm
CB2012T2R2M
2.2
µH 530mA 0.33 1.25mm
LBC2016T3R3M
3.3
µH 410mA 0.27 1.6mm
Panasonic
ELT5KT4R7M
4.7
µH 950mA 0.2 1.2mm
Sumida
CDRH2D18/LD
4.7
µH 630mA 0.086 2mm
Murata
LQH32CN4R7M23 4.7
µH 450mA 0.2 2mm
Taiyo Yuden
NR30102R2M
2.2
µH 1100mA 0.1 1mm
NR30104R7M
4.7
µH 750mA 0.19 1mm
FDK
FDKMIPF2520D
4.7
µH 1100mA 0.11 1mm
FDKMIPF2520D
3.3
µH 1200mA 0.1 1mm
FDKMIPF2520D
2.2
µH 1300mA 0.08 1mm
C
IN
and C
OUT
Selection
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle V
OUT
/V
IN
. To prevent large
voltage transients, a low ESR input capacitor sized for the
maximum RMS current must be used. The maximum
RMS capacitor current is given by:
C
required I
I
V
V
V
V
IN
RMS
OMAX
OUT
IN
OUT
IN
-
(
)
[
]
1 2
/
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT
/2. This simple worst-case condition is com-
monly used for design because even significant deviations
do not offer much relief. Note that the capacitor
manufacturer's ripple current ratings are often based on
2000 hours of life. This makes it advisable to further derate
the capacitor, or choose a capacitor rated at a higher
V
IN
C
IN
4.7
µF
CER
V
IN
2.7V
TO 5.5V
LTC3410
RUN
4.7
µH
10pF
232k
464k
3410 F01
SW
V
FB
GND
C
OUT
4.7
µF
CER
V
OUT
1.2V
Figure 1. High Efficiency Step-Down Converter
10
LTC3410
3410f
V
FB
GND
LTC3410
0.8V
V
OUT
5.5V
R2
R1
3410 F02
can potentially cause a voltage spike at V
IN
, large enough
to damage the part.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
The recommended capacitance value to use is 4.7
µF for
both input and output capacitor. For applications with
V
OUT
greater than 2.5V, the recommended value for output
capacitance should be increased. See Table 2.
Table 2. Capacitance Selection
OUTPUT
OUTPUT
INPUT
VOLTAGE RANGE
CAPACITANCE
CAPACITANCE
0.8V
V
OUT
2.5V
4.7
µF
4.7
µF
V
OUT
> 2.5V
10
µH or 2x 4.7µF
4.7
µF
Output Voltage Programming
The output voltage is set by a resistive divider according
to the following formula:
V
V
R
R
OUT
=
+
0 8
1
2
1
2
.
( )
The external resistive divider is connected to the output,
allowing remote voltage sensing as shown in Figure 2.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% (L1 + L2 + L3 + ...)
temperature than required. Always consult the manufac-
turer if there is any question.
The selection of C
OUT
is driven by the required effective
series resistance (ESR). Typically, once the ESR require-
ment for C
OUT
has been met, the RMS current rating
generally far exceeds the I
RIPPLE(P-P)
requirement. The
output ripple
V
OUT
is determined by:
+
V
I ESR
fC
OUT
L
OUT
1
8
where f = operating frequency, C
OUT
= output capacitance
and
I
L
= ripple current in the inductor. For a fixed output
voltage, the output ripple is highest at maximum input
voltage since
I
L
increases with input voltage.
If tantalum capacitors are used, it is critical that the
capacitors are surge tested for use in switching power
supplies. An excellent choice is the AVX TPS series of
surface mount tantalum. These are specially constructed
and tested for low ESR so they give the lowest ESR for a
given volume. Other capacitor types include Sanyo
POSCAP, Kemet T510 and T495 series, and Sprague 593D
and 595D series. Consult the manufacturer for other
specific recommendations.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. Because the
LTC3410's control loop does not depend on the output
capacitor's ESR for stable operation, ceramic capacitors
can be used freely to achieve very low output ripple and
small circuit size.
However, care must be taken when ceramic capacitors are
used at the input and the output. When a ceramic capacitor
is used at the input and the power is supplied by a wall
adapter through long wires, a load step at the output can
induce ringing at the input, V
IN
. At best, this ringing can
couple to the output and be mistaken as loop instability. At
worst, a sudden inrush of current through the long wires
Figure 2. Setting the LTC3410 Output Voltage
APPLICATIO S I FOR ATIO
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LTC3410
3410f
APPLICATIO S I FOR ATIO
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where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC3410 circuits: V
IN
quiescent current and I
2
R
losses. The V
IN
quiescent current loss dominates the
efficiency loss at very low load currents whereas the I
2
R
loss dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence as illustrated in Figure 3.
1. The V
IN
quiescent current is due to two components:
the DC bias current as given in the electrical character-
istics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge, dQ, moves from V
IN
to ground. The resulting
dQ/dt is the current out of V
IN
that is typically larger than
the DC bias current. In continuous mode,
I
GATECHG
= f(Q
T
+ Q
B
) where Q
T
and Q
B
are the
gate charges of the internal top and bottom
switches. Both the DC bias and gate charge
losses are proportional to V
IN
and thus their effects will
be more pronounced at higher supply voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In
continuous mode, the average output current flowing
through inductor L is "chopped" between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
DS(ON)
and the duty cycle
(DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Charateristics
curves. Thus, to obtain I
2
R losses, simply add R
SW
to
R
L
and multiply the result by the square of the average
output current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for less
than 2% total additional loss.
Thermal Considerations
In most applications the LTC3410 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC3410 is running at high ambient
temperature with low supply voltage and high duty
cycles, such as in dropout, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 150
°C,
Figure 3. Power Loss vs Load Current
LOAD CURRENT (mA)
0.1
1
0.00001
POWER LOSS (W)
0.001
1
10
100
1000
3410 F03
0.0001
0.01
0.1
V
IN
= 3.6V
V
OUT
= 3.3V
V
OUT
= 1.8V
V
OUT
= 1.2V
12
LTC3410
3410f
APPLICATIO S I FOR ATIO
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both power switches will be turned off and the SW node
will become high impedance.
To avoid the LTC3410 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
T
R
= (P
D
)(
JA
)
where P
D
is the power dissipated by the regulator and
JA
is the thermal resistance from the junction of the die to
the ambient temperature.
The junction temperature, T
J
, is given by:
T
J
= T
A
+ T
R
where T
A
is the ambient temperature.
As an example, consider the LTC3410 in dropout at an
input voltage of 2.7V, a load current of 300mA and an
ambient temperature of 70
°C. From the typical perfor-
mance graph of switch resistance, the R
DS(ON)
of the
P-channel switch at 70
°C is approximately 1.0.
Therefore, power dissipated by the part is:
P
D
= I
LOAD
2
· R
DS(ON)
= 90mW
For the SC70 package, the
JA
is 250
°C/W. Thus, the
junction temperature of the regulator is:
T
J
= 70
°C + (0.09)(250) = 92.5°C
which is well below the maximum junction temperature
of 125
°C.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R
DS(ON)
).
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to (
I
LOAD
· ESR), where ESR is the effective series
resistance of C
OUT
.
I
LOAD
also begins to charge or
discharge C
OUT
, which generates a feedback error signal.
The regulator loop then acts to return V
OUT
to its steady-
state value. During this recovery time V
OUT
can be moni-
tored for overshoot or ringing that would indicate a stability
problem. For a detailed explanation of switching control
loop theory, see Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1
µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 · C
LOAD
).
Thus, a 10
µF capacitor charging to 3.3V would require a
250
µs rise time, limiting the charging current to about
130mA.
13
LTC3410
3410f
APPLICATIO S I FOR ATIO
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PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3410. These items are also illustrated graphically in
Figures 4 and 5. Check the following in your layout:
1. The power traces, consisting of the GND trace, the SW
trace and the V
IN
trace should be kept short, direct and
wide.
2. Does the V
FB
pin connect directly to the feedback
resistors? The resistive divider R1/R2 must be con-
nected between the (+) plate of C
OUT
and ground.
3. Does the (+) plate of C
IN
connect to V
IN
as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
4. Keep the () plates of C
IN
and C
OUT
as close as possible.
5. Keep the switching node, SW, away from the sensitive
V
FB
node.
Figure 4. LTC3410 Layout Diagram
RUN
LTC3410
GND
SW
L1
R2
R1
C
FWD
BOLD LINES INDICATE HIGH CURRENT PATHS
V
IN
V
OUT
3410 F04
4
6
5
1
3
+
2
V
FB
V
IN
C
IN
C
OUT
Figure 5. LTC3410 Suggested Layout
LTC3410
GND
3410 F05
PIN 1
V
OUT
V
IN
VIA TO V
OUT
SW
VIA TO V
IN
VIA TO GND
C
OUT
C
IN
L1
R2
C
FWD
R1
14
LTC3410
3410f
APPLICATIO S I FOR ATIO
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Design Example
As a design example, assume the LTC3410 is used in a
single lithium-ion battery-powered cellular phone
application. The V
IN
will be operating from a maximum of
4.2V down to about 2.7V. The load current requirement
is a maximum of 0.3A but most of the time it will be in
standby mode, requiring only 2mA. Efficiency at both low
and high load currents is important. Output voltage is
3V. With this information we can calculate L using
Equation (1),
L
f
I
V
V
V
L
OUT
OUT
IN
=
( )
( )
-
1
1
3
( )
Substituting V
OUT
= 3V, V
IN
= 4.2V,
I
L
= 100mA
and f = 2.25MHz in Equation (3) gives:
L
V
MHz
mA
V
V
H
=
-
=
3
2 25
100
1
3
4 2
3 8
.
(
)
.
.
µ
A 4.7
µH inductor works well for this application. For best
efficiency choose a 350mA or greater inductor with less
than 0.3
series resistance.
C
IN
will require an RMS current rating of at least 0.125A
I
LOAD(MAX)
/2 at temperature and C
OUT
will require an ESR
of less than 0.5
. In most cases, a ceramic capacitor will
satisfy this requirement. From Table 2, Capacitance Selec-
tion, C
OUT
= 10
µF and C
IN
= 4.7
µF.
For the feedback resistors, choose R1 = 301k. R2 can
then be calculated from equation (2) to be:
R
V
R
k use
k
OUT
2
0 8
1 1 827 8
825
=
-
=
.
. ;
Figure 6 shows the complete circuit along with its
efficiency curve.
Figure 6a
V
IN
C
IN
4.7
µF
CER
V
IN
2.7V
TO 4.2V
LTC3410
RUN
3
4.7
µH*
10pF
825k
301k
3410 F06a
6
4
1
2, 5
SW
V
FB
GND
C
OUT
10
µF
CER
V
OUT
3V
TAIYO YUDEN JMK212BJ106
TAIYO YUDEN JMK212BJ475
*MURATA LQH32CN4R7M23
Figure 6b
Figure 6c
I
LOAD
(mA)
0.1
0
10
20
30
40
EFFICIENCY (%)
50
60
70
80
90
100
10
100
1
1000
3410 F06b
V
IN
= 3.6V
V
IN
= 4.2V
V
OUT
100mV/DIV
AC COUPLED
I
L
200mA/DIV
I
LOAD
200mA/DIV
20
µs/DIV
3410 F06c
V
IN
= 3.6V
V
OUT
= 3V
I
LOAD
= 100mA TO 300mA
15
LTC3410
3410f
U
PACKAGE DESCRIPTIO
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
SC6 Package
6-Lead Plastic SC70
(Reference LTC DWG # 05-08-1638)
1.15 1.35
(NOTE 4)
1.80 2.40
0.15 0.30
6 PLCS (NOTE 3)
SC6 SC70 1205 REV B
1.80 2.20
(NOTE 4)
0.65 BSC
PIN 1
0.80 1.00
1.00 MAX
0.00 0.10
REF
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. DETAILS OF THE PIN 1 INDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE INDEX AREA
7. EIAJ PACKAGE REFERENCE IS EIAJ SC-70
8. JEDEC PACKAGE REFERENCE IS MO-203 VARIATION AB
2.8 BSC
0.47
MAX
0.65
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.8 REF
1.00 REF
INDEX AREA
(NOTE 6)
0.10 0.18
(NOTE 3)
0.26 0.46
GAUGE PLANE
0.15 BSC
0.10 0.40
16
LTC3410
3410f
PART NUMBER
DESCRIPTION
COMMENTS
LT1616
500mA (I
OUT
), 1.4MHz, High Efficiency Step-Down
90% Efficiency, V
IN
= 3.6V to 25V, V
OUT
= 1.25V, I
Q
= 1.9mA,
DC/DC Converter
I
SD
= <1
µA, ThinSOT Package
LT1676
450mA (I
OUT
), 100kHz, High Efficiency Step-Down
90% Efficiency, V
IN
= 7.4V to 60V, V
OUT
= 1.24V, I
Q
= 3.2mA,
DC/DC Converter
I
SD
= 2.5
µA, S8 Package
LT1776
500mA (I
OUT
), 200kHz, High Efficiency Step-Down
90% Efficiency, V
IN
= 7.4V to 40V, V
OUT
= 1.24V, I
Q
= 3.2mA,
DC/DC Converter
I
SD
= 30
µA, N8, S8 Packages
LTC1877
600mA (I
OUT
), 550kHz, Synchronous Step-Down
95% Efficiency, V
IN
= 2.7V to 10V, V
OUT
= 0.8V, I
Q
= 10
µA,
DC/DC Converter
I
SD
= <1
µA, MS8 Package
LTC1878
600mA (I
OUT
), 550kHz, Synchronous Step-Down
95% Efficiency, V
IN
= 2.7V to 6V, V
OUT
= 0.8V, I
Q
= 10
µA,
DC/DC Converter
I
SD
= <1
µA, MS8 Package
LTC1879
1.2A (I
OUT
), 550kHz, Synchronous Step-Down
95% Efficiency, V
IN
= 2.7V to 10V, V
OUT
= 0.8V, I
Q
= 15
µA,
DC/DC Converter
I
SD
= <1
µA, TSSOP-16 Package
LTC3403
600mA (I
OUT
), 1.5MHz, Synchronous Step-Down
96% Efficiency, V
IN
= 2.5V to 5.5V, V
OUT
= Dynamically Adjustable,
DC/DC Converter with Bypass Transistor
I
Q
= 20
µA, I
SD
= <1
µA, DFN Package
LTC3404
600mA (I
OUT
), 1.4MHz, Synchronous Step-Down
95% Efficiency, V
IN
= 2.7V to 6V, V
OUT
= 0.8V, I
Q
= 10
µA,
DC/DC Converter
I
SD
= <1
µA, MS8 Package
LTC3405/LTC3405A
300mA (I
OUT
), 1.5MHz, Synchronous Step-Down
96% Efficiency, V
IN
= 2.5V to 5.5V, V
OUT
= 0.8V, I
Q
= 20
µA,
DC/DC Converter
I
SD
= <1
µA, ThinSOT Package
LTC3406
600mA (I
OUT
), 1.5MHz, Synchronous Step-Down
96% Efficiency, V
IN
= 2.5V to 5.5V, V
OUT
= 0.6V, I
Q
= 20
µA,
DC/DC Converter
I
SD
= <1
µA, ThinSOT Package
LTC3409
600mA (I
OUT
), 1.5MHz/2.25MHz, Synchronous
95% Efficiency, V
IN
= 1.6V to 5.5V, V
OUT
= 0.613V, I
Q
= 65
µA,
Step-Down DC/DC Converter
DD8 Package
LTC3410B
300mA (I
OUT
), 2.25MHz, Synchronous Step-Down
96% Efficiency, V
IN
= 2.5V to 3.5V, V
OUT(MIN)
= 0.8V, I
Q
= 200
µA,
DC/DC Converter with Burst Disabled
I
SD
= <1
µA, SC70 Package
LTC3411
1.25A (I
OUT
), 4MHz, Synchronous Step-Down
95% Efficiency, V
IN
= 2.5V to 5.5V, V
OUT
= 0.8V, I
Q
= 60
µA,
DC/DC Converter
I
SD
= <1
µA, MS Package
LTC3412
2.5A (I
OUT
), 4MHz, Synchronous Step-Down
95% Efficiency, V
IN
= 2.5V to 5.5V, V
OUT
= 0.8V, I
Q
= 60
µA,
DC/DC Converter
I
SD
= <1
µA, TSSOP-16E Package
LTC3440
600mA (I
OUT
), 2MHz, Synchronous Buck-Boost
95% Efficiency, V
IN
= 2.5V to 5.5V, V
OUT
= 2.5V, I
Q
= 25
µA,
DC/DC Converter
I
SD
= <1
µA, MS Package
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
FAX: (408) 434-0507
www.linear.com
LT 1205 · PRINTED IN USA
© LINEAR TECHNOLOGY CORPORATION 2005
U
TYPICAL APPLICATIO
RELATED PARTS
V
IN
C
IN
4.7
µF
V
IN
2.7V
TO 4.2V
LTC3410
RUN
3
4.7
µH*
10pF
402k
464k
3410 TA02
6
4
1
2, 5
SW
V
FB
GND
C
OUT
4.7
µF
V
OUT
1.5V
TAIYO YUDEN JMK212BJ475
*FDK MIPF2520D
I
LOAD
(mA)
0.1
0
10
20
30
40
EFFICIENCY (%)
50
60
70
80
90
100
10
100
1
1000
3410 TA03
V
IN
= 2.7V
V
IN
= 3.6V
V
IN
= 4.2V
Efficiency
V
OUT
100mV/DIV
AC COUPLED
I
L
200mA/DIV
I
LOAD
200mA/DIV
20
µs/DIV
3410 TA04
V
IN
= 3.6V
V
OUT
= 1.5V
I
LOAD
= 100mA TO 300mA
Load Step
Using Low Profile Components, <1mm Height
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