1
LTC1665/LTC1660
Micropower Octal
8-Bit and 10-Bit DACs
The 8-bit LTC
®
1665 and 10-bit LTC1660 integrate eight
accurate, serially addressable digital-to-analog convert-
ers (DACs) in tiny 16-pin narrow SSOP packages. Each
buffered DAC draws just 56
µ
A total supply current, yet is
capable of supplying DC output currents in excess of
5mA and reliably driving capacitive loads to 1000pF.
Sleep mode further reduces total supply current to 1
µ
A.
Linear Technology's proprietary, inherently monotonic
voltage interpolation architecture provides excellent lin-
earity while allowing for an exceptionally small external
form factor.
Ultralow supply current, power-saving Sleep mode and
extremely compact size make the LTC1665 and LTC1660
ideal for battery-powered applications, while their ease of
use, high performance and wide supply range make them
excellent choices as general purpose converters.
s
Tiny: 8 DACs in the Board Space of an SO-8
s
Micropower: 56
µ
A per DAC Plus
1
µ
A Sleep Mode for Extended Battery Life
s
Pin Compatible 8-Bit LTC1665 and 10-Bit LTC1660
s
Wide 2.7V to 5.5V Supply Range
s
Rail-to-Rail Voltage Outputs Drive 1000pF
s
Reference Range Includes Supply for Ratiometric
0V-to-V
CC
Output
s
Reference Input Impedance is Constant--
Eliminates External Buffer
s
Mobile Communications
s
Remote Industrial Devices
s
Automatic Calibration for Manufacturing
s
Portable Battery-Powered Instruments
s
Trim/Adjust Applications
LTC1665 Differential Nonlinearity (DNL)
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
BLOCK DIAGRA
W
2
15
1
GND
V
OUT A
V
OUT B
V
OUT C
V
OUT D
REF
CS/LD
SCK
V
CC
V
OUT H
V
OUT G
V
OUT F
V
OUT E
CLR
D
OUT
D
IN
1665/60 BD
16
DAC A
DAC H
3
14
DAC B
DAC G
4
13
DAC C
DAC F
5
7
6
8
10
11
9
12
DAC D
DAC E
ADDRESS
DECODER
CONTROL
LOGIC
SHIFT REGISTER
CODE
0
64
128
192
255
LSB
1665/60 G09
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
V
CC
= 5V
V
REF
= 4.096V
CODE
0
256
512
768
1023
LSB
1665/60 G13
1
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1
V
CC
= 5V
V
REF
= 4.096V
LTC1660 Differential Nonlinearity (DNL)
, LTC and LT are registered trademarks of Linear Technology Corporation.
2
LTC1665/LTC1660
A
U
G
W
A
W
U
W
A
R
BSOLUTE
XI
TI
S
ORDER PART
NUMBER
W
U
U
PACKAGE/ORDER I FOR ATIO
T
JMAX
= 125
°
C,
JA
= 150
°
C/W (GN)
T
JMAX
= 125
°
C,
JA
= 100
°
C/W (N)
Consult factory for Military grade parts.
(Note 1)
V
CC
to GND .............................................. 0.2V to 7.5V
Logic Inputs to GND ................................ 0.2V to 7.5V
V
OUT A
, V
OUT B
...V
OUT H
,
REF to GND ................................. 0.2V to (V
CC
+ 0.2V)
Maximum Junction Temperature ......................... 125
°
C
Operating Temperature Range
LTC1665C/LTC1660C ............................ 0
°
C to 70
°
C
LTC1665I/LTC1660I .......................... 40
°
C to 85
°
C
Storage Temperature Range ................ 65
°
C to 150
°
C
Lead Temperature (Soldering, 10 sec)................ 300
°
C
LTC1665CGN
LTC1665CN
LTC1665IGN
LTC1665IN
LTC1660CGN
LTC1660CN
LTC1660IGN
LTC1660IN
GN PART MARKING
1665
1665I
1660
1660I
1
2
3
4
5
6
7
8
TOP VIEW
GN PACKAGE
16-LEAD PLASTIC SSOP
N PACKAGE
16-LEAD PDIP
16
15
14
13
12
11
10
9
GND
V
OUT A
V
OUT B
V
OUT C
V
OUT D
REF
CS/LD
SCK
V
CC
V
OUT H
V
OUT G
V
OUT F
V
OUT E
CLR
D
OUT
D
IN
ELECTRICAL C
C
HARA TERISTICS
The
q
denotes specifications which apply over the full operating temperature range, otherwise specifications
are at T
A
= 25
°
C. V
CC
= 2.7V to 5.5V, V
REF
V
CC
, V
OUT
unloaded, unless otherwise noted.
LTC1665
LTC1660
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Accuracy
Resolution
q
8
10
Bits
Monotonicity
V
REF
V
CC
0.1V (Note 2)
q
8
10
Bits
DNL
Differential Nonlinearity
V
REF
V
CC
0.1V (Note 2)
q
±
0.1
±
0.5
±
0.2
±
0.75
LSB
INL
Integral Nonlinearity
V
REF
V
CC
0.1V (Note 2)
q
±
0.2
±
1.0
±
0.6
±
2.5
LSB
V
OS
Offset Error
(Note 7)
q
±
10
±
30
±
10
±
30
mV
V
OS
Temperature Coefficient
q
±
15
±
15
µ
V/
°
C
FSE
Full-Scale Error
V
CC
= 5V, V
REF
= 4.096V
q
±
1
±
4
±
3
±
15
LSB
Full-Scale Error Temperature Coefficient
q
±
30
±
30
µ
V/
°
C
PSR
Power Supply Rejection
V
REF
= 2.5V
0.045
0.18
LSB/V
SYMBOL
PARAMETER
CONDITONS
MIN
TYP
MAX
UNITS
Reference Input
Input Voltage Range
q
0
V
CC
V
Resistance
Not in Sleep Mode
q
35
65
k
Capacitance
(Note 6)
15
pF
I
REF
Reference Current
Sleep Mode
q
0.001
1
µ
A
Power Supply
V
CC
Positive Supply Voltage
For Specified Performance
q
2.7
5.5
V
I
CC
Supply Current
V
CC
= 5V (Note 3)
q
450
730
µ
A
V
CC
= 3V (Note 3)
q
340
550
µ
A
Sleep Mode (Note 3)
q
1
3
µ
A
The
q
denotes specifications which apply over the full operating temperature range, otherwise specifications
are at T
A
= 25
°
C. V
CC
= 2.7V to 5.5V, V
REF
V
CC
, V
OUT
unloaded, unless otherwise noted.
3
LTC1665/LTC1660
ELECTRICAL C
C
HARA TERISTICS
TI I G CHARACTERISTICS
U
W
The
q
denotes specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25
°
C. (See Figure 1)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DC Performance
Short-Circuit Current Low
V
OUT
= 0V, V
CC
= 5.5V, V
REF
= 5.1V, Code = Full Scale
q
10
30
100
mA
Short-Circuit Current High
V
OUT
= V
CC
= 5.5V, V
REF
= 5.1V, Code = 0
q
10
27
120
mA
AC Performance
Voltage Output Slew Rate
Rising (Notes 4, 5)
0.60
V/
µ
s
Falling (Notes 4, 5)
0.25
V/
µ
s
Voltage Output Settling Time
To
±
0.5LSB (Notes 4, 5)
30
µ
s
Capacitive Load Driving
1000
pF
Digital I/O
V
IH
Digital Input High Voltage
V
CC
= 2.7V to 5.5V
q
2.4
V
V
CC
= 2.7V to 3.6V
q
2.0
V
V
IL
Digital Input Low Voltage
V
CC
= 4.5V to 5.5V
q
0.8
V
V
CC
= 2.7V to 5.5V
q
0.6
V
V
OH
Digital Output High Voltage
I
OUT
= 1mA, D
OUT
Only
q
V
CC
1
V
V
OL
Digital Output Low Voltage
I
OUT
= 1mA, D
OUT
Only
q
0.4
V
I
LK
Digital Input Leakage
V
IN
= GND to V
CC
q
±
10
µ
A
C
IN
Digital Input Capacitance
(Note 6)
q
10
pF
The
q
denotes specifications which apply over the full operating temperature range, otherwise specifications
are at T
A
= 25
°
C. V
CC
= 2.7V to 5.5V, V
REF
V
CC
, V
OUT
unloaded, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
= 4.5V to 5.5V
t
1
D
IN
Valid to SCK Setup
q
40
15
ns
t
2
D
IN
Valid to SCK Hold
q
0
11
ns
t
3
SCK High Time
(Note 6)
q
30
5
ns
t
4
SCK Low Time
(Note 6)
q
30
7
ns
t
5
CS/LD Pulse Width
(Note 6)
q
80
30
ns
t
6
LSB SCK High to CS/LD High
(Note 6)
q
30
4
ns
t
7
CS/LD Low to SCK High
(Note 6)
q
80
26
ns
t
8
D
OUT
Propagation Delay
C
LOAD
= 15pF (Note 6)
q
5
26
80
ns
t
9
SCK Low to CS/LD Low
(Note 6)
q
20
0
ns
t
10
CLR Pulse Width
(Note 6)
q
100
37
ns
t
11
CS/LD High to SCK Positive Edge
(Note 6)
q
30
0
ns
SCK Frequency
Continuous Square Wave (Note 6)
q
5.00
MHz
Continuous 23% Duty Cycle Pulse (Note 6)
q
7.69
MHz
Gated Square Wave (Note 6)
q
16.7
MHz
V
CC
= 2.7V to 5.5V
t
1
D
IN
Valid to SCK Setup
(Note 6)
q
60
20
ns
t
2
D
IN
Valid to SCK Hold
(Note 6)
q
0
14
ns
t
3
SCK High Time
(Note 6)
q
50
8
ns
t
4
SCK Low Time
(Note 6)
q
50
12
ns
t
5
CS/LD Pulse Width
(Note 6)
q
100
30
ns
4
LTC1665/LTC1660
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t
6
LSB SCK High to CS/LD High
(Note 6)
q
50
5
ns
t
7
CS/LD Low to SCK High
(Note 6)
q
100
27
ns
t
8
D
OUT
Propagation Delay
C
LOAD
= 15pF (Note 6)
q
5
47
150
ns
t
9
SCK Low to CS/LD Low
(Note 6)
q
30
0
ns
t
10
CLR Pulse Width
(Note 6)
q
120
41
ns
t
11
CS/LD High to SCK Positive Edge
(Note 6)
q
30
0
ns
SCK Frequency
Continuous Square Wave (Note 6)
q
3.85
MHz
Continuous 28% Duty Cycle Pulse
q
5.55
MHz
Gated Square Wave
q
10
MHz
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
TI I G CHARACTERISTICS
U
W
The
q
denotes specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25
°
C. (See Figure 1)
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: Nonlinearity and monotonicity are defined from code 4 to code
255 for the LTC1665 and from code 20 to code 1023 for the LTC1660.
See Applications Information.
Note 3: Digital inputs at 0V or V
CC
.
Note 4: Load is 10k
in parallel with 100pF.
Note 5: V
CC
= V
REF
= 5V. DAC switched between 0.1V
FS
and 0.9V
FS
,
i.e., codes 26 and 230 for the LTC1665 or codes 102 and 922 for the
LTC1660.
Note 6: Guaranteed by design and not production tested.
Note 7: Measured at code 4 for the LTC1665 and code 20 for the
LTC1660.
(LTC1665/LTC1660)
Midscale Output Voltage
vs Load Current
Midscale Output Voltage
vs Load Current
I
OUT
(mA)
30
20
10
0
10
20
30
V
OUT
(V)
1665/60 G01
3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
V
CC
= 4.5V
V
CC
= 5V
V
CC
= 5.5V
V
REF
= V
CC
CODE = 128 (LTC1665)
CODE = 512 (LTC1660)
SINK
SOURCE
I
OUT
(mA)
15
4
8
12
0
4
8
12 15
V
OUT
(V)
1665/60 G02
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
V
CC
= 2.7V
V
CC
= 3V
V
CC
= 3.6V
V
REF
= V
CC
CODE = 128 (LTC1665)
CODE = 512 (LTC1660)
SINK
SOURCE
5
LTC1665/LTC1660
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Supply Current vs Temperature
Large-Signal Step Response
Supply Current vs Logic Input Voltage
TIME (
µ
s)
0
20
40
60
80
100
V
OUT
(V)
1665/60 G05
5
4
3
2
1
0
10% TO
90% STEP
V
CC
= V
REF
= 5V
TEMPERATURE (
°
C)
55 35 15
5
25
45
65
85 105 125
SUPPLY CURRENT (
µ
A)
1665/60 G06
500
480
460
440
420
400
380
360
340
320
300
V
CC
= 5.5V
V
CC
= 4.5V
V
CC
= 3.6V
V
CC
= 2.7V
LOGIC INPUT VOLTAGE (V)
0
1
2
3
4
5
SUPPLY CURRENT (mA)
1665/60 G07
2
1.6
1.2
0.8
0.4
0
ALL DIGITAL INPUTS
SHORTED TOGETHER
(LTC1665/LTC1660)
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
CODE
0
64
128
192
255
LSB
1665/60 G08
1
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1
V
CC
= 5V
V
REF
= 4.096V
CODE
0
64
128
192
255
LSB
1665/60 G09
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
V
CC
= 5V
V
REF
= 4.096V
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
(LTC1665)
0
2
4
6
8
10
V
CC
V
OUT
(mV)
1665/60 G03
1400
1200
1000
800
600
400
200
0
55
°
C
25
°
C
125
°
C
V
REF
= 4.096V
V
OUT
< 1LSB
CODE = 255 (LTC1665)
CODE = 1023 (LTC1660)
|
I
OUT
|
(mA) (Sourcing)
Minimum Supply Headroom vs
Load Current (Output Sourcing)
Minimum V
OUT
vs
Load Current (Output Sinking)
|
I
OUT
|
(mA) (Sinking)
0
2
4
6
8
10
V
OUT
(mV)
1665/60 G04
1400
1200
1000
800
600
400
200
0
55
°
C
25
°
C
125
°
C
V
CC
= 5V
CODE = 0
6
LTC1665/LTC1660
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
(LTC1660)
Load Regulation vs Output Current
Load Regulation vs Output Current
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
CODE
0
256
512
768
1023
LSB
1665/60 G12
2.5
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.5
V
CC
= 5V
V
REF
= 4.096V
CODE
0
256
512
768
1023
LSB
1665/60 G13
1
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1
V
CC
= 5V
V
REF
= 4.096V
I
OUT
(mA)
2
1
0
1
2
V
OUT
(LSB)
2
1.5
1
0.5
0
0.5
1
1.5
2
1665/60 G14
V
CC
= V
REF
= 5V
CODE = 512
SINK
SOURCE
I
OUT
(
µ
A)
500
0
500
V
OUT
(LSB)
2
1.5
1
0.5
0
0.5
1
1.5
2
1665/60 G15
SINK
SOURCE
V
CC
= V
REF
= 3V
CODE = 512
Load Regulation vs Output Current
Load Regulation vs Output Current
I
OUT
(mA)
2
1
0
1
2
V
OUT
(LSB)
0.5
0.25
0
0.25
0.5
1665/60 G10
V
CC
= V
REF
= 5V
CODE = 128
SINK
SOURCE
I
OUT
(
µ
A)
500
0
500
V
OUT
(LSB)
0.5
0.25
0
0.25
0.5
1665/60 G11
SINK
SOURCE
V
CC
= V
REF
= 3V
CODE = 128
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
(LTC1665)
7
LTC1665/LTC1660
BLOCK DIAGRA
W
PI
N
FU
N
CTIO
N
S
U
U
U
GND (Pin 1): System Ground.
V
OUT A
to V
OUT H
(Pins 2-5 and 12-15): DAC Analog
Voltage Outputs. The output range is
0
255
256
1665
0
1023
1024
1660
to
V
for the LTC
to
V
for the LTC
REF
REF
REF (Pin 6): Reference Voltage Input. 0V
V
REF
V
CC
.
CS/LD (Pin 7): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on D
IN
into the register. When CS/LD is pulled high, SCK is
disabled and data is loaded from the shift register into the
specified DAC register(s), updating the analog output(s).
CMOS and TTL compatible.
SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL
compatible.
D
IN
(Pin 9): Serial Interface Data Input. Data on the D
IN
pin
is shifted into the 16-bit register on the rising edge of SCK.
CMOS and TTL compatible.
D
OUT
(Pin 10): Serial Interface Data Output. Data appears
on D
OUT
16 positive SCK edges after being applied to D
IN
.
May be tied to D
IN
of another LTC1665/LTC1660 for daisy-
chain operaton. CMOS and TTL compatible.
CLR (Pin 11): Asynchronous Clear Input. All internal shift
and DAC registers are cleared to zero at the falling edge of
the CLR signal, forcing the analog outputs to zero scale.
CMOS and TTL compatible.
V
CC
(Pin 16): Supply Voltage Input. 2.7V
V
CC
5.5V.
2
15
1
GND
V
OUT A
V
OUT B
V
OUT C
V
OUT D
REF
CS/LD
SCK
V
CC
V
OUT H
V
OUT G
V
OUT F
V
OUT E
CLR
D
OUT
D
IN
1665/60 BD
16
DAC A
DAC H
3
14
DAC B
DAC G
4
13
DAC C
DAC F
5
7
6
8
10
11
9
12
DAC D
DAC E
ADDRESS
DECODER
CONTROL
LOGIC
SHIFT REGISTER
(LTC1665/LTC1660)
8
LTC1665/LTC1660
TI I G DIAGRA
U
W
W
Figure 1
OPERATIO
U
Transfer Function
The transfer function is
V
k
V
for the LTC
V
k
V
for the LTC
OUT IDEAL
REF
OUT IDEAL
REF
(
)
(
)
=
=
256
1665
1024
1660
where k is the decimal equivalent of the binary DAC input
code and V
REF
is the voltage at REF (Pin 6).
Power-On Reset
The LTC1665 clears the outputs to zero scale when power
is first applied, making system initialization consistent and
repeatable.
Power Supply Sequencing
The voltage at REF (Pin 6) should be kept within the range
0.2V
V
REF
V
CC
+ 0.2V (see Absolute Maximum
Ratings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at V
CC
(Pin 16) is in transition.
Serial Interface
Referring to Figure 2a (2b): With CS/LD held low, data on
the D
IN
input is shifted into the 16-bit shift register on the
positive edge of SCK. The 4-bit DAC address, A3-A0, is
loaded first (see Table 2), then the 8-bit (10-bit) input
code, D7-D0 (D9-D0), ordered MSB-to-LSB in each case.
Four (two) don't-care bits, X3-X0 (X1-X0), are loaded last.
When the full 16-bit input word has been shifted in, CS/LD
is pulled high, loading the DAC register with the word and
causing the addressed DAC output(s) to update. The
clock is disabled internally when CS/LD is high. Note: SCK
must be low before CS/LD is pulled low.
The buffered serial output of the shift register is available
on the D
OUT
pin, which swings from GND to V
CC
. Data
appears on D
OUT
16 positive SCK edges after being applied
to D
IN
.
Multiple LTC1665/LTC1660's can be controlled from a
single 3-wire serial port (i.e., SCK, D
IN
and CS/LD) by
using the included "daisy-chain" facility. A series of
m
chips is configured by connecting each D
OUT
(except the
last) to D
IN
of the next chip, forming a single 16
m-bit shift
register. The SCK and CS/LD signals are common to all
D
IN
D
OUT
CS/LD
SCK
A3
A3
A3
A2
A2
X1
A1
X0
1665/60 F01
A1
X1
X0
t
2
t
8
t
9
t
11
t
5
t
7
t
6
t
1
t
3
t
4
9
LTC1665/LTC1660
Figure 2a. LTC1665 Register Loading Sequence
OPERATIO
U
Table 1a. LTC1665 Input Word
D
IN
D
OUT
SCK
CS/LD
A3
A2
INPUT WORD W
0
INPUT CODE
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
X3
X2
X1
X0
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
X3
X2
X1
X0
A3
1665/60 F02a
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(ENABLE CLK)
(UPDATE OUTPUT)
ADDRESS/CONTROL
DON'T CARE
INPUT WORD W
0
INPUT WORD W
1
D
IN
D
OUT
SCK
CS/LD
A3
A2
INPUT WORD W
0
INPUT CODE
DON'T CARE
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X1
X0
A3
A2
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X1
X0
A3
1665/60 F02b
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(ENABLE CLK)
(UPDATE OUTPUT)
ADDRESS/CONTROL
INPUT WORD W
0
INPUT WORD W
1
Figure 2b. LTC1660 Register Loading Sequence
A3 A2 A1
Address/Control
A0 D7 D6 D5 D4 D3 D2 D1 D0 X3
X1 X0
X2
Don't Care
Input Code
A3 A2 A1
Address/Control
A0 D9 D8 D7 D6 D5 D4 D3 D2 D1
X1 X0
D0
Input Code
Don't
Care
Table 1b. LTC1660 Input Word
chips in the chain. In use, CS/LD is held low while
m
16-bit words are clocked to D
IN
of the first chip; CS/LD is
then pulled high, updating all of them simultaneously.
Sleep Mode
DAC address 1110
b
is reserved for the special Sleep
instruction (see Table 2). In this mode, the digital interface
stays active while the analog circuits are disabled; static
power consumption is thus virtually eliminated. The refer-
ence input and analog outputs are set in a high impedance
10
LTC1665/LTC1660
OPERATIO
U
Table 2. DAC Address/Control Functions
ADDRESS/CONTROL
A3
A2
A1
A0
DAC STATUS
SLEEP STATUS
0
0
0
0
No Change
Wake
0
0
0
1
Load DAC A
Wake
0
0
1
0
Load DAC B
Wake
0
0
1
1
Load DAC C
Wake
0
1
0
0
Load DAC D
Wake
0
1
0
1
Load DAC E
Wake
0
1
1
0
Load DAC F
Wake
0
1
1
1
Load DAC G
Wake
1
0
0
0
Load DAC H
Wake
1
0
0
1
No Change
Wake
1
0
1
0
No Change
Wake
1
0
1
1
No Change
Wake
1
1
0
0
No Change
Wake
1
1
0
1
No Change
Wake
1
1
1
0
No Change
Sleep
1
1
1
1
Load
ALL DACs
Wake
with Same
8/10-Bit Code
state and all DAC settings are retained in memory so that
when Sleep mode is exited, the outputs of DACs not
updated by the Wake command are restored to their last
active state.
Sleep mode is initiated by performing a load sequence to
address 1110
b
(the DAC input word D7-D0 [D9-D0] is
ignored). Once in Sleep mode, a load sequence to any
other address (including "No Change" addresses 0000
b
and 1001-1101
b
) causes the LTC1665/LTC1660 to Wake.
It is possible to keep one or more chips of a daisy chain in
continuous Sleep mode by giving the Sleep instruction to
these chips each time the active chips in the chain are
updated.
Voltage Outputs
Each of the eight rail-to-rail output amplifiers contained in
these parts can source or sink up to 5mA. The outputs
swing to within a few millivolts of either supply rail when
unloaded and have an equivalent output resistance of 85
when driving a load to the rails. The output amplifiers are
stable driving capacitive loads up to 1000pF.
A small resistor placed in series with the output can be
used to achieve stability for any load capacitance. A 1
µ
F
load can be successfully driven by inserting a 20
resis-
tor; a 2.2
µ
F load needs only a 10
resistor. In either case,
larger values of resistance, capacitance or both may be
safely substituted for the values given.
Rail-to-Rail Output Considerations
In any rail-to-rail output voltage DAC, the output is limited
to voltages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 3b.
Similarly, limiting can occur near full scale when the REF
pin is tied to V
CC
. If V
REF
= V
CC
and the DAC full-scale error
(FSE) is positive, the output for the highest codes limits at
V
CC
as shown in Figure 3c. No full-scale limiting can occur
if V
REF
is less than V
CC
FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
11
LTC1665/LTC1660
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When V
REF
= V
CC
1665/60 F03
INPUT CODE
(b)
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
128
0
255
INPUT CODE
OUTPUT
VOLTAGE
(a)
V
REF
= V
CC
V
REF
= V
CC
(c)
INPUT CODE
OUTPUT
VOLTAGE
POSITIVE
FSE
OPERATIO
U
12
LTC1665/LTC1660
A Low Power Quad Trim Circuit with Coarse/Fine Adjustment
V
OUT4
V
OUT1
V
OUT3
V
OUT2
R1
COARSE
R1
COARSE
0.1
µ
F
0.1
µ
F
R1
4
1
2
3
11
3.3V
3.3V
R1
COARSE
R1
R2
R2
R2
FINE
R2
FINE
R2
FINE
R1
COARSE
R2
FINE
1665/60 TA01
2
15
1
GND
V
OUT A
V
OUT B
V
OUT C
V
OUT D
REF
CS/LD
SCK
3-WIRE
SERIAL
INTERFACE
V
CC
V
OUT H
V
OUT G
V
OUT F
V
OUT E
CLR
TO OTHER
LTC1665s
D
OUT
D
IN
16
DAC A
DAC H
3
14
DAC B
DAC G
4
13
DAC C
DAC F
5
7
6
8
11
9
12
DAC D
DAC E
ADDRESS
DECODER
CONTROL
LOGIC
SHIFT REGISTER
0.1
µ
F
0.1
µ
F
3.3V
1
4
2
U1
LTC1665
+
U2A
LT
®
1491
7
6
5
+
U2B
LT1491
LTC1258-2.5
0.1
µ
F
0.1
µ
F
R1
14
13
12
R2
+
U2D
LT1491
0.1
µ
F
R1
8
9
10
R2
+
U2C
LT1491
R2 >> R1
V
OUT 1
= V
OUT A
+
Example: For R1 = 110
and R2 = 11k,
V
OUT 1
= V
OUT A
+ 0.01 V
OUT B
))
R1
R2
V
OUT B
Similarly V
OUT 2
, V
OUT 3
, V
OUT 4
10
TYPICAL APPLICATIO
N
S
U
13
LTC1665/LTC1660
TYPICAL APPLICATIO
N
S
U
An 8-Channel Bipolar Output Voltage Circuit Configuration
V
OUT D
±
5V
5V
R
R
1665/60 TA01
2
15
1
GND
V
OUT A
V
OUT B
V
OUT C
V
OUT D
REF
CS/LD
CLK
3-WIRE
SERIAL
INTERFACE
V
CC
V
OUT H
V
OUT G
V
OUT F
V
OUT E
CLR
D
OUT
D
IN
16
DAC A
DAC H
3
14
DAC B
DAC G
4
13
DAC C
DAC F
5
7
6
8
10
11
9
12
DAC D
DAC E
ADDRESS
DECODER
CONTROL
LOGIC
SHIFT REGISTER
U1
LTC1660
14
13
12
+
U2D
LT1491
V
OUT C
±
5V
R
R
8
9
10
+
U2C
LT1491
V
OUT B
±
5V
R
R
7
6
5
+
U2B
LT1491
V
OUT A
±
5V
R
0.1
µ
F
0.1
µ
F
V
S
+
V
S
R
1
2
4
11
3
+
U2A
LT1491
0.1
µ
F
V
OUT E
±
5V
14
13
12
+
U3D
LT1491
V
OUT F
±
5V
8
9
10
+
U3C
LT1491
V
OUT G
±
5V
7
6
5
+
U3B
LT1491
V
OUT H
±
5V
R
0.1
µ
F
0.1
µ
F
V
S
+
V
S
R
R
R
R
R
R
R
1
2
4
11
3
+
U3A
LT1491
CODE
0
512
1023
V
OUT X
5V
0V
+4.99V
14
LTC1665/LTC1660
PACKAGE DESCRIPTIO
N
U
Dimensions in inches (millimeters) unless otherwise noted.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
GN16 (SSOP) 1098
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1
2
3
4
5
6
7
8
0.229 0.244
(5.817 6.198)
0.150 0.157**
(3.810 3.988)
16 15 14 13
0.189 0.196*
(4.801 4.978)
12 11 10 9
0.016 0.050
(0.406 1.270)
0.015
±
0.004
(0.38
±
0.10)
×
45
°
0
°
8
°
TYP
0.007 0.0098
(0.178 0.249)
0.053 0.068
(1.351 1.727)
0.008 0.012
(0.203 0.305)
0.004 0.0098
(0.102 0.249)
0.0250
(0.635)
BSC
0.009
(0.229)
REF
15
LTC1665/LTC1660
PACKAGE DESCRIPTIO
N
U
Dimensions in inches (millimeters) unless otherwise noted.
N Package
16-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
N16 1098
0.255
±
0.015*
(6.477
±
0.381)
0.770*
(19.558)
MAX
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0.020
(0.508)
MIN
0.125
(3.175)
MIN
0.130
±
0.005
(3.302
±
0.127)
0.065
(1.651)
TYP
0.045 0.065
(1.143 1.651)
0.018
±
0.003
(0.457
±
0.076)
0.100
(2.54)
BSC
0.009 0.015
(0.229 0.381)
0.300 0.325
(7.620 8.255)
0.325
+0.035
0.015
+0.889
0.381
8.255
(
)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
16
LTC1665/LTC1660
©
LINEAR TECHNOLOGY CORPORATION 1999
166560f LT/TP 0999 4K · PRINTED IN THE USA
TYPICAL APPLICATIO
N
U
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507
q
www.linear-tech.com
PART NUMBER
DESCRIPTION
COMMENTS
LTC1661
Dual 10-Bit V
OUT
DAC in 8-Lead MSOP Package
V
CC
= 2.7V to 5.5V Micropower Rail-to-Rail Output
LTC1663
Single 10-Bit V
OUT
DAC in SOT-23 Package
V
CC
= 2.7V to 5.5V, Internal Reference, 60
µ
A
LTC1446/LTC1446L
Dual 12-Bit V
OUT
DACs in SO-8 Package with Internal Reference
LTC1446: V
CC
= 4.5V to 5.5V, V
OUT
= 0V to 4.095V
LTC1446L: V
CC
= 2.7V to 5.5V, V
OUT
= 0V to 2.5V
LTC1448
Dual 12-Bit V
OUT
DAC in SO-8 Package
V
CC
= 2.7V to 5.5V, External Reference Can Be Tied to V
CC
LTC1454/LTC1454L
Dual 12-Bit V
OUT
DACs in SO-16 Package with Added Functionality
LTC1454: V
CC
= 4.5V to 5.5V, V
OUT
= 0V to 4.095V
LTC1454L: V
CC
= 2.7V to 5.5V, V
OUT
= 0V to 2.5V
LTC1458/LTC1458L
Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality
LTC1458: V
CC
= 4.5V to 5.5V, V
OUT
= 0V to 4.095V
LTC1458L: V
CC
= 2.7V to 5.5V, V
OUT
= 0V to 2.5V
LTC1590
Dual 12-Bit I
OUT
DAC in SO-16 Package
V
CC
= 4.5V to 5.5V, 4-Quadrant Multiplication
LTC1659
Single Rail-to-Rail 12-Bit V
OUT
DAC in 8-Lead MSOP Package
Low Power Multiplying V
OUT
DAC. Output Swings from
V
CC
: 2.7V to 5.5V
GND to REF. REF Input Can Be Tied to V
CC
LT1460
Micropower Precision Series Reference, 2.5V, 5V, 10V Versions
0.075% Max, 10ppm/
°
C Max, Only 130
µ
A Supply Current
RELATED PARTS
A Pin Driver V
H
and V
L
Adjustment Circuit for ATE Applications
2
6
16
11
DAC A
CLR
V
CC
REF
5V
U1 LTC1660
0.1
µ
F
0.1
µ
F
0.1
µ
F
V
A
3
V
H
= V
H
+
V
H
V
L
= V
L
+
V
L
V
L
1
2
V
H
(FROM MAIN DAC)
V
L
(FROM MAIN DAC)
10V
5V
R
G
50k
R
F
5k
V
B
V
C
V
D
GND
1665/60 TA03
3
DAC B
0.1
µ
F
R
G
50k
R
G
50k
R
G
50k
+
U2A
LT1369
QUAD
0.1
µ
F
5
7
6
R
F
5k
R
F
5k
R
F
5k
LOGIC
DRIVE
PIN DRIVER
(1 OF 2)
DAC C
DAC D
DAC H
DAC G
DAC F
DAC E
CS/LD
SCK
D
IN
4
5
8
1
9
7
+
U2B
LT1369
QUAD
V
L
V
OUT
V
H
CODE A
512
512
512
CODE B
1023
512
0
V
H
,
V
L
250mV
0
+ 250mV
V
A
= V
C
= 2.5V
For Resistor Values Shown:
Adjustment Range =
±
250mV
Adjustment Step Size = 500
µ
V
Note: DACs E Through H Can Be
Configured for a Second Pin Driver
With U2C and U2D of the LT1369
V
H
= V
H
+
(V
A
V
B
)
R
F
R
G
V
L
= V
L
+
(V
C
V
D
)
R
F
R
G
V
H
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